gwj / at91sam9263 · Commits

Commit ee8ae9e42a84f0243af3961f376e3d2dfc2dfbe6

Authored by blueswir1
1 parent eca8f888

Update ppc-dis.c from binutils from 4th July, 2007, just before GPLv3 switch 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6583 c046a42c-6fe2-441c-8c8c-71466251a162
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ppc-dis.c
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1 /* ppc-dis.c -- Disassemble PowerPC instructions 1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 - Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005 2 + Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc. 3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 4 Written by Ian Lance Taylor, Cygnus Support
5 5
@@ -22,8 +22,8 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US @@ -22,8 +22,8 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
22 #define BFD_DEFAULT_TARGET_SIZE 64 22 #define BFD_DEFAULT_TARGET_SIZE 64
23 23
24 /* ppc.h -- Header file for PowerPC opcode table 24 /* ppc.h -- Header file for PowerPC opcode table
25 - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005  
26 - Free Software Foundation, Inc. 25 + Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
  26 + 2007 Free Software Foundation, Inc.
27 Written by Ian Lance Taylor, Cygnus Support 27 Written by Ian Lance Taylor, Cygnus Support
28 28
29 This file is part of GDB, GAS, and the GNU binutils. 29 This file is part of GDB, GAS, and the GNU binutils.
@@ -155,10 +155,16 @@ extern const int powerpc_num_opcodes; @@ -155,10 +155,16 @@ extern const int powerpc_num_opcodes;
155 #define PPC_OPCODE_RFMCI 0x800000 155 #define PPC_OPCODE_RFMCI 0x800000
156 156
157 /* Opcode is only supported by Power5 architecture. */ 157 /* Opcode is only supported by Power5 architecture. */
158 -#define PPC_OPCODE_POWER5 0x1000000 158 +#define PPC_OPCODE_POWER5 0x1000000
159 159
160 /* Opcode is supported by PowerPC e300 family. */ 160 /* Opcode is supported by PowerPC e300 family. */
161 -#define PPC_OPCODE_E300 0x2000000 161 +#define PPC_OPCODE_E300 0x2000000
  162 +
  163 +/* Opcode is only supported by Power6 architecture. */
  164 +#define PPC_OPCODE_POWER6 0x4000000
  165 +
  166 +/* Opcode is only supported by PowerPC Cell family. */
  167 +#define PPC_OPCODE_CELL 0x8000000
162 168
163 /* A macro to extract the major opcode from an instruction. */ 169 /* A macro to extract the major opcode from an instruction. */
164 #define PPC_OP(i) (((i) >> 26) & 0x3f) 170 #define PPC_OP(i) (((i) >> 26) & 0x3f)
@@ -167,20 +173,21 @@ extern const int powerpc_num_opcodes; @@ -167,20 +173,21 @@ extern const int powerpc_num_opcodes;
167 173
168 struct powerpc_operand 174 struct powerpc_operand
169 { 175 {
170 - /* The number of bits in the operand. */  
171 - int bits; 176 + /* A bitmask of bits in the operand. */
  177 + unsigned int bitm;
172 178
173 - /* How far the operand is left shifted in the instruction. */ 179 + /* How far the operand is left shifted in the instruction.
  180 + -1 to indicate that BITM and SHIFT cannot be used to determine
  181 + where the operand goes in the insn. */
174 int shift; 182 int shift;
175 183
176 /* Insertion function. This is used by the assembler. To insert an 184 /* Insertion function. This is used by the assembler. To insert an
177 operand value into an instruction, check this field. 185 operand value into an instruction, check this field.
178 186
179 If it is NULL, execute 187 If it is NULL, execute
180 - i |= (op & ((1 << o->bits) - 1)) << o->shift; 188 + i |= (op & o->bitm) << o->shift;
181 (i is the instruction which we are filling in, o is a pointer to 189 (i is the instruction which we are filling in, o is a pointer to
182 - this structure, and op is the opcode value; this assumes twos  
183 - complement arithmetic). 190 + this structure, and op is the operand value).
184 191
185 If this field is not NULL, then simply call it with the 192 If this field is not NULL, then simply call it with the
186 instruction and the operand value. It will return the new value 193 instruction and the operand value. It will return the new value
@@ -196,12 +203,11 @@ struct powerpc_operand @@ -196,12 +203,11 @@ struct powerpc_operand
196 extract this operand type from an instruction, check this field. 203 extract this operand type from an instruction, check this field.
197 204
198 If it is NULL, compute 205 If it is NULL, compute
199 - op = ((i) >> o->shift) & ((1 << o->bits) - 1);  
200 - if ((o->flags & PPC_OPERAND_SIGNED) != 0  
201 - && (op & (1 << (o->bits - 1))) != 0)  
202 - op -= 1 << o->bits; 206 + op = (i >> o->shift) & o->bitm;
  207 + if ((o->flags & PPC_OPERAND_SIGNED) != 0)
  208 + sign_extend (op);
203 (i is the instruction, o is a pointer to this structure, and op 209 (i is the instruction, o is a pointer to this structure, and op
204 - is the result; this assumes twos complement arithmetic). 210 + is the result).
205 211
206 If this field is not NULL, then simply call it with the 212 If this field is not NULL, then simply call it with the
207 instruction value. It will return the value of the operand. If 213 instruction value. It will return the value of the operand. If
@@ -219,17 +225,18 @@ struct powerpc_operand @@ -219,17 +225,18 @@ struct powerpc_operand
219 the operands field of the powerpc_opcodes table. */ 225 the operands field of the powerpc_opcodes table. */
220 226
221 extern const struct powerpc_operand powerpc_operands[]; 227 extern const struct powerpc_operand powerpc_operands[];
  228 +extern const unsigned int num_powerpc_operands;
222 229
223 /* Values defined for the flags field of a struct powerpc_operand. */ 230 /* Values defined for the flags field of a struct powerpc_operand. */
224 231
225 /* This operand takes signed values. */ 232 /* This operand takes signed values. */
226 -#define PPC_OPERAND_SIGNED (01) 233 +#define PPC_OPERAND_SIGNED (0x1)
227 234
228 /* This operand takes signed values, but also accepts a full positive 235 /* This operand takes signed values, but also accepts a full positive
229 range of values when running in 32 bit mode. That is, if bits is 236 range of values when running in 32 bit mode. That is, if bits is
230 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 237 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
231 this flag is ignored. */ 238 this flag is ignored. */
232 -#define PPC_OPERAND_SIGNOPT (02) 239 +#define PPC_OPERAND_SIGNOPT (0x2)
233 240
234 /* This operand does not actually exist in the assembler input. This 241 /* This operand does not actually exist in the assembler input. This
235 is used to support extended mnemonics such as mr, for which two 242 is used to support extended mnemonics such as mr, for which two
@@ -237,14 +244,14 @@ extern const struct powerpc_operand powerpc_operands[]; @@ -237,14 +244,14 @@ extern const struct powerpc_operand powerpc_operands[];
237 insert function with any op value. The disassembler should call 244 insert function with any op value. The disassembler should call
238 the extract function, ignore the return value, and check the value 245 the extract function, ignore the return value, and check the value
239 placed in the valid argument. */ 246 placed in the valid argument. */
240 -#define PPC_OPERAND_FAKE (04) 247 +#define PPC_OPERAND_FAKE (0x4)
241 248
242 /* The next operand should be wrapped in parentheses rather than 249 /* The next operand should be wrapped in parentheses rather than
243 separated from this one by a comma. This is used for the load and 250 separated from this one by a comma. This is used for the load and
244 store instructions which want their operands to look like 251 store instructions which want their operands to look like
245 reg,displacement(reg) 252 reg,displacement(reg)
246 */ 253 */
247 -#define PPC_OPERAND_PARENS (010) 254 +#define PPC_OPERAND_PARENS (0x8)
248 255
249 /* This operand may use the symbolic names for the CR fields, which 256 /* This operand may use the symbolic names for the CR fields, which
250 are 257 are
@@ -253,26 +260,26 @@ extern const struct powerpc_operand powerpc_operands[]; @@ -253,26 +260,26 @@ extern const struct powerpc_operand powerpc_operands[];
253 cr4 4 cr5 5 cr6 6 cr7 7 260 cr4 4 cr5 5 cr6 6 cr7 7
254 These may be combined arithmetically, as in cr2*4+gt. These are 261 These may be combined arithmetically, as in cr2*4+gt. These are
255 only supported on the PowerPC, not the POWER. */ 262 only supported on the PowerPC, not the POWER. */
256 -#define PPC_OPERAND_CR (020) 263 +#define PPC_OPERAND_CR (0x10)
257 264
258 /* This operand names a register. The disassembler uses this to print 265 /* This operand names a register. The disassembler uses this to print
259 register names with a leading 'r'. */ 266 register names with a leading 'r'. */
260 -#define PPC_OPERAND_GPR (040) 267 +#define PPC_OPERAND_GPR (0x20)
261 268
262 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 269 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
263 -#define PPC_OPERAND_GPR_0 (0100) 270 +#define PPC_OPERAND_GPR_0 (0x40)
264 271
265 /* This operand names a floating point register. The disassembler 272 /* This operand names a floating point register. The disassembler
266 prints these with a leading 'f'. */ 273 prints these with a leading 'f'. */
267 -#define PPC_OPERAND_FPR (0200) 274 +#define PPC_OPERAND_FPR (0x80)
268 275
269 /* This operand is a relative branch displacement. The disassembler 276 /* This operand is a relative branch displacement. The disassembler
270 prints these symbolically if possible. */ 277 prints these symbolically if possible. */
271 -#define PPC_OPERAND_RELATIVE (0400) 278 +#define PPC_OPERAND_RELATIVE (0x100)
272 279
273 /* This operand is an absolute branch address. The disassembler 280 /* This operand is an absolute branch address. The disassembler
274 prints these symbolically if possible. */ 281 prints these symbolically if possible. */
275 -#define PPC_OPERAND_ABSOLUTE (01000) 282 +#define PPC_OPERAND_ABSOLUTE (0x200)
276 283
277 /* This operand is optional, and is zero if omitted. This is used for 284 /* This operand is optional, and is zero if omitted. This is used for
278 example, in the optional BF field in the comparison instructions. The 285 example, in the optional BF field in the comparison instructions. The
@@ -280,7 +287,7 @@ extern const struct powerpc_operand powerpc_operands[]; @@ -280,7 +287,7 @@ extern const struct powerpc_operand powerpc_operands[];
280 and the number of operands remaining for the opcode, and decide 287 and the number of operands remaining for the opcode, and decide
281 whether this operand is present or not. The disassembler should 288 whether this operand is present or not. The disassembler should
282 print this operand out only if it is not zero. */ 289 print this operand out only if it is not zero. */
283 -#define PPC_OPERAND_OPTIONAL (02000) 290 +#define PPC_OPERAND_OPTIONAL (0x400)
284 291
285 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 292 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
286 is omitted, then for the next operand use this operand value plus 293 is omitted, then for the next operand use this operand value plus
@@ -288,24 +295,27 @@ extern const struct powerpc_operand powerpc_operands[]; @@ -288,24 +295,27 @@ extern const struct powerpc_operand powerpc_operands[];
288 hack is needed because the Power rotate instructions can take 295 hack is needed because the Power rotate instructions can take
289 either 4 or 5 operands. The disassembler should print this operand 296 either 4 or 5 operands. The disassembler should print this operand
290 out regardless of the PPC_OPERAND_OPTIONAL field. */ 297 out regardless of the PPC_OPERAND_OPTIONAL field. */
291 -#define PPC_OPERAND_NEXT (04000) 298 +#define PPC_OPERAND_NEXT (0x800)
292 299
293 /* This operand should be regarded as a negative number for the 300 /* This operand should be regarded as a negative number for the
294 purposes of overflow checking (i.e., the normal most negative 301 purposes of overflow checking (i.e., the normal most negative
295 number is disallowed and one more than the normal most positive 302 number is disallowed and one more than the normal most positive
296 number is allowed). This flag will only be set for a signed 303 number is allowed). This flag will only be set for a signed
297 operand. */ 304 operand. */
298 -#define PPC_OPERAND_NEGATIVE (010000) 305 +#define PPC_OPERAND_NEGATIVE (0x1000)
299 306
300 /* This operand names a vector unit register. The disassembler 307 /* This operand names a vector unit register. The disassembler
301 prints these with a leading 'v'. */ 308 prints these with a leading 'v'. */
302 -#define PPC_OPERAND_VR (020000) 309 +#define PPC_OPERAND_VR (0x2000)
303 310
304 /* This operand is for the DS field in a DS form instruction. */ 311 /* This operand is for the DS field in a DS form instruction. */
305 -#define PPC_OPERAND_DS (040000) 312 +#define PPC_OPERAND_DS (0x4000)
306 313
307 /* This operand is for the DQ field in a DQ form instruction. */ 314 /* This operand is for the DQ field in a DQ form instruction. */
308 -#define PPC_OPERAND_DQ (0100000) 315 +#define PPC_OPERAND_DQ (0x8000)
  316 +
  317 +/* Valid range of operand is 0..n rather than 0..n-1. */
  318 +#define PPC_OPERAND_PLUS1 (0x10000)
309 319
310 /* The POWER and PowerPC assemblers use a few macros. We keep them 320 /* The POWER and PowerPC assemblers use a few macros. We keep them
311 with the operands table for simplicity. The macro table is an 321 with the operands table for simplicity. The macro table is an
@@ -335,7 +345,7 @@ extern const int powerpc_num_macros; @@ -335,7 +345,7 @@ extern const int powerpc_num_macros;
335 345
336 /* ppc-opc.c -- PowerPC opcode list 346 /* ppc-opc.c -- PowerPC opcode list
337 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 347 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
338 - 2005 Free Software Foundation, Inc. 348 + 2005, 2006, 2007 Free Software Foundation, Inc.
339 Written by Ian Lance Taylor, Cygnus Support 349 Written by Ian Lance Taylor, Cygnus Support
340 350
341 This file is part of GDB, GAS, and the GNU binutils. 351 This file is part of GDB, GAS, and the GNU binutils.
@@ -372,8 +382,6 @@ static unsigned long insert_bat (unsigned long, long, int, const char **); @@ -372,8 +382,6 @@ static unsigned long insert_bat (unsigned long, long, int, const char **);
372 static long extract_bat (unsigned long, int, int *); 382 static long extract_bat (unsigned long, int, int *);
373 static unsigned long insert_bba (unsigned long, long, int, const char **); 383 static unsigned long insert_bba (unsigned long, long, int, const char **);
374 static long extract_bba (unsigned long, int, int *); 384 static long extract_bba (unsigned long, int, int *);
375 -static unsigned long insert_bd (unsigned long, long, int, const char **);  
376 -static long extract_bd (unsigned long, int, int *);  
377 static unsigned long insert_bdm (unsigned long, long, int, const char **); 385 static unsigned long insert_bdm (unsigned long, long, int, const char **);
378 static long extract_bdm (unsigned long, int, int *); 386 static long extract_bdm (unsigned long, int, int *);
379 static unsigned long insert_bdp (unsigned long, long, int, const char **); 387 static unsigned long insert_bdp (unsigned long, long, int, const char **);
@@ -382,23 +390,12 @@ static unsigned long insert_bo (unsigned long, long, int, const char **); @@ -382,23 +390,12 @@ static unsigned long insert_bo (unsigned long, long, int, const char **);
382 static long extract_bo (unsigned long, int, int *); 390 static long extract_bo (unsigned long, int, int *);
383 static unsigned long insert_boe (unsigned long, long, int, const char **); 391 static unsigned long insert_boe (unsigned long, long, int, const char **);
384 static long extract_boe (unsigned long, int, int *); 392 static long extract_boe (unsigned long, int, int *);
385 -static unsigned long insert_dq (unsigned long, long, int, const char **);  
386 -static long extract_dq (unsigned long, int, int *);  
387 -static unsigned long insert_ds (unsigned long, long, int, const char **);  
388 -static long extract_ds (unsigned long, int, int *);  
389 -static unsigned long insert_de (unsigned long, long, int, const char **);  
390 -static long extract_de (unsigned long, int, int *);  
391 -static unsigned long insert_des (unsigned long, long, int, const char **);  
392 -static long extract_des (unsigned long, int, int *);  
393 static unsigned long insert_fxm (unsigned long, long, int, const char **); 393 static unsigned long insert_fxm (unsigned long, long, int, const char **);
394 static long extract_fxm (unsigned long, int, int *); 394 static long extract_fxm (unsigned long, int, int *);
395 -static unsigned long insert_li (unsigned long, long, int, const char **);  
396 -static long extract_li (unsigned long, int, int *);  
397 static unsigned long insert_mbe (unsigned long, long, int, const char **); 395 static unsigned long insert_mbe (unsigned long, long, int, const char **);
398 static long extract_mbe (unsigned long, int, int *); 396 static long extract_mbe (unsigned long, int, int *);
399 static unsigned long insert_mb6 (unsigned long, long, int, const char **); 397 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
400 static long extract_mb6 (unsigned long, int, int *); 398 static long extract_mb6 (unsigned long, int, int *);
401 -static unsigned long insert_nb (unsigned long, long, int, const char **);  
402 static long extract_nb (unsigned long, int, int *); 399 static long extract_nb (unsigned long, int, int *);
403 static unsigned long insert_nsi (unsigned long, long, int, const char **); 400 static unsigned long insert_nsi (unsigned long, long, int, const char **);
404 static long extract_nsi (unsigned long, int, int *); 401 static long extract_nsi (unsigned long, int, int *);
@@ -408,8 +405,6 @@ static unsigned long insert_raq (unsigned long, long, int, const char **); @@ -408,8 +405,6 @@ static unsigned long insert_raq (unsigned long, long, int, const char **);
408 static unsigned long insert_ras (unsigned long, long, int, const char **); 405 static unsigned long insert_ras (unsigned long, long, int, const char **);
409 static unsigned long insert_rbs (unsigned long, long, int, const char **); 406 static unsigned long insert_rbs (unsigned long, long, int, const char **);
410 static long extract_rbs (unsigned long, int, int *); 407 static long extract_rbs (unsigned long, int, int *);
411 -static unsigned long insert_rsq (unsigned long, long, int, const char **);  
412 -static unsigned long insert_rtq (unsigned long, long, int, const char **);  
413 static unsigned long insert_sh6 (unsigned long, long, int, const char **); 408 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
414 static long extract_sh6 (unsigned long, int, int *); 409 static long extract_sh6 (unsigned long, int, int *);
415 static unsigned long insert_spr (unsigned long, long, int, const char **); 410 static unsigned long insert_spr (unsigned long, long, int, const char **);
@@ -418,16 +413,10 @@ static unsigned long insert_sprg (unsigned long, long, int, const char **); @@ -418,16 +413,10 @@ static unsigned long insert_sprg (unsigned long, long, int, const char **);
418 static long extract_sprg (unsigned long, int, int *); 413 static long extract_sprg (unsigned long, int, int *);
419 static unsigned long insert_tbr (unsigned long, long, int, const char **); 414 static unsigned long insert_tbr (unsigned long, long, int, const char **);
420 static long extract_tbr (unsigned long, int, int *); 415 static long extract_tbr (unsigned long, int, int *);
421 -static unsigned long insert_ev2 (unsigned long, long, int, const char **);  
422 -static long extract_ev2 (unsigned long, int, int *);  
423 -static unsigned long insert_ev4 (unsigned long, long, int, const char **);  
424 -static long extract_ev4 (unsigned long, int, int *);  
425 -static unsigned long insert_ev8 (unsigned long, long, int, const char **);  
426 -static long extract_ev8 (unsigned long, int, int *);  
427 416
428 /* The operands table. 417 /* The operands table.
429 418
430 - The fields are bits, shift, insert, extract, flags. 419 + The fields are bitm, shift, insert, extract, flags.
431 420
432 We used to put parens around the various additions, like the one 421 We used to put parens around the various additions, like the one
433 for BA just below. However, that caused trouble with feeble 422 for BA just below. However, that caused trouble with feeble
@@ -445,302 +434,298 @@ const struct powerpc_operand powerpc_operands[] = @@ -445,302 +434,298 @@ const struct powerpc_operand powerpc_operands[] =
445 434
446 /* The BA field in an XL form instruction. */ 435 /* The BA field in an XL form instruction. */
447 #define BA UNUSED + 1 436 #define BA UNUSED + 1
448 -#define BA_MASK (0x1f << 16)  
449 - { 5, 16, NULL, NULL, PPC_OPERAND_CR }, 437 + /* The BI field in a B form or XL form instruction. */
  438 +#define BI BA
  439 +#define BI_MASK (0x1f << 16)
  440 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
450 441
451 /* The BA field in an XL form instruction when it must be the same 442 /* The BA field in an XL form instruction when it must be the same
452 as the BT field in the same instruction. */ 443 as the BT field in the same instruction. */
453 #define BAT BA + 1 444 #define BAT BA + 1
454 - { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 445 + { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
455 446
456 /* The BB field in an XL form instruction. */ 447 /* The BB field in an XL form instruction. */
457 #define BB BAT + 1 448 #define BB BAT + 1
458 #define BB_MASK (0x1f << 11) 449 #define BB_MASK (0x1f << 11)
459 - { 5, 11, NULL, NULL, PPC_OPERAND_CR }, 450 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
460 451
461 /* The BB field in an XL form instruction when it must be the same 452 /* The BB field in an XL form instruction when it must be the same
462 as the BA field in the same instruction. */ 453 as the BA field in the same instruction. */
463 #define BBA BB + 1 454 #define BBA BB + 1
464 - { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 455 + { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
465 456
466 /* The BD field in a B form instruction. The lower two bits are 457 /* The BD field in a B form instruction. The lower two bits are
467 forced to zero. */ 458 forced to zero. */
468 #define BD BBA + 1 459 #define BD BBA + 1
469 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 460 + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
470 461
471 /* The BD field in a B form instruction when absolute addressing is 462 /* The BD field in a B form instruction when absolute addressing is
472 used. */ 463 used. */
473 #define BDA BD + 1 464 #define BDA BD + 1
474 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 465 + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
475 466
476 /* The BD field in a B form instruction when the - modifier is used. 467 /* The BD field in a B form instruction when the - modifier is used.
477 This sets the y bit of the BO field appropriately. */ 468 This sets the y bit of the BO field appropriately. */
478 #define BDM BDA + 1 469 #define BDM BDA + 1
479 - { 16, 0, insert_bdm, extract_bdm, 470 + { 0xfffc, 0, insert_bdm, extract_bdm,
480 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 471 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
481 472
482 /* The BD field in a B form instruction when the - modifier is used 473 /* The BD field in a B form instruction when the - modifier is used
483 and absolute address is used. */ 474 and absolute address is used. */
484 #define BDMA BDM + 1 475 #define BDMA BDM + 1
485 - { 16, 0, insert_bdm, extract_bdm, 476 + { 0xfffc, 0, insert_bdm, extract_bdm,
486 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 477 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
487 478
488 /* The BD field in a B form instruction when the + modifier is used. 479 /* The BD field in a B form instruction when the + modifier is used.
489 This sets the y bit of the BO field appropriately. */ 480 This sets the y bit of the BO field appropriately. */
490 #define BDP BDMA + 1 481 #define BDP BDMA + 1
491 - { 16, 0, insert_bdp, extract_bdp, 482 + { 0xfffc, 0, insert_bdp, extract_bdp,
492 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 483 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
493 484
494 /* The BD field in a B form instruction when the + modifier is used 485 /* The BD field in a B form instruction when the + modifier is used
495 and absolute addressing is used. */ 486 and absolute addressing is used. */
496 #define BDPA BDP + 1 487 #define BDPA BDP + 1
497 - { 16, 0, insert_bdp, extract_bdp, 488 + { 0xfffc, 0, insert_bdp, extract_bdp,
498 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 489 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
499 490
500 /* The BF field in an X or XL form instruction. */ 491 /* The BF field in an X or XL form instruction. */
501 #define BF BDPA + 1 492 #define BF BDPA + 1
502 - { 3, 23, NULL, NULL, PPC_OPERAND_CR }, 493 + /* The CRFD field in an X form instruction. */
  494 +#define CRFD BF
  495 + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
  496 +
  497 + /* The BF field in an X or XL form instruction. */
  498 +#define BFF BF + 1
  499 + { 0x7, 23, NULL, NULL, 0 },
503 500
504 /* An optional BF field. This is used for comparison instructions, 501 /* An optional BF field. This is used for comparison instructions,
505 in which an omitted BF field is taken as zero. */ 502 in which an omitted BF field is taken as zero. */
506 -#define OBF BF + 1  
507 - { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 503 +#define OBF BFF + 1
  504 + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
508 505
509 /* The BFA field in an X or XL form instruction. */ 506 /* The BFA field in an X or XL form instruction. */
510 #define BFA OBF + 1 507 #define BFA OBF + 1
511 - { 3, 18, NULL, NULL, PPC_OPERAND_CR },  
512 -  
513 - /* The BI field in a B form or XL form instruction. */  
514 -#define BI BFA + 1  
515 -#define BI_MASK (0x1f << 16)  
516 - { 5, 16, NULL, NULL, PPC_OPERAND_CR }, 508 + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
517 509
518 /* The BO field in a B form instruction. Certain values are 510 /* The BO field in a B form instruction. Certain values are
519 illegal. */ 511 illegal. */
520 -#define BO BI + 1 512 +#define BO BFA + 1
521 #define BO_MASK (0x1f << 21) 513 #define BO_MASK (0x1f << 21)
522 - { 5, 21, insert_bo, extract_bo, 0 }, 514 + { 0x1f, 21, insert_bo, extract_bo, 0 },
523 515
524 /* The BO field in a B form instruction when the + or - modifier is 516 /* The BO field in a B form instruction when the + or - modifier is
525 used. This is like the BO field, but it must be even. */ 517 used. This is like the BO field, but it must be even. */
526 #define BOE BO + 1 518 #define BOE BO + 1
527 - { 5, 21, insert_boe, extract_boe, 0 }, 519 + { 0x1e, 21, insert_boe, extract_boe, 0 },
528 520
529 #define BH BOE + 1 521 #define BH BOE + 1
530 - { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 522 + { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
531 523
532 /* The BT field in an X or XL form instruction. */ 524 /* The BT field in an X or XL form instruction. */
533 #define BT BH + 1 525 #define BT BH + 1
534 - { 5, 21, NULL, NULL, PPC_OPERAND_CR }, 526 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
535 527
536 /* The condition register number portion of the BI field in a B form 528 /* The condition register number portion of the BI field in a B form
537 or XL form instruction. This is used for the extended 529 or XL form instruction. This is used for the extended
538 conditional branch mnemonics, which set the lower two bits of the 530 conditional branch mnemonics, which set the lower two bits of the
539 BI field. This field is optional. */ 531 BI field. This field is optional. */
540 #define CR BT + 1 532 #define CR BT + 1
541 - { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 533 + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
542 534
543 /* The CRB field in an X form instruction. */ 535 /* The CRB field in an X form instruction. */
544 #define CRB CR + 1 536 #define CRB CR + 1
545 - { 5, 6, NULL, NULL, 0 },  
546 -  
547 - /* The CRFD field in an X form instruction. */  
548 -#define CRFD CRB + 1  
549 - { 3, 23, NULL, NULL, PPC_OPERAND_CR }, 537 + /* The MB field in an M form instruction. */
  538 +#define MB CRB
  539 +#define MB_MASK (0x1f << 6)
  540 + { 0x1f, 6, NULL, NULL, 0 },
550 541
551 /* The CRFS field in an X form instruction. */ 542 /* The CRFS field in an X form instruction. */
552 -#define CRFS CRFD + 1  
553 - { 3, 0, NULL, NULL, PPC_OPERAND_CR }, 543 +#define CRFS CRB + 1
  544 + { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
554 545
555 /* The CT field in an X form instruction. */ 546 /* The CT field in an X form instruction. */
556 #define CT CRFS + 1 547 #define CT CRFS + 1
557 - { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 548 + /* The MO field in an mbar instruction. */
  549 +#define MO CT
  550 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
558 551
559 /* The D field in a D form instruction. This is a displacement off 552 /* The D field in a D form instruction. This is a displacement off
560 a register, and implies that the next operand is a register in 553 a register, and implies that the next operand is a register in
561 parentheses. */ 554 parentheses. */
562 #define D CT + 1 555 #define D CT + 1
563 - { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 556 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
564 557
565 /* The DE field in a DE form instruction. This is like D, but is 12 558 /* The DE field in a DE form instruction. This is like D, but is 12
566 bits only. */ 559 bits only. */
567 #define DE D + 1 560 #define DE D + 1
568 - { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, 561 + { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
569 562
570 /* The DES field in a DES form instruction. This is like DS, but is 14 563 /* The DES field in a DES form instruction. This is like DS, but is 14
571 bits only (12 stored.) */ 564 bits only (12 stored.) */
572 #define DES DE + 1 565 #define DES DE + 1
573 - { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 566 + { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
574 567
575 /* The DQ field in a DQ form instruction. This is like D, but the 568 /* The DQ field in a DQ form instruction. This is like D, but the
576 lower four bits are forced to zero. */ 569 lower four bits are forced to zero. */
577 #define DQ DES + 1 570 #define DQ DES + 1
578 - { 16, 0, insert_dq, extract_dq,  
579 - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 571 + { 0xfff0, 0, NULL, NULL,
  572 + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
580 573
581 /* The DS field in a DS form instruction. This is like D, but the 574 /* The DS field in a DS form instruction. This is like D, but the
582 lower two bits are forced to zero. */ 575 lower two bits are forced to zero. */
583 #define DS DQ + 1 576 #define DS DQ + 1
584 - { 16, 0, insert_ds, extract_ds,  
585 - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 577 + { 0xfffc, 0, NULL, NULL,
  578 + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
586 579
587 /* The E field in a wrteei instruction. */ 580 /* The E field in a wrteei instruction. */
588 #define E DS + 1 581 #define E DS + 1
589 - { 1, 15, NULL, NULL, 0 }, 582 + { 0x1, 15, NULL, NULL, 0 },
590 583
591 /* The FL1 field in a POWER SC form instruction. */ 584 /* The FL1 field in a POWER SC form instruction. */
592 #define FL1 E + 1 585 #define FL1 E + 1
593 - { 4, 12, NULL, NULL, 0 }, 586 + /* The U field in an X form instruction. */
  587 +#define U FL1
  588 + { 0xf, 12, NULL, NULL, 0 },
594 589
595 /* The FL2 field in a POWER SC form instruction. */ 590 /* The FL2 field in a POWER SC form instruction. */
596 #define FL2 FL1 + 1 591 #define FL2 FL1 + 1
597 - { 3, 2, NULL, NULL, 0 }, 592 + { 0x7, 2, NULL, NULL, 0 },
598 593
599 /* The FLM field in an XFL form instruction. */ 594 /* The FLM field in an XFL form instruction. */
600 #define FLM FL2 + 1 595 #define FLM FL2 + 1
601 - { 8, 17, NULL, NULL, 0 }, 596 + { 0xff, 17, NULL, NULL, 0 },
602 597
603 /* The FRA field in an X or A form instruction. */ 598 /* The FRA field in an X or A form instruction. */
604 #define FRA FLM + 1 599 #define FRA FLM + 1
605 #define FRA_MASK (0x1f << 16) 600 #define FRA_MASK (0x1f << 16)
606 - { 5, 16, NULL, NULL, PPC_OPERAND_FPR }, 601 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
607 602
608 /* The FRB field in an X or A form instruction. */ 603 /* The FRB field in an X or A form instruction. */
609 #define FRB FRA + 1 604 #define FRB FRA + 1
610 #define FRB_MASK (0x1f << 11) 605 #define FRB_MASK (0x1f << 11)
611 - { 5, 11, NULL, NULL, PPC_OPERAND_FPR }, 606 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
612 607
613 /* The FRC field in an A form instruction. */ 608 /* The FRC field in an A form instruction. */
614 #define FRC FRB + 1 609 #define FRC FRB + 1
615 #define FRC_MASK (0x1f << 6) 610 #define FRC_MASK (0x1f << 6)
616 - { 5, 6, NULL, NULL, PPC_OPERAND_FPR }, 611 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
617 612
618 /* The FRS field in an X form instruction or the FRT field in a D, X 613 /* The FRS field in an X form instruction or the FRT field in a D, X
619 or A form instruction. */ 614 or A form instruction. */
620 #define FRS FRC + 1 615 #define FRS FRC + 1
621 #define FRT FRS 616 #define FRT FRS
622 - { 5, 21, NULL, NULL, PPC_OPERAND_FPR }, 617 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
623 618
624 /* The FXM field in an XFX instruction. */ 619 /* The FXM field in an XFX instruction. */
625 #define FXM FRS + 1 620 #define FXM FRS + 1
626 -#define FXM_MASK (0xff << 12)  
627 - { 8, 12, insert_fxm, extract_fxm, 0 }, 621 + { 0xff, 12, insert_fxm, extract_fxm, 0 },
628 622
629 /* Power4 version for mfcr. */ 623 /* Power4 version for mfcr. */
630 #define FXM4 FXM + 1 624 #define FXM4 FXM + 1
631 - { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 625 + { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
632 626
633 /* The L field in a D or X form instruction. */ 627 /* The L field in a D or X form instruction. */
634 #define L FXM4 + 1 628 #define L FXM4 + 1
635 - { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 629 + { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
636 630
637 /* The LEV field in a POWER SVC form instruction. */ 631 /* The LEV field in a POWER SVC form instruction. */
638 #define SVC_LEV L + 1 632 #define SVC_LEV L + 1
639 - { 7, 5, NULL, NULL, 0 }, 633 + { 0x7f, 5, NULL, NULL, 0 },
640 634
641 /* The LEV field in an SC form instruction. */ 635 /* The LEV field in an SC form instruction. */
642 #define LEV SVC_LEV + 1 636 #define LEV SVC_LEV + 1
643 - { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 637 + { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
644 638
645 /* The LI field in an I form instruction. The lower two bits are 639 /* The LI field in an I form instruction. The lower two bits are
646 forced to zero. */ 640 forced to zero. */
647 #define LI LEV + 1 641 #define LI LEV + 1
648 - { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 642 + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
649 643
650 /* The LI field in an I form instruction when used as an absolute 644 /* The LI field in an I form instruction when used as an absolute
651 address. */ 645 address. */
652 #define LIA LI + 1 646 #define LIA LI + 1
653 - { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 647 + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
654 648
655 /* The LS field in an X (sync) form instruction. */ 649 /* The LS field in an X (sync) form instruction. */
656 #define LS LIA + 1 650 #define LS LIA + 1
657 - { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },  
658 -  
659 - /* The MB field in an M form instruction. */  
660 -#define MB LS + 1  
661 -#define MB_MASK (0x1f << 6)  
662 - { 5, 6, NULL, NULL, 0 }, 651 + { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
663 652
664 /* The ME field in an M form instruction. */ 653 /* The ME field in an M form instruction. */
665 -#define ME MB + 1 654 +#define ME LS + 1
666 #define ME_MASK (0x1f << 1) 655 #define ME_MASK (0x1f << 1)
667 - { 5, 1, NULL, NULL, 0 }, 656 + { 0x1f, 1, NULL, NULL, 0 },
668 657
669 /* The MB and ME fields in an M form instruction expressed a single 658 /* The MB and ME fields in an M form instruction expressed a single
670 operand which is a bitmask indicating which bits to select. This 659 operand which is a bitmask indicating which bits to select. This
671 is a two operand form using PPC_OPERAND_NEXT. See the 660 is a two operand form using PPC_OPERAND_NEXT. See the
672 description in opcode/ppc.h for what this means. */ 661 description in opcode/ppc.h for what this means. */
673 #define MBE ME + 1 662 #define MBE ME + 1
674 - { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },  
675 - { 32, 0, insert_mbe, extract_mbe, 0 }, 663 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
  664 + { -1, 0, insert_mbe, extract_mbe, 0 },
676 665
677 /* The MB or ME field in an MD or MDS form instruction. The high 666 /* The MB or ME field in an MD or MDS form instruction. The high
678 bit is wrapped to the low end. */ 667 bit is wrapped to the low end. */
679 #define MB6 MBE + 2 668 #define MB6 MBE + 2
680 #define ME6 MB6 669 #define ME6 MB6
681 #define MB6_MASK (0x3f << 5) 670 #define MB6_MASK (0x3f << 5)
682 - { 6, 5, insert_mb6, extract_mb6, 0 },  
683 -  
684 - /* The MO field in an mbar instruction. */  
685 -#define MO MB6 + 1  
686 - { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 671 + { 0x3f, 5, insert_mb6, extract_mb6, 0 },
687 672
688 /* The NB field in an X form instruction. The value 32 is stored as 673 /* The NB field in an X form instruction. The value 32 is stored as
689 0. */ 674 0. */
690 -#define NB MO + 1  
691 - { 6, 11, insert_nb, extract_nb, 0 }, 675 +#define NB MB6 + 1
  676 + { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
692 677
693 /* The NSI field in a D form instruction. This is the same as the 678 /* The NSI field in a D form instruction. This is the same as the
694 SI field, only negated. */ 679 SI field, only negated. */
695 #define NSI NB + 1 680 #define NSI NB + 1
696 - { 16, 0, insert_nsi, extract_nsi, 681 + { 0xffff, 0, insert_nsi, extract_nsi,
697 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 682 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
698 683
699 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 684 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
700 #define RA NSI + 1 685 #define RA NSI + 1
701 #define RA_MASK (0x1f << 16) 686 #define RA_MASK (0x1f << 16)
702 - { 5, 16, NULL, NULL, PPC_OPERAND_GPR }, 687 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
703 688
704 /* As above, but 0 in the RA field means zero, not r0. */ 689 /* As above, but 0 in the RA field means zero, not r0. */
705 #define RA0 RA + 1 690 #define RA0 RA + 1
706 - { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 691 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
707 692
708 /* The RA field in the DQ form lq instruction, which has special 693 /* The RA field in the DQ form lq instruction, which has special
709 value restrictions. */ 694 value restrictions. */
710 #define RAQ RA0 + 1 695 #define RAQ RA0 + 1
711 - { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, 696 + { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
712 697
713 /* The RA field in a D or X form instruction which is an updating 698 /* The RA field in a D or X form instruction which is an updating
714 load, which means that the RA field may not be zero and may not 699 load, which means that the RA field may not be zero and may not
715 equal the RT field. */ 700 equal the RT field. */
716 #define RAL RAQ + 1 701 #define RAL RAQ + 1
717 - { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, 702 + { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
718 703
719 /* The RA field in an lmw instruction, which has special value 704 /* The RA field in an lmw instruction, which has special value
720 restrictions. */ 705 restrictions. */
721 #define RAM RAL + 1 706 #define RAM RAL + 1
722 - { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, 707 + { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
723 708
724 /* The RA field in a D or X form instruction which is an updating 709 /* The RA field in a D or X form instruction which is an updating
725 store or an updating floating point load, which means that the RA 710 store or an updating floating point load, which means that the RA
726 field may not be zero. */ 711 field may not be zero. */
727 #define RAS RAM + 1 712 #define RAS RAM + 1
728 - { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, 713 + { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
729 714
730 /* The RA field of the tlbwe instruction, which is optional. */ 715 /* The RA field of the tlbwe instruction, which is optional. */
731 #define RAOPT RAS + 1 716 #define RAOPT RAS + 1
732 - { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 717 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
733 718
734 /* The RB field in an X, XO, M, or MDS form instruction. */ 719 /* The RB field in an X, XO, M, or MDS form instruction. */
735 #define RB RAOPT + 1 720 #define RB RAOPT + 1
736 #define RB_MASK (0x1f << 11) 721 #define RB_MASK (0x1f << 11)
737 - { 5, 11, NULL, NULL, PPC_OPERAND_GPR }, 722 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
738 723
739 /* The RB field in an X form instruction when it must be the same as 724 /* The RB field in an X form instruction when it must be the same as
740 the RS field in the instruction. This is used for extended 725 the RS field in the instruction. This is used for extended
741 mnemonics like mr. */ 726 mnemonics like mr. */
742 #define RBS RB + 1 727 #define RBS RB + 1
743 - { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 728 + { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
744 729
745 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 730 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
746 instruction or the RT field in a D, DS, X, XFX or XO form 731 instruction or the RT field in a D, DS, X, XFX or XO form
@@ -748,153 +733,168 @@ const struct powerpc_operand powerpc_operands[] = @@ -748,153 +733,168 @@ const struct powerpc_operand powerpc_operands[] =
748 #define RS RBS + 1 733 #define RS RBS + 1
749 #define RT RS 734 #define RT RS
750 #define RT_MASK (0x1f << 21) 735 #define RT_MASK (0x1f << 21)
751 - { 5, 21, NULL, NULL, PPC_OPERAND_GPR }, 736 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
752 737
753 - /* The RS field of the DS form stq instruction, which has special  
754 - value restrictions. */ 738 + /* The RS and RT fields of the DS form stq instruction, which have
  739 + special value restrictions. */
755 #define RSQ RS + 1 740 #define RSQ RS + 1
756 - { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },  
757 -  
758 - /* The RT field of the DQ form lq instruction, which has special  
759 - value restrictions. */  
760 -#define RTQ RSQ + 1  
761 - { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 }, 741 +#define RTQ RSQ
  742 + { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
762 743
763 /* The RS field of the tlbwe instruction, which is optional. */ 744 /* The RS field of the tlbwe instruction, which is optional. */
764 -#define RSO RTQ + 1 745 +#define RSO RSQ + 1
765 #define RTO RSO 746 #define RTO RSO
766 - { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 747 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
767 748
768 /* The SH field in an X or M form instruction. */ 749 /* The SH field in an X or M form instruction. */
769 #define SH RSO + 1 750 #define SH RSO + 1
770 #define SH_MASK (0x1f << 11) 751 #define SH_MASK (0x1f << 11)
771 - { 5, 11, NULL, NULL, 0 }, 752 + /* The other UIMM field in a EVX form instruction. */
  753 +#define EVUIMM SH
  754 + { 0x1f, 11, NULL, NULL, 0 },
772 755
773 /* The SH field in an MD form instruction. This is split. */ 756 /* The SH field in an MD form instruction. This is split. */
774 #define SH6 SH + 1 757 #define SH6 SH + 1
775 #define SH6_MASK ((0x1f << 11) | (1 << 1)) 758 #define SH6_MASK ((0x1f << 11) | (1 << 1))
776 - { 6, 1, insert_sh6, extract_sh6, 0 }, 759 + { 0x3f, -1, insert_sh6, extract_sh6, 0 },
777 760
778 /* The SH field of the tlbwe instruction, which is optional. */ 761 /* The SH field of the tlbwe instruction, which is optional. */
779 #define SHO SH6 + 1 762 #define SHO SH6 + 1
780 - { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL }, 763 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
781 764
782 /* The SI field in a D form instruction. */ 765 /* The SI field in a D form instruction. */
783 #define SI SHO + 1 766 #define SI SHO + 1
784 - { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 767 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
785 768
786 /* The SI field in a D form instruction when we accept a wide range 769 /* The SI field in a D form instruction when we accept a wide range
787 of positive values. */ 770 of positive values. */
788 #define SISIGNOPT SI + 1 771 #define SISIGNOPT SI + 1
789 - { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 772 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
790 773
791 /* The SPR field in an XFX form instruction. This is flipped--the 774 /* The SPR field in an XFX form instruction. This is flipped--the
792 lower 5 bits are stored in the upper 5 and vice- versa. */ 775 lower 5 bits are stored in the upper 5 and vice- versa. */
793 #define SPR SISIGNOPT + 1 776 #define SPR SISIGNOPT + 1
794 #define PMR SPR 777 #define PMR SPR
795 #define SPR_MASK (0x3ff << 11) 778 #define SPR_MASK (0x3ff << 11)
796 - { 10, 11, insert_spr, extract_spr, 0 }, 779 + { 0x3ff, 11, insert_spr, extract_spr, 0 },
797 780
798 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 781 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
799 #define SPRBAT SPR + 1 782 #define SPRBAT SPR + 1
800 #define SPRBAT_MASK (0x3 << 17) 783 #define SPRBAT_MASK (0x3 << 17)
801 - { 2, 17, NULL, NULL, 0 }, 784 + { 0x3, 17, NULL, NULL, 0 },
802 785
803 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 786 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
804 #define SPRG SPRBAT + 1 787 #define SPRG SPRBAT + 1
805 - { 5, 16, insert_sprg, extract_sprg, 0 }, 788 + { 0x1f, 16, insert_sprg, extract_sprg, 0 },
806 789
807 /* The SR field in an X form instruction. */ 790 /* The SR field in an X form instruction. */
808 #define SR SPRG + 1 791 #define SR SPRG + 1
809 - { 4, 16, NULL, NULL, 0 }, 792 + { 0xf, 16, NULL, NULL, 0 },
810 793
811 /* The STRM field in an X AltiVec form instruction. */ 794 /* The STRM field in an X AltiVec form instruction. */
812 #define STRM SR + 1 795 #define STRM SR + 1
813 -#define STRM_MASK (0x3 << 21)  
814 - { 2, 21, NULL, NULL, 0 }, 796 + { 0x3, 21, NULL, NULL, 0 },
815 797
816 /* The SV field in a POWER SC form instruction. */ 798 /* The SV field in a POWER SC form instruction. */
817 #define SV STRM + 1 799 #define SV STRM + 1
818 - { 14, 2, NULL, NULL, 0 }, 800 + { 0x3fff, 2, NULL, NULL, 0 },
819 801
820 /* The TBR field in an XFX form instruction. This is like the SPR 802 /* The TBR field in an XFX form instruction. This is like the SPR
821 field, but it is optional. */ 803 field, but it is optional. */
822 #define TBR SV + 1 804 #define TBR SV + 1
823 - { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 805 + { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
824 806
825 /* The TO field in a D or X form instruction. */ 807 /* The TO field in a D or X form instruction. */
826 #define TO TBR + 1 808 #define TO TBR + 1
827 #define TO_MASK (0x1f << 21) 809 #define TO_MASK (0x1f << 21)
828 - { 5, 21, NULL, NULL, 0 },  
829 -  
830 - /* The U field in an X form instruction. */  
831 -#define U TO + 1  
832 - { 4, 12, NULL, NULL, 0 }, 810 + { 0x1f, 21, NULL, NULL, 0 },
833 811
834 /* The UI field in a D form instruction. */ 812 /* The UI field in a D form instruction. */
835 -#define UI U + 1  
836 - { 16, 0, NULL, NULL, 0 }, 813 +#define UI TO + 1
  814 + { 0xffff, 0, NULL, NULL, 0 },
837 815
838 /* The VA field in a VA, VX or VXR form instruction. */ 816 /* The VA field in a VA, VX or VXR form instruction. */
839 #define VA UI + 1 817 #define VA UI + 1
840 -#define VA_MASK (0x1f << 16)  
841 - { 5, 16, NULL, NULL, PPC_OPERAND_VR }, 818 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
842 819
843 /* The VB field in a VA, VX or VXR form instruction. */ 820 /* The VB field in a VA, VX or VXR form instruction. */
844 #define VB VA + 1 821 #define VB VA + 1
845 -#define VB_MASK (0x1f << 11)  
846 - { 5, 11, NULL, NULL, PPC_OPERAND_VR }, 822 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
847 823
848 /* The VC field in a VA form instruction. */ 824 /* The VC field in a VA form instruction. */
849 #define VC VB + 1 825 #define VC VB + 1
850 -#define VC_MASK (0x1f << 6)  
851 - { 5, 6, NULL, NULL, PPC_OPERAND_VR }, 826 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
852 827
853 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 828 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
854 #define VD VC + 1 829 #define VD VC + 1
855 #define VS VD 830 #define VS VD
856 -#define VD_MASK (0x1f << 21)  
857 - { 5, 21, NULL, NULL, PPC_OPERAND_VR }, 831 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
858 832
859 /* The SIMM field in a VX form instruction. */ 833 /* The SIMM field in a VX form instruction. */
860 #define SIMM VD + 1 834 #define SIMM VD + 1
861 - { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 835 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
862 836
863 - /* The UIMM field in a VX form instruction. */ 837 + /* The UIMM field in a VX form instruction, and TE in Z form. */
864 #define UIMM SIMM + 1 838 #define UIMM SIMM + 1
865 - { 5, 16, NULL, NULL, 0 }, 839 +#define TE UIMM
  840 + { 0x1f, 16, NULL, NULL, 0 },
866 841
867 /* The SHB field in a VA form instruction. */ 842 /* The SHB field in a VA form instruction. */
868 #define SHB UIMM + 1 843 #define SHB UIMM + 1
869 - { 4, 6, NULL, NULL, 0 },  
870 -  
871 - /* The other UIMM field in a EVX form instruction. */  
872 -#define EVUIMM SHB + 1  
873 - { 5, 11, NULL, NULL, 0 }, 844 + { 0xf, 6, NULL, NULL, 0 },
874 845
875 /* The other UIMM field in a half word EVX form instruction. */ 846 /* The other UIMM field in a half word EVX form instruction. */
876 -#define EVUIMM_2 EVUIMM + 1  
877 - { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, 847 +#define EVUIMM_2 SHB + 1
  848 + { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
878 849
879 /* The other UIMM field in a word EVX form instruction. */ 850 /* The other UIMM field in a word EVX form instruction. */
880 #define EVUIMM_4 EVUIMM_2 + 1 851 #define EVUIMM_4 EVUIMM_2 + 1
881 - { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, 852 + { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
882 853
883 /* The other UIMM field in a double EVX form instruction. */ 854 /* The other UIMM field in a double EVX form instruction. */
884 #define EVUIMM_8 EVUIMM_4 + 1 855 #define EVUIMM_8 EVUIMM_4 + 1
885 - { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, 856 + { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
886 857
887 /* The WS field. */ 858 /* The WS field. */
888 #define WS EVUIMM_8 + 1 859 #define WS EVUIMM_8 + 1
889 -#define WS_MASK (0x7 << 11)  
890 - { 3, 11, NULL, NULL, 0 }, 860 + { 0x7, 11, NULL, NULL, 0 },
  861 +
  862 + /* The L field in an mtmsrd or A form instruction or W in an X form. */
  863 +#define A_L WS + 1
  864 +#define W A_L
  865 + { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
  866 +
  867 +#define RMC A_L + 1
  868 + { 0x3, 9, NULL, NULL, 0 },
  869 +
  870 +#define R RMC + 1
  871 + { 0x1, 16, NULL, NULL, 0 },
891 872
892 - /* The L field in an mtmsrd instruction */  
893 -#define MTMSRD_L WS + 1  
894 - { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 873 +#define SP R + 1
  874 + { 0x3, 19, NULL, NULL, 0 },
895 875
  876 +#define S SP + 1
  877 + { 0x1, 20, NULL, NULL, 0 },
  878 +
  879 + /* SH field starting at bit position 16. */
  880 +#define SH16 S + 1
  881 + /* The DCM and DGM fields in a Z form instruction. */
  882 +#define DCM SH16
  883 +#define DGM DCM
  884 + { 0x3f, 10, NULL, NULL, 0 },
  885 +
  886 + /* The EH field in larx instruction. */
  887 +#define EH SH16 + 1
  888 + { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
  889 +
  890 + /* The L field in an mtfsf or XFL form instruction. */
  891 +#define XFL_L EH + 1
  892 + { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
896 }; 893 };
897 894
  895 +const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
  896 + / sizeof (powerpc_operands[0]));
  897 +
898 /* The functions used to insert and extract complicated operands. */ 898 /* The functions used to insert and extract complicated operands. */
899 899
900 /* The BA field in an XL form instruction when it must be the same as 900 /* The BA field in an XL form instruction when it must be the same as
@@ -947,26 +947,6 @@ extract_bba (unsigned long insn, @@ -947,26 +947,6 @@ extract_bba (unsigned long insn,
947 return 0; 947 return 0;
948 } 948 }
949 949
950 -/* The BD field in a B form instruction. The lower two bits are  
951 - forced to zero. */  
952 -  
953 -static unsigned long  
954 -insert_bd (unsigned long insn,  
955 - long value,  
956 - int dialect ATTRIBUTE_UNUSED,  
957 - const char **errmsg ATTRIBUTE_UNUSED)  
958 -{  
959 - return insn | (value & 0xfffc);  
960 -}  
961 -  
962 -static long  
963 -extract_bd (unsigned long insn,  
964 - int dialect ATTRIBUTE_UNUSED,  
965 - int *invalid ATTRIBUTE_UNUSED)  
966 -{  
967 - return ((insn & 0xfffc) ^ 0x8000) - 0x8000;  
968 -}  
969 -  
970 /* The BD field in a B form instruction when the - modifier is used. 950 /* The BD field in a B form instruction when the - modifier is used.
971 This modifier means that the branch is not expected to be taken. 951 This modifier means that the branch is not expected to be taken.
972 For chips built to versions of the architecture prior to version 2 952 For chips built to versions of the architecture prior to version 2
@@ -978,7 +958,11 @@ extract_bd (unsigned long insn, @@ -978,7 +958,11 @@ extract_bd (unsigned long insn,
978 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 958 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
979 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 959 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
980 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 960 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
981 - for branch on CTR. We only handle the taken/not-taken hint here. */ 961 + for branch on CTR. We only handle the taken/not-taken hint here.
  962 + Note that we don't relax the conditions tested here when
  963 + disassembling with -Many because insns using extract_bdm and
  964 + extract_bdp always occur in pairs. One or the other will always
  965 + be valid. */
982 966
983 static unsigned long 967 static unsigned long
984 insert_bdm (unsigned long insn, 968 insert_bdm (unsigned long insn,
@@ -1069,10 +1053,11 @@ extract_bdp (unsigned long insn, @@ -1069,10 +1053,11 @@ extract_bdp (unsigned long insn,
1069 /* Check for legal values of a BO field. */ 1053 /* Check for legal values of a BO field. */
1070 1054
1071 static int 1055 static int
1072 -valid_bo (long value, int dialect) 1056 +valid_bo (long value, int dialect, int extract)
1073 { 1057 {
1074 if ((dialect & PPC_OPCODE_POWER4) == 0) 1058 if ((dialect & PPC_OPCODE_POWER4) == 0)
1075 { 1059 {
  1060 + int valid;
1076 /* Certain encodings have bits that are required to be zero. 1061 /* Certain encodings have bits that are required to be zero.
1077 These are (z must be zero, y may be anything): 1062 These are (z must be zero, y may be anything):
1078 001zy 1063 001zy
@@ -1085,36 +1070,43 @@ valid_bo (long value, int dialect) @@ -1085,36 +1070,43 @@ valid_bo (long value, int dialect)
1085 { 1070 {
1086 default: 1071 default:
1087 case 0: 1072 case 0:
1088 - return 1; 1073 + valid = 1;
  1074 + break;
1089 case 0x4: 1075 case 0x4:
1090 - return (value & 0x2) == 0; 1076 + valid = (value & 0x2) == 0;
  1077 + break;
1091 case 0x10: 1078 case 0x10:
1092 - return (value & 0x8) == 0; 1079 + valid = (value & 0x8) == 0;
  1080 + break;
1093 case 0x14: 1081 case 0x14:
1094 - return value == 0x14; 1082 + valid = value == 0x14;
  1083 + break;
1095 } 1084 }
  1085 + /* When disassembling with -Many, accept power4 encodings too. */
  1086 + if (valid
  1087 + || (dialect & PPC_OPCODE_ANY) == 0
  1088 + || !extract)
  1089 + return valid;
1096 } 1090 }
  1091 +
  1092 + /* Certain encodings have bits that are required to be zero.
  1093 + These are (z must be zero, a & t may be anything):
  1094 + 0000z
  1095 + 0001z
  1096 + 0100z
  1097 + 0101z
  1098 + 001at
  1099 + 011at
  1100 + 1a00t
  1101 + 1a01t
  1102 + 1z1zz
  1103 + */
  1104 + if ((value & 0x14) == 0)
  1105 + return (value & 0x1) == 0;
  1106 + else if ((value & 0x14) == 0x14)
  1107 + return value == 0x14;
1097 else 1108 else
1098 - {  
1099 - /* Certain encodings have bits that are required to be zero.  
1100 - These are (z must be zero, a & t may be anything):  
1101 - 0000z  
1102 - 0001z  
1103 - 0100z  
1104 - 0101z  
1105 - 001at  
1106 - 011at  
1107 - 1a00t  
1108 - 1a01t  
1109 - 1z1zz  
1110 - */  
1111 - if ((value & 0x14) == 0)  
1112 - return (value & 0x1) == 0;  
1113 - else if ((value & 0x14) == 0x14)  
1114 - return value == 0x14;  
1115 - else  
1116 - return 1;  
1117 - } 1109 + return 1;
1118 } 1110 }
1119 1111
1120 /* The BO field in a B form instruction. Warn about attempts to set 1112 /* The BO field in a B form instruction. Warn about attempts to set
@@ -1126,7 +1118,7 @@ insert_bo (unsigned long insn, @@ -1126,7 +1118,7 @@ insert_bo (unsigned long insn,
1126 int dialect, 1118 int dialect,
1127 const char **errmsg) 1119 const char **errmsg)
1128 { 1120 {
1129 - if (!valid_bo (value, dialect)) 1121 + if (!valid_bo (value, dialect, 0))
1130 *errmsg = _("invalid conditional option"); 1122 *errmsg = _("invalid conditional option");
1131 return insn | ((value & 0x1f) << 21); 1123 return insn | ((value & 0x1f) << 21);
1132 } 1124 }
@@ -1139,7 +1131,7 @@ extract_bo (unsigned long insn, @@ -1139,7 +1131,7 @@ extract_bo (unsigned long insn,
1139 long value; 1131 long value;
1140 1132
1141 value = (insn >> 21) & 0x1f; 1133 value = (insn >> 21) & 0x1f;
1142 - if (!valid_bo (value, dialect)) 1134 + if (!valid_bo (value, dialect, 1))
1143 *invalid = 1; 1135 *invalid = 1;
1144 return value; 1136 return value;
1145 } 1137 }
@@ -1154,7 +1146,7 @@ insert_boe (unsigned long insn, @@ -1154,7 +1146,7 @@ insert_boe (unsigned long insn,
1154 int dialect, 1146 int dialect,
1155 const char **errmsg) 1147 const char **errmsg)
1156 { 1148 {
1157 - if (!valid_bo (value, dialect)) 1149 + if (!valid_bo (value, dialect, 0))
1158 *errmsg = _("invalid conditional option"); 1150 *errmsg = _("invalid conditional option");
1159 else if ((value & 1) != 0) 1151 else if ((value & 1) != 0)
1160 *errmsg = _("attempt to set y bit when using + or - modifier"); 1152 *errmsg = _("attempt to set y bit when using + or - modifier");
@@ -1170,162 +1162,11 @@ extract_boe (unsigned long insn, @@ -1170,162 +1162,11 @@ extract_boe (unsigned long insn,
1170 long value; 1162 long value;
1171 1163
1172 value = (insn >> 21) & 0x1f; 1164 value = (insn >> 21) & 0x1f;
1173 - if (!valid_bo (value, dialect)) 1165 + if (!valid_bo (value, dialect, 1))
1174 *invalid = 1; 1166 *invalid = 1;
1175 return value & 0x1e; 1167 return value & 0x1e;
1176 } 1168 }
1177 1169
1178 -/* The DQ field in a DQ form instruction. This is like D, but the  
1179 - lower four bits are forced to zero. */  
1180 -  
1181 -static unsigned long  
1182 -insert_dq (unsigned long insn,  
1183 - long value,  
1184 - int dialect ATTRIBUTE_UNUSED,  
1185 - const char **errmsg)  
1186 -{  
1187 - if ((value & 0xf) != 0)  
1188 - *errmsg = _("offset not a multiple of 16");  
1189 - return insn | (value & 0xfff0);  
1190 -}  
1191 -  
1192 -static long  
1193 -extract_dq (unsigned long insn,  
1194 - int dialect ATTRIBUTE_UNUSED,  
1195 - int *invalid ATTRIBUTE_UNUSED)  
1196 -{  
1197 - return ((insn & 0xfff0) ^ 0x8000) - 0x8000;  
1198 -}  
1199 -  
1200 -static unsigned long  
1201 -insert_ev2 (unsigned long insn,  
1202 - long value,  
1203 - int dialect ATTRIBUTE_UNUSED,  
1204 - const char **errmsg)  
1205 -{  
1206 - if ((value & 1) != 0)  
1207 - *errmsg = _("offset not a multiple of 2");  
1208 - if ((value > 62) != 0)  
1209 - *errmsg = _("offset greater than 62");  
1210 - return insn | ((value & 0x3e) << 10);  
1211 -}  
1212 -  
1213 -static long  
1214 -extract_ev2 (unsigned long insn,  
1215 - int dialect ATTRIBUTE_UNUSED,  
1216 - int *invalid ATTRIBUTE_UNUSED)  
1217 -{  
1218 - return (insn >> 10) & 0x3e;  
1219 -}  
1220 -  
1221 -static unsigned long  
1222 -insert_ev4 (unsigned long insn,  
1223 - long value,  
1224 - int dialect ATTRIBUTE_UNUSED,  
1225 - const char **errmsg)  
1226 -{  
1227 - if ((value & 3) != 0)  
1228 - *errmsg = _("offset not a multiple of 4");  
1229 - if ((value > 124) != 0)  
1230 - *errmsg = _("offset greater than 124");  
1231 - return insn | ((value & 0x7c) << 9);  
1232 -}  
1233 -  
1234 -static long  
1235 -extract_ev4 (unsigned long insn,  
1236 - int dialect ATTRIBUTE_UNUSED,  
1237 - int *invalid ATTRIBUTE_UNUSED)  
1238 -{  
1239 - return (insn >> 9) & 0x7c;  
1240 -}  
1241 -  
1242 -static unsigned long  
1243 -insert_ev8 (unsigned long insn,  
1244 - long value,  
1245 - int dialect ATTRIBUTE_UNUSED,  
1246 - const char **errmsg)  
1247 -{  
1248 - if ((value & 7) != 0)  
1249 - *errmsg = _("offset not a multiple of 8");  
1250 - if ((value > 248) != 0)  
1251 - *errmsg = _("offset greater than 248");  
1252 - return insn | ((value & 0xf8) << 8);  
1253 -}  
1254 -  
1255 -static long  
1256 -extract_ev8 (unsigned long insn,  
1257 - int dialect ATTRIBUTE_UNUSED,  
1258 - int *invalid ATTRIBUTE_UNUSED)  
1259 -{  
1260 - return (insn >> 8) & 0xf8;  
1261 -}  
1262 -  
1263 -/* The DS field in a DS form instruction. This is like D, but the  
1264 - lower two bits are forced to zero. */  
1265 -  
1266 -static unsigned long  
1267 -insert_ds (unsigned long insn,  
1268 - long value,  
1269 - int dialect ATTRIBUTE_UNUSED,  
1270 - const char **errmsg)  
1271 -{  
1272 - if ((value & 3) != 0)  
1273 - *errmsg = _("offset not a multiple of 4");  
1274 - return insn | (value & 0xfffc);  
1275 -}  
1276 -  
1277 -static long  
1278 -extract_ds (unsigned long insn,  
1279 - int dialect ATTRIBUTE_UNUSED,  
1280 - int *invalid ATTRIBUTE_UNUSED)  
1281 -{  
1282 - return ((insn & 0xfffc) ^ 0x8000) - 0x8000;  
1283 -}  
1284 -  
1285 -/* The DE field in a DE form instruction. */  
1286 -  
1287 -static unsigned long  
1288 -insert_de (unsigned long insn,  
1289 - long value,  
1290 - int dialect ATTRIBUTE_UNUSED,  
1291 - const char **errmsg)  
1292 -{  
1293 - if (value > 2047 || value < -2048)  
1294 - *errmsg = _("offset not between -2048 and 2047");  
1295 - return insn | ((value << 4) & 0xfff0);  
1296 -}  
1297 -  
1298 -static long  
1299 -extract_de (unsigned long insn,  
1300 - int dialect ATTRIBUTE_UNUSED,  
1301 - int *invalid ATTRIBUTE_UNUSED)  
1302 -{  
1303 - return (insn & 0xfff0) >> 4;  
1304 -}  
1305 -  
1306 -/* The DES field in a DES form instruction. */  
1307 -  
1308 -static unsigned long  
1309 -insert_des (unsigned long insn,  
1310 - long value,  
1311 - int dialect ATTRIBUTE_UNUSED,  
1312 - const char **errmsg)  
1313 -{  
1314 - if (value > 8191 || value < -8192)  
1315 - *errmsg = _("offset not between -8192 and 8191");  
1316 - else if ((value & 3) != 0)  
1317 - *errmsg = _("offset not a multiple of 4");  
1318 - return insn | ((value << 2) & 0xfff0);  
1319 -}  
1320 -  
1321 -static long  
1322 -extract_des (unsigned long insn,  
1323 - int dialect ATTRIBUTE_UNUSED,  
1324 - int *invalid ATTRIBUTE_UNUSED)  
1325 -{  
1326 - return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;  
1327 -}  
1328 -  
1329 /* FXM mask in mfcr and mtcrf instructions. */ 1170 /* FXM mask in mfcr and mtcrf instructions. */
1330 1171
1331 static unsigned long 1172 static unsigned long
@@ -1398,28 +1239,6 @@ extract_fxm (unsigned long insn, @@ -1398,28 +1239,6 @@ extract_fxm (unsigned long insn,
1398 return mask; 1239 return mask;
1399 } 1240 }
1400 1241
1401 -/* The LI field in an I form instruction. The lower two bits are  
1402 - forced to zero. */  
1403 -  
1404 -static unsigned long  
1405 -insert_li (unsigned long insn,  
1406 - long value,  
1407 - int dialect ATTRIBUTE_UNUSED,  
1408 - const char **errmsg)  
1409 -{  
1410 - if ((value & 3) != 0)  
1411 - *errmsg = _("ignoring least significant bits in branch offset");  
1412 - return insn | (value & 0x3fffffc);  
1413 -}  
1414 -  
1415 -static long  
1416 -extract_li (unsigned long insn,  
1417 - int dialect ATTRIBUTE_UNUSED,  
1418 - int *invalid ATTRIBUTE_UNUSED)  
1419 -{  
1420 - return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;  
1421 -}  
1422 -  
1423 /* The MB and ME fields in an M form instruction expressed as a single 1242 /* The MB and ME fields in an M form instruction expressed as a single
1424 operand which is itself a bitmask. The extraction function always 1243 operand which is itself a bitmask. The extraction function always
1425 marks it as invalid, since we never want to recognize an 1244 marks it as invalid, since we never want to recognize an
@@ -1531,19 +1350,6 @@ extract_mb6 (unsigned long insn, @@ -1531,19 +1350,6 @@ extract_mb6 (unsigned long insn,
1531 /* The NB field in an X form instruction. The value 32 is stored as 1350 /* The NB field in an X form instruction. The value 32 is stored as
1532 0. */ 1351 0. */
1533 1352
1534 -static unsigned long  
1535 -insert_nb (unsigned long insn,  
1536 - long value,  
1537 - int dialect ATTRIBUTE_UNUSED,  
1538 - const char **errmsg)  
1539 -{  
1540 - if (value < 0 || value > 32)  
1541 - *errmsg = _("value out of range");  
1542 - if (value == 32)  
1543 - value = 0;  
1544 - return insn | ((value & 0x1f) << 11);  
1545 -}  
1546 -  
1547 static long 1353 static long
1548 extract_nb (unsigned long insn, 1354 extract_nb (unsigned long insn,
1549 int dialect ATTRIBUTE_UNUSED, 1355 int dialect ATTRIBUTE_UNUSED,
@@ -1666,34 +1472,6 @@ extract_rbs (unsigned long insn, @@ -1666,34 +1472,6 @@ extract_rbs (unsigned long insn,
1666 return 0; 1472 return 0;
1667 } 1473 }
1668 1474
1669 -/* The RT field of the DQ form lq instruction, which has special  
1670 - value restrictions. */  
1671 -  
1672 -static unsigned long  
1673 -insert_rtq (unsigned long insn,  
1674 - long value,  
1675 - int dialect ATTRIBUTE_UNUSED,  
1676 - const char **errmsg)  
1677 -{  
1678 - if ((value & 1) != 0)  
1679 - *errmsg = _("target register operand must be even");  
1680 - return insn | ((value & 0x1f) << 21);  
1681 -}  
1682 -  
1683 -/* The RS field of the DS form stq instruction, which has special  
1684 - value restrictions. */  
1685 -  
1686 -static unsigned long  
1687 -insert_rsq (unsigned long insn,  
1688 - long value ATTRIBUTE_UNUSED,  
1689 - int dialect ATTRIBUTE_UNUSED,  
1690 - const char **errmsg)  
1691 -{  
1692 - if ((value & 1) != 0)  
1693 - *errmsg = _("source register operand must be even");  
1694 - return insn | ((value & 0x1f) << 21);  
1695 -}  
1696 -  
1697 /* The SH field in an MD form instruction. This is split. */ 1475 /* The SH field in an MD form instruction. This is split. */
1698 1476
1699 static unsigned long 1477 static unsigned long
@@ -1839,6 +1617,9 @@ extract_tbr (unsigned long insn, @@ -1839,6 +1617,9 @@ extract_tbr (unsigned long insn,
1839 /* An A_MASK with the FRA and FRC fields fixed. */ 1617 /* An A_MASK with the FRA and FRC fields fixed. */
1840 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 1618 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1841 1619
  1620 +/* An AFRAFRC_MASK, but with L bit clear. */
  1621 +#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
  1622 +
1842 /* A B form instruction. */ 1623 /* A B form instruction. */
1843 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 1624 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1844 #define B_MASK B (0x3f, 1, 1) 1625 #define B_MASK B (0x3f, 1, 1)
@@ -1949,21 +1730,37 @@ extract_tbr (unsigned long insn, @@ -1949,21 +1730,37 @@ extract_tbr (unsigned long insn,
1949 /* An X form instruction. */ 1730 /* An X form instruction. */
1950 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1731 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1951 1732
  1733 +/* A Z form instruction. */
  1734 +#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
  1735 +
1952 /* An X form instruction with the RC bit specified. */ 1736 /* An X form instruction with the RC bit specified. */
1953 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 1737 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1954 1738
  1739 +/* A Z form instruction with the RC bit specified. */
  1740 +#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
  1741 +
1955 /* The mask for an X form instruction. */ 1742 /* The mask for an X form instruction. */
1956 #define X_MASK XRC (0x3f, 0x3ff, 1) 1743 #define X_MASK XRC (0x3f, 0x3ff, 1)
1957 1744
  1745 +/* The mask for a Z form instruction. */
  1746 +#define Z_MASK ZRC (0x3f, 0x1ff, 1)
  1747 +#define Z2_MASK ZRC (0x3f, 0xff, 1)
  1748 +
1958 /* An X_MASK with the RA field fixed. */ 1749 /* An X_MASK with the RA field fixed. */
1959 #define XRA_MASK (X_MASK | RA_MASK) 1750 #define XRA_MASK (X_MASK | RA_MASK)
1960 1751
  1752 +/* An XRA_MASK with the W field clear. */
  1753 +#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
  1754 +
1961 /* An X_MASK with the RB field fixed. */ 1755 /* An X_MASK with the RB field fixed. */
1962 #define XRB_MASK (X_MASK | RB_MASK) 1756 #define XRB_MASK (X_MASK | RB_MASK)
1963 1757
1964 /* An X_MASK with the RT field fixed. */ 1758 /* An X_MASK with the RT field fixed. */
1965 #define XRT_MASK (X_MASK | RT_MASK) 1759 #define XRT_MASK (X_MASK | RT_MASK)
1966 1760
  1761 +/* An XRT_MASK mask with the L bits clear. */
  1762 +#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
  1763 +
1967 /* An X_MASK with the RA and RB fields fixed. */ 1764 /* An X_MASK with the RA and RB fields fixed. */
1968 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 1765 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1969 1766
@@ -2000,13 +1797,16 @@ extract_tbr (unsigned long insn, @@ -2000,13 +1797,16 @@ extract_tbr (unsigned long insn,
2000 /* An X form sync instruction with everything filled in except the LS field. */ 1797 /* An X form sync instruction with everything filled in except the LS field. */
2001 #define XSYNC_MASK (0xff9fffff) 1798 #define XSYNC_MASK (0xff9fffff)
2002 1799
  1800 +/* An X_MASK, but with the EH bit clear. */
  1801 +#define XEH_MASK (X_MASK & ~((unsigned long )1))
  1802 +
2003 /* An X form AltiVec dss instruction. */ 1803 /* An X form AltiVec dss instruction. */
2004 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 1804 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2005 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 1805 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2006 1806
2007 /* An XFL form instruction. */ 1807 /* An XFL form instruction. */
2008 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 1808 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2009 -#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) 1809 +#define XFL_MASK XFL (0x3f, 0x3ff, 1)
2010 1810
2011 /* An X form isel instruction. */ 1811 /* An X form isel instruction. */
2012 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 1812 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
@@ -2082,7 +1882,7 @@ extract_tbr (unsigned long insn, @@ -2082,7 +1882,7 @@ extract_tbr (unsigned long insn,
2082 1882
2083 /* An XFX form instruction with the SPR field filled in except for the 1883 /* An XFX form instruction with the SPR field filled in except for the
2084 SPRG field. */ 1884 SPRG field. */
2085 -#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16)) 1885 +#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2086 1886
2087 /* An X form instruction with everything filled in except the E field. */ 1887 /* An X form instruction with everything filled in except the E field. */
2088 #define XE_MASK (0xffff7fff) 1888 #define XE_MASK (0xffff7fff)
@@ -2153,6 +1953,8 @@ extract_tbr (unsigned long insn, @@ -2153,6 +1953,8 @@ extract_tbr (unsigned long insn,
2153 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1953 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
2154 #define POWER4 PPC_OPCODE_POWER4 1954 #define POWER4 PPC_OPCODE_POWER4
2155 #define POWER5 PPC_OPCODE_POWER5 1955 #define POWER5 PPC_OPCODE_POWER5
  1956 +#define POWER6 PPC_OPCODE_POWER6
  1957 +#define CELL PPC_OPCODE_CELL
2156 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 1958 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
2157 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 1959 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
2158 #define PPC403 PPC_OPCODE_403 1960 #define PPC403 PPC_OPCODE_403
@@ -3344,16 +3146,23 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -3344,16 +3146,23 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3344 3146
3345 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, 3147 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3346 3148
3347 -{ "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } }, 3149 +{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
3348 3150
3349 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 3151 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3350 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, 3152 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3351 3153
  3154 +{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
  3155 +
3352 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, 3156 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3353 3157
  3158 +{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
  3159 +
3354 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, 3160 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3355 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, 3161 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3356 3162
  3163 +{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
  3164 +{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
  3165 +
3357 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, 3166 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3358 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, 3167 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3359 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3168 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
@@ -3504,8 +3313,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -3504,8 +3313,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3504 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3313 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3505 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3314 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3506 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3315 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3507 -{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },  
3508 -{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, 3316 +{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
  3317 +{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
3509 3318
3510 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3319 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3511 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3320 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
@@ -3651,10 +3460,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -3651,10 +3460,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3651 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, 3460 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3652 3461
3653 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, 3462 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3654 -{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } }, 3463 +{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3655 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, 3464 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3656 3465
3657 -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } }, 3466 +{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3658 3467
3659 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, 3468 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3660 3469
@@ -3747,9 +3556,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -3747,9 +3556,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3747 3556
3748 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, 3557 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3749 3558
3750 -{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } }, 3559 +{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3751 3560
3752 -{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, 3561 +{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
  3562 +{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
3753 3563
3754 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, 3564 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3755 3565
@@ -3831,12 +3641,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -3831,12 +3641,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3831 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, 3641 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3832 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, 3642 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3833 3643
  3644 +{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
  3645 +
3834 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, 3646 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3835 3647
3836 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, 3648 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3837 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3649 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3838 3650
3839 -{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, 3651 +{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
3840 3652
3841 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, 3653 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3842 3654
@@ -3846,6 +3658,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -3846,6 +3658,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3846 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, 3658 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3847 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, 3659 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3848 3660
  3661 +{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
  3662 +
3849 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, 3663 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3850 3664
3851 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3665 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
@@ -3952,7 +3766,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -3952,7 +3766,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
3952 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, 3766 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3953 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, 3767 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3954 3768
3955 -{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, 3769 +{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3956 3770
3957 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, 3771 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3958 3772
@@ -4033,6 +3847,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4033,6 +3847,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4033 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, 3847 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
4034 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, 3848 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
4035 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, 3849 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
  3850 +{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
4036 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, 3851 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
4037 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, 3852 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
4038 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, 3853 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
@@ -4254,12 +4069,18 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4254,12 +4069,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4254 4069
4255 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, 4070 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4256 4071
  4072 +{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
  4073 +
4257 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, 4074 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4258 4075
  4076 +{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
  4077 +
4259 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, 4078 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4260 4079
4261 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, 4080 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4262 4081
  4082 +{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
  4083 +
4263 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, 4084 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4264 4085
4265 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, 4086 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
@@ -4278,6 +4099,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4278,6 +4099,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4278 4099
4279 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, 4100 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4280 4101
  4102 +{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
  4103 +{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
  4104 +{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
  4105 +{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
  4106 +{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
  4107 +{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
  4108 +{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
4281 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, 4109 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4282 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, 4110 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4283 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, 4111 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
@@ -4349,6 +4177,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4349,6 +4177,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4349 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, 4177 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4350 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, 4178 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4351 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, 4179 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
  4180 +{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
4352 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, 4181 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4353 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, 4182 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4354 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, 4183 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
@@ -4536,6 +4365,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4536,6 +4365,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4536 4365
4537 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, 4366 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4538 4367
  4368 +{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
  4369 +
4539 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, 4370 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4540 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, 4371 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4541 4372
@@ -4585,6 +4416,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4585,6 +4416,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4585 4416
4586 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, 4417 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4587 4418
  4419 +{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
  4420 +
4588 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, 4421 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4589 4422
4590 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, 4423 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
@@ -4595,6 +4428,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4595,6 +4428,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4595 4428
4596 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, 4429 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4597 4430
  4431 +{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
  4432 +
4598 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, 4433 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4599 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, 4434 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4600 4435
@@ -4633,6 +4468,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4633,6 +4468,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4633 4468
4634 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4469 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4635 4470
  4471 +{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
  4472 +
4636 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, 4473 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4637 4474
4638 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, 4475 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
@@ -4647,6 +4484,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4647,6 +4484,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4647 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, 4484 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4648 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, 4485 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4649 4486
  4487 +{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
  4488 +
4650 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, 4489 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4651 4490
4652 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4491 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
@@ -4664,6 +4503,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4664,6 +4503,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4664 4503
4665 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, 4504 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4666 4505
  4506 +{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
  4507 +
4667 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, 4508 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4668 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, 4509 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4669 4510
@@ -4674,16 +4515,24 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4674,16 +4515,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4674 4515
4675 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, 4516 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4676 4517
  4518 +{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
  4519 +
4677 { "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 4520 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4678 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, 4521 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4679 4522
  4523 +{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
  4524 +
  4525 +{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
  4526 +
4680 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 4527 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4681 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 4528 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4682 -{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },  
4683 -{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, 4529 +{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
  4530 +{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
4684 4531
4685 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, 4532 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4686 4533
  4534 +{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
  4535 +
4687 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, 4536 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4688 4537
4689 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, 4538 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
@@ -4705,6 +4554,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4705,6 +4554,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4705 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, 4554 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4706 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 4555 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4707 4556
  4557 +{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
  4558 +
4708 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, 4559 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4709 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, 4560 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4710 4561
@@ -4720,6 +4571,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4720,6 +4571,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4720 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 4571 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4721 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, 4572 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4722 4573
  4574 +{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
  4575 +
4723 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 4576 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4724 4577
4725 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, 4578 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
@@ -4734,6 +4587,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4734,6 +4587,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4734 4587
4735 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, 4588 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4736 4589
  4590 +{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
  4591 +
4737 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, 4592 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4738 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4593 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4739 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4594 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
@@ -4753,6 +4608,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4753,6 +4608,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4753 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, 4608 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4754 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, 4609 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4755 4610
  4611 +/* New load/store left/right index vector instructions that are in the Cell only. */
  4612 +{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
  4613 +{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
  4614 +{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
  4615 +{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
  4616 +{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
  4617 +{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
  4618 +{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
  4619 +{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
  4620 +
4756 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, 4621 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4757 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4622 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4758 4623
@@ -4813,6 +4678,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4813,6 +4678,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4813 4678
4814 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4679 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4815 4680
  4681 +{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
  4682 +
4816 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4683 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4817 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4684 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4818 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4685 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
@@ -4834,6 +4701,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4834,6 +4701,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4834 4701
4835 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, 4702 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4836 4703
  4704 +{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4705 +{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4706 +
  4707 +{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4708 +{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4709 +
4837 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4710 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4838 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4711 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4839 4712
@@ -4846,14 +4719,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4846,14 +4719,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4846 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4719 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4847 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4720 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4848 4721
4849 -{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },  
4850 -{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4722 +{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
  4723 +{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4851 4724
4852 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4725 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4853 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4726 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4854 4727
4855 -{ "frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },  
4856 -{ "frsqrtes.",A(59,26,1), AFRAFRC_MASK, POWER5, { FRT, FRB } }, 4728 +{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
  4729 +{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4857 4730
4858 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4731 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4859 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4732 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
@@ -4867,10 +4740,73 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4867,10 +4740,73 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4867 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4740 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4868 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4741 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4869 4742
  4743 +{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4744 +{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4745 +
  4746 +{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4747 +{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4748 +
  4749 +{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4750 +{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4751 +
  4752 +{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
  4753 +{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
  4754 +
  4755 +{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4756 +{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4757 +
  4758 +{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4759 +{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4760 +
  4761 +{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
  4762 +
  4763 +{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
  4764 +{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
  4765 +{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
  4766 +
  4767 +{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4768 +{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4769 +
  4770 +{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
  4771 +{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
  4772 +
  4773 +{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
  4774 +{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
  4775 +
  4776 +{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
  4777 +{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
  4778 +
  4779 +{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
  4780 +{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
  4781 +
  4782 +{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4783 +{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4784 +
  4785 +{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4786 +{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4787 +
  4788 +{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
  4789 +
  4790 +{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
  4791 +
  4792 +{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
  4793 +{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
  4794 +
  4795 +{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
  4796 +{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
  4797 +
  4798 +{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
  4799 +{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
  4800 +
  4801 +{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4802 +{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4803 +
4870 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 4804 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4871 4805
4872 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 4806 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4873 4807
  4808 +{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
  4809 +
4874 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4810 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4875 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4811 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4876 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 4812 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
@@ -4892,6 +4828,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4892,6 +4828,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4892 4828
4893 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4829 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4894 4830
  4831 +{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4832 +{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4833 +
  4834 +{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4835 +{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4836 +
  4837 +{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4838 +{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4839 +
4895 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 4840 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4896 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, 4841 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4897 4842
@@ -4926,16 +4871,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4926,16 +4871,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4926 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4871 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4927 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4872 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4928 4873
4929 -{ "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },  
4930 -{ "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB } }, 4874 +{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
  4875 +{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4931 4876
4932 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4877 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4933 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4878 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4934 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4879 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4935 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4880 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4936 4881
4937 -{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },  
4938 -{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4882 +{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
  4883 +{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4939 4884
4940 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4885 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4941 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4886 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
@@ -4959,6 +4904,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4959,6 +4904,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4959 4904
4960 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4905 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4961 4906
  4907 +{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4908 +{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4909 +
  4910 +{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4911 +{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4912 +
4962 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, 4913 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4963 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, 4914 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4964 4915
@@ -4967,21 +4918,54 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4967,21 +4918,54 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4967 4918
4968 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, 4919 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4969 4920
  4921 +{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4922 +{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4923 +
  4924 +{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
  4925 +{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
  4926 +
4970 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, 4927 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4971 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, 4928 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4972 4929
4973 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, 4930 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4974 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, 4931 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4975 4932
4976 -{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },  
4977 -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 4933 +{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4934 +{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
  4935 +
  4936 +{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4937 +{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4938 +
  4939 +{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
  4940 +
  4941 +{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
  4942 +{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4978 4943
4979 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, 4944 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4980 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, 4945 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4981 4946
  4947 +{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
  4948 +{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
  4949 +{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
  4950 +
  4951 +{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4952 +{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
  4953 +
  4954 +{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
  4955 +{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
  4956 +
4982 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, 4957 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4983 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, 4958 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4984 4959
  4960 +{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
  4961 +{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
  4962 +
  4963 +{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
  4964 +{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
  4965 +
  4966 +{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
  4967 +{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
  4968 +
4985 { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, 4969 { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4986 { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } }, 4970 { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4987 { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } }, 4971 { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
@@ -4991,11 +4975,27 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -4991,11 +4975,27 @@ const struct powerpc_opcode powerpc_opcodes[] = {
4991 { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } }, 4975 { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4992 { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } }, 4976 { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4993 4977
  4978 +{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4979 +{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4980 +
  4981 +{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  4982 +{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  4983 +
4994 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, 4984 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4995 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, 4985 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4996 4986
4997 -{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },  
4998 -{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, 4987 +{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
  4988 +
  4989 +{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
  4990 +
  4991 +{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
  4992 +{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
  4993 +
  4994 +{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
  4995 +{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
  4996 +
  4997 +{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
  4998 +{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4999 4999
5000 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, 5000 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
5001 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, 5001 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
@@ -5003,9 +5003,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { @@ -5003,9 +5003,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
5003 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, 5003 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
5004 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, 5004 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
5005 5005
  5006 +{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
  5007 +{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
  5008 +
5006 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, 5009 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
5007 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, 5010 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
5008 5011
  5012 +{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
  5013 +{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
  5014 +
5009 }; 5015 };
5010 5016
5011 const int powerpc_num_opcodes = 5017 const int powerpc_num_opcodes =
@@ -5068,6 +5074,7 @@ const struct powerpc_macro powerpc_macros[] = { @@ -5068,6 +5074,7 @@ const struct powerpc_macro powerpc_macros[] = {
5068 const int powerpc_num_macros = 5074 const int powerpc_num_macros =
5069 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 5075 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
5070 5076
  5077 +
5071 /* This file provides several disassembler functions, all of which use 5078 /* This file provides several disassembler functions, all of which use
5072 the disassembler interface defined in dis-asm.h. Several functions 5079 the disassembler interface defined in dis-asm.h. Several functions
5073 are provided because this file handles disassembly for the PowerPC 5080 are provided because this file handles disassembly for the PowerPC
@@ -5105,6 +5112,10 @@ powerpc_dialect (struct disassemble_info *info) @@ -5105,6 +5112,10 @@ powerpc_dialect (struct disassemble_info *info)
5105 else if (info->disassembler_options 5112 else if (info->disassembler_options
5106 && strstr (info->disassembler_options, "e300") != NULL) 5113 && strstr (info->disassembler_options, "e300") != NULL)
5107 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON; 5114 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
  5115 + else if (info->disassembler_options
  5116 + && strstr (info->disassembler_options, "440") != NULL)
  5117 + dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
  5118 + | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
5108 else 5119 else
5109 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC 5120 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
5110 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); 5121 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
@@ -5118,6 +5129,14 @@ powerpc_dialect (struct disassemble_info *info) @@ -5118,6 +5129,14 @@ powerpc_dialect (struct disassemble_info *info)
5118 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; 5129 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
5119 5130
5120 if (info->disassembler_options 5131 if (info->disassembler_options
  5132 + && strstr (info->disassembler_options, "cell") != NULL)
  5133 + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
  5134 +
  5135 + if (info->disassembler_options
  5136 + && strstr (info->disassembler_options, "power6") != NULL)
  5137 + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
  5138 +
  5139 + if (info->disassembler_options
5121 && strstr (info->disassembler_options, "any") != NULL) 5140 && strstr (info->disassembler_options, "any") != NULL)
5122 dialect |= PPC_OPCODE_ANY; 5141 dialect |= PPC_OPCODE_ANY;
5123 5142
@@ -5167,6 +5186,56 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) @@ -5167,6 +5186,56 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
5167 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); 5186 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
5168 } 5187 }
5169 5188
  5189 +/* Extract the operand value from the PowerPC or POWER instruction. */
  5190 +
  5191 +static long
  5192 +operand_value_powerpc (const struct powerpc_operand *operand,
  5193 + unsigned long insn, int dialect)
  5194 +{
  5195 + long value;
  5196 + int invalid;
  5197 + /* Extract the value from the instruction. */
  5198 + if (operand->extract)
  5199 + value = (*operand->extract) (insn, dialect, &invalid);
  5200 + else
  5201 + {
  5202 + value = (insn >> operand->shift) & operand->bitm;
  5203 + if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
  5204 + {
  5205 + /* BITM is always some number of zeros followed by some
  5206 + number of ones, followed by some numer of zeros. */
  5207 + unsigned long top = operand->bitm;
  5208 + /* top & -top gives the rightmost 1 bit, so this
  5209 + fills in any trailing zeros. */
  5210 + top |= (top & -top) - 1;
  5211 + top &= ~(top >> 1);
  5212 + value = (value ^ top) - top;
  5213 + }
  5214 + }
  5215 +
  5216 + return value;
  5217 +}
  5218 +
  5219 +/* Determine whether the optional operand(s) should be printed. */
  5220 +
  5221 +static int
  5222 +skip_optional_operands (const unsigned char *opindex,
  5223 + unsigned long insn, int dialect)
  5224 +{
  5225 + const struct powerpc_operand *operand;
  5226 +
  5227 + for (; *opindex != 0; opindex++)
  5228 + {
  5229 + operand = &powerpc_operands[*opindex];
  5230 + if ((operand->flags & PPC_OPERAND_NEXT) != 0
  5231 + || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
  5232 + && operand_value_powerpc (operand, insn, dialect) != 0))
  5233 + return 0;
  5234 + }
  5235 +
  5236 + return 1;
  5237 +}
  5238 +
5170 /* Print a PowerPC or POWER instruction. */ 5239 /* Print a PowerPC or POWER instruction. */
5171 5240
5172 static int 5241 static int
@@ -5212,6 +5281,7 @@ print_insn_powerpc (bfd_vma memaddr, @@ -5212,6 +5281,7 @@ print_insn_powerpc (bfd_vma memaddr,
5212 int invalid; 5281 int invalid;
5213 int need_comma; 5282 int need_comma;
5214 int need_paren; 5283 int need_paren;
  5284 + int skip_optional;
5215 5285
5216 table_op = PPC_OP (opcode->opcode); 5286 table_op = PPC_OP (opcode->opcode);
5217 if (op < table_op) 5287 if (op < table_op)
@@ -5245,6 +5315,7 @@ print_insn_powerpc (bfd_vma memaddr, @@ -5245,6 +5315,7 @@ print_insn_powerpc (bfd_vma memaddr,
5245 /* Now extract and print the operands. */ 5315 /* Now extract and print the operands. */
5246 need_comma = 0; 5316 need_comma = 0;
5247 need_paren = 0; 5317 need_paren = 0;
  5318 + skip_optional = -1;
5248 for (opindex = opcode->operands; *opindex != 0; opindex++) 5319 for (opindex = opcode->operands; *opindex != 0; opindex++)
5249 { 5320 {
5250 long value; 5321 long value;
@@ -5257,23 +5328,18 @@ print_insn_powerpc (bfd_vma memaddr, @@ -5257,23 +5328,18 @@ print_insn_powerpc (bfd_vma memaddr,
5257 if ((operand->flags & PPC_OPERAND_FAKE) != 0) 5328 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
5258 continue; 5329 continue;
5259 5330
5260 - /* Extract the value from the instruction. */  
5261 - if (operand->extract)  
5262 - value = (*operand->extract) (insn, dialect, &invalid);  
5263 - else 5331 + /* If all of the optional operands have the value zero,
  5332 + then don't print any of them. */
  5333 + if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
5264 { 5334 {
5265 - value = (insn >> operand->shift) & ((1 << operand->bits) - 1);  
5266 - if ((operand->flags & PPC_OPERAND_SIGNED) != 0  
5267 - && (value & (1 << (operand->bits - 1))) != 0)  
5268 - value -= 1 << operand->bits; 5335 + if (skip_optional < 0)
  5336 + skip_optional = skip_optional_operands (opindex, insn,
  5337 + dialect);
  5338 + if (skip_optional)
  5339 + continue;
5269 } 5340 }
5270 5341
5271 - /* If the operand is optional, and the value is zero, don't  
5272 - print anything. */  
5273 - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0  
5274 - && (operand->flags & PPC_OPERAND_NEXT) == 0  
5275 - && value == 0)  
5276 - continue; 5342 + value = operand_value_powerpc (operand, insn, dialect);
5277 5343
5278 if (need_comma) 5344 if (need_comma)
5279 { 5345 {
@@ -5298,7 +5364,7 @@ print_insn_powerpc (bfd_vma memaddr, @@ -5298,7 +5364,7 @@ print_insn_powerpc (bfd_vma memaddr,
5298 (*info->fprintf_func) (info->stream, "%ld", value); 5364 (*info->fprintf_func) (info->stream, "%ld", value);
5299 else 5365 else
5300 { 5366 {
5301 - if (operand->bits == 3) 5367 + if (operand->bitm == 7)
5302 (*info->fprintf_func) (info->stream, "cr%ld", value); 5368 (*info->fprintf_func) (info->stream, "cr%ld", value);
5303 else 5369 else
5304 { 5370 {