Commit ed005253181b0dae5911e1378f274ed80a20d0be
1 parent
e6320485
Don't wrap I2C registers addresses on PXA270.
This way the registers will only be visible at the given offset instead of every 0x100 bytes. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5899 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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7 additions
and
4 deletions
hw/pxa2xx.c
| @@ -1260,6 +1260,7 @@ struct pxa2xx_i2c_s { | @@ -1260,6 +1260,7 @@ struct pxa2xx_i2c_s { | ||
| 1260 | i2c_slave slave; | 1260 | i2c_slave slave; |
| 1261 | i2c_bus *bus; | 1261 | i2c_bus *bus; |
| 1262 | qemu_irq irq; | 1262 | qemu_irq irq; |
| 1263 | + target_phys_addr_t offset; | ||
| 1263 | 1264 | ||
| 1264 | uint16_t control; | 1265 | uint16_t control; |
| 1265 | uint16_t status; | 1266 | uint16_t status; |
| @@ -1340,7 +1341,7 @@ static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) | @@ -1340,7 +1341,7 @@ static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) | ||
| 1340 | { | 1341 | { |
| 1341 | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; | 1342 | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
| 1342 | 1343 | ||
| 1343 | - addr &= 0xff; | 1344 | + addr -= s->offset; |
| 1344 | switch (addr) { | 1345 | switch (addr) { |
| 1345 | case ICR: | 1346 | case ICR: |
| 1346 | return s->control; | 1347 | return s->control; |
| @@ -1369,7 +1370,7 @@ static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, | @@ -1369,7 +1370,7 @@ static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, | ||
| 1369 | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; | 1370 | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
| 1370 | int ack; | 1371 | int ack; |
| 1371 | 1372 | ||
| 1372 | - addr &= 0xff; | 1373 | + addr -= s->offset; |
| 1373 | switch (addr) { | 1374 | switch (addr) { |
| 1374 | case ICR: | 1375 | case ICR: |
| 1375 | s->control = value & 0xfff7; | 1376 | s->control = value & 0xfff7; |
| @@ -1474,7 +1475,7 @@ static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id) | @@ -1474,7 +1475,7 @@ static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id) | ||
| 1474 | } | 1475 | } |
| 1475 | 1476 | ||
| 1476 | struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, | 1477 | struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, |
| 1477 | - qemu_irq irq, uint32_t page_size) | 1478 | + qemu_irq irq, uint32_t region_size) |
| 1478 | { | 1479 | { |
| 1479 | int iomemtype; | 1480 | int iomemtype; |
| 1480 | /* FIXME: Should the slave device really be on a separate bus? */ | 1481 | /* FIXME: Should the slave device really be on a separate bus? */ |
| @@ -1486,10 +1487,12 @@ struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, | @@ -1486,10 +1487,12 @@ struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, | ||
| 1486 | s->slave.recv = pxa2xx_i2c_rx; | 1487 | s->slave.recv = pxa2xx_i2c_rx; |
| 1487 | s->slave.send = pxa2xx_i2c_tx; | 1488 | s->slave.send = pxa2xx_i2c_tx; |
| 1488 | s->bus = i2c_init_bus(); | 1489 | s->bus = i2c_init_bus(); |
| 1490 | + s->offset = base & region_size; | ||
| 1489 | 1491 | ||
| 1490 | iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn, | 1492 | iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn, |
| 1491 | pxa2xx_i2c_writefn, s); | 1493 | pxa2xx_i2c_writefn, s); |
| 1492 | - cpu_register_physical_memory(base & ~page_size, page_size + 1, iomemtype); | 1494 | + cpu_register_physical_memory(base & ~region_size, |
| 1495 | + region_size + 1, iomemtype); | ||
| 1493 | 1496 | ||
| 1494 | register_savevm("pxa2xx_i2c", base, 1, | 1497 | register_savevm("pxa2xx_i2c", base, 1, |
| 1495 | pxa2xx_i2c_save, pxa2xx_i2c_load, s); | 1498 | pxa2xx_i2c_save, pxa2xx_i2c_load, s); |