gwj / at91sam9263 · Commits

Commit ea363694707975f2e41dcabc2a77bc9ca015e7ac

Authored by aurel32
1 parent 312179c4

target-ppc: use consistent names for variables 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5557 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 141 additions and 141 deletions
target-ppc/translate.c
  View file @ea36369
... ... @@ -703,7 +703,7 @@ static opc_handler_t invalid_handler = {
703 703  
704 704 /*** Integer comparison ***/
705 705  
706   -static always_inline void gen_op_cmp(TCGv t0, TCGv t1, int s, int crf)
  706 +static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
707 707 {
708 708 int l1, l2, l3;
709 709  
... ... @@ -714,11 +714,11 @@ static always_inline void gen_op_cmp(TCGv t0, TCGv t1, int s, int crf)
714 714 l2 = gen_new_label();
715 715 l3 = gen_new_label();
716 716 if (s) {
717   - tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
718   - tcg_gen_brcond_tl(TCG_COND_GT, t0, t1, l2);
  717 + tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
  718 + tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
719 719 } else {
720   - tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
721   - tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l2);
  720 + tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
  721 + tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
722 722 }
723 723 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
724 724 tcg_gen_br(l3);
... ... @@ -730,36 +730,36 @@ static always_inline void gen_op_cmp(TCGv t0, TCGv t1, int s, int crf)
730 730 gen_set_label(l3);
731 731 }
732 732  
733   -static always_inline void gen_op_cmpi(TCGv t0, target_ulong t1, int s, int crf)
  733 +static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
734 734 {
735   - TCGv temp = tcg_const_local_tl(t1);
736   - gen_op_cmp(t0, temp, s, crf);
737   - tcg_temp_free(temp);
  735 + TCGv t0 = tcg_const_local_tl(arg1);
  736 + gen_op_cmp(arg0, t0, s, crf);
  737 + tcg_temp_free(t0);
738 738 }
739 739  
740 740 #if defined(TARGET_PPC64)
741   -static always_inline void gen_op_cmp32(TCGv t0, TCGv t1, int s, int crf)
  741 +static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
742 742 {
743   - TCGv t0_32, t1_32;
744   - t0_32 = tcg_temp_local_new(TCG_TYPE_TL);
745   - t1_32 = tcg_temp_local_new(TCG_TYPE_TL);
  743 + TCGv t0, t1;
  744 + t0 = tcg_temp_local_new(TCG_TYPE_TL);
  745 + t1 = tcg_temp_local_new(TCG_TYPE_TL);
746 746 if (s) {
747   - tcg_gen_ext32s_tl(t0_32, t0);
748   - tcg_gen_ext32s_tl(t1_32, t1);
  747 + tcg_gen_ext32s_tl(t0, arg0);
  748 + tcg_gen_ext32s_tl(t1, arg1);
749 749 } else {
750   - tcg_gen_ext32u_tl(t0_32, t0);
751   - tcg_gen_ext32u_tl(t1_32, t1);
  750 + tcg_gen_ext32u_tl(t0, arg0);
  751 + tcg_gen_ext32u_tl(t1, arg1);
752 752 }
753   - gen_op_cmp(t0_32, t1_32, s, crf);
754   - tcg_temp_free(t1_32);
755   - tcg_temp_free(t0_32);
  753 + gen_op_cmp(t0, t1, s, crf);
  754 + tcg_temp_free(t1);
  755 + tcg_temp_free(t0);
756 756 }
757 757  
758   -static always_inline void gen_op_cmpi32(TCGv t0, target_ulong t1, int s, int crf)
  758 +static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
759 759 {
760   - TCGv temp = tcg_const_local_tl(t1);
761   - gen_op_cmp32(t0, temp, s, crf);
762   - tcg_temp_free(temp);
  760 + TCGv t0 = tcg_const_local_tl(arg1);
  761 + gen_op_cmp32(arg0, t0, s, crf);
  762 + tcg_temp_free(t0);
763 763 }
764 764 #endif
765 765  
... ... @@ -1393,12 +1393,12 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1393 1393 break;
1394 1394 }
1395 1395 if (prio) {
1396   - TCGv temp = tcg_temp_new(TCG_TYPE_TL);
1397   - tcg_gen_ld_tl(temp, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1398   - tcg_gen_andi_tl(temp, temp, ~0x001C000000000000ULL);
1399   - tcg_gen_ori_tl(temp, temp, ((uint64_t)prio) << 50);
1400   - tcg_gen_st_tl(temp, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1401   - tcg_temp_free(temp);
  1396 + TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
  1397 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
  1398 + tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
  1399 + tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
  1400 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
  1401 + tcg_temp_free(t0);
1402 1402 }
1403 1403 #endif
1404 1404 }
... ... @@ -2413,135 +2413,135 @@ GEN_QEMU_ST_PPC64(16)
2413 2413 GEN_QEMU_ST_PPC64(32)
2414 2414 GEN_QEMU_ST_PPC64(64)
2415 2415  
2416   -static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
  2416 +static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2417 2417 {
2418   - gen_qemu_ld8u_ppc64(t0, t1, flags);
  2418 + gen_qemu_ld8u_ppc64(arg0, arg1, flags);
2419 2419 }
2420 2420  
2421   -static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
  2421 +static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2422 2422 {
2423   - gen_qemu_ld8s_ppc64(t0, t1, flags);
  2423 + gen_qemu_ld8s_ppc64(arg0, arg1, flags);
2424 2424 }
2425 2425  
2426   -static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
  2426 +static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2427 2427 {
2428 2428 if (unlikely(flags & 1)) {
2429   - TCGv t0_32;
2430   - gen_qemu_ld16u_ppc64(t0, t1, flags);
2431   - t0_32 = tcg_temp_new(TCG_TYPE_I32);
2432   - tcg_gen_trunc_tl_i32(t0_32, t0);
2433   - tcg_gen_bswap16_i32(t0_32, t0_32);
2434   - tcg_gen_extu_i32_tl(t0, t0_32);
2435   - tcg_temp_free(t0_32);
  2429 + TCGv t0;
  2430 + gen_qemu_ld16u_ppc64(arg0, arg1, flags);
  2431 + t0 = tcg_temp_new(TCG_TYPE_I32);
  2432 + tcg_gen_trunc_tl_i32(t0, arg0);
  2433 + tcg_gen_bswap16_i32(t0, t0);
  2434 + tcg_gen_extu_i32_tl(arg0, t0);
  2435 + tcg_temp_free(t0);
2436 2436 } else
2437   - gen_qemu_ld16u_ppc64(t0, t1, flags);
  2437 + gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2438 2438 }
2439 2439  
2440   -static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
  2440 +static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2441 2441 {
2442 2442 if (unlikely(flags & 1)) {
2443   - TCGv t0_32;
2444   - gen_qemu_ld16u_ppc64(t0, t1, flags);
2445   - t0_32 = tcg_temp_new(TCG_TYPE_I32);
2446   - tcg_gen_trunc_tl_i32(t0_32, t0);
2447   - tcg_gen_bswap16_i32(t0_32, t0_32);
2448   - tcg_gen_extu_i32_tl(t0, t0_32);
2449   - tcg_gen_ext16s_tl(t0, t0);
2450   - tcg_temp_free(t0_32);
  2443 + TCGv t0;
  2444 + gen_qemu_ld16u_ppc64(arg0, arg1, flags);
  2445 + t0 = tcg_temp_new(TCG_TYPE_I32);
  2446 + tcg_gen_trunc_tl_i32(t0, arg0);
  2447 + tcg_gen_bswap16_i32(t0, t0);
  2448 + tcg_gen_extu_i32_tl(arg0, t0);
  2449 + tcg_gen_ext16s_tl(arg0, arg0);
  2450 + tcg_temp_free(t0);
2451 2451 } else
2452   - gen_qemu_ld16s_ppc64(t0, t1, flags);
  2452 + gen_qemu_ld16s_ppc64(arg0, arg1, flags);
2453 2453 }
2454 2454  
2455   -static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
  2455 +static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2456 2456 {
2457 2457 if (unlikely(flags & 1)) {
2458   - TCGv t0_32;
2459   - gen_qemu_ld32u_ppc64(t0, t1, flags);
2460   - t0_32 = tcg_temp_new(TCG_TYPE_I32);
2461   - tcg_gen_trunc_tl_i32(t0_32, t0);
2462   - tcg_gen_bswap_i32(t0_32, t0_32);
2463   - tcg_gen_extu_i32_tl(t0, t0_32);
2464   - tcg_temp_free(t0_32);
  2458 + TCGv t0;
  2459 + gen_qemu_ld32u_ppc64(arg0, arg1, flags);
  2460 + t0 = tcg_temp_new(TCG_TYPE_I32);
  2461 + tcg_gen_trunc_tl_i32(t0, arg0);
  2462 + tcg_gen_bswap_i32(t0, t0);
  2463 + tcg_gen_extu_i32_tl(arg0, t0);
  2464 + tcg_temp_free(t0);
2465 2465 } else
2466   - gen_qemu_ld32u_ppc64(t0, t1, flags);
  2466 + gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2467 2467 }
2468 2468  
2469   -static always_inline void gen_qemu_ld32s(TCGv t0, TCGv t1, int flags)
  2469 +static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
2470 2470 {
2471 2471 if (unlikely(flags & 1)) {
2472   - TCGv t0_32;
2473   - gen_qemu_ld32u_ppc64(t0, t1, flags);
2474   - t0_32 = tcg_temp_new(TCG_TYPE_I32);
2475   - tcg_gen_trunc_tl_i32(t0_32, t0);
2476   - tcg_gen_bswap_i32(t0_32, t0_32);
2477   - tcg_gen_ext_i32_tl(t0, t0_32);
2478   - tcg_temp_free(t0_32);
  2472 + TCGv t0;
  2473 + gen_qemu_ld32u_ppc64(arg0, arg1, flags);
  2474 + t0 = tcg_temp_new(TCG_TYPE_I32);
  2475 + tcg_gen_trunc_tl_i32(t0, arg0);
  2476 + tcg_gen_bswap_i32(t0, t0);
  2477 + tcg_gen_ext_i32_tl(arg0, t0);
  2478 + tcg_temp_free(t0);
2479 2479 } else
2480   - gen_qemu_ld32s_ppc64(t0, t1, flags);
  2480 + gen_qemu_ld32s_ppc64(arg0, arg1, flags);
2481 2481 }
2482 2482  
2483   -static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
  2483 +static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2484 2484 {
2485   - gen_qemu_ld64_ppc64(t0, t1, flags);
  2485 + gen_qemu_ld64_ppc64(arg0, arg1, flags);
2486 2486 if (unlikely(flags & 1))
2487   - tcg_gen_bswap_i64(t0, t0);
  2487 + tcg_gen_bswap_i64(arg0, arg0);
2488 2488 }
2489 2489  
2490   -static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
  2490 +static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2491 2491 {
2492   - gen_qemu_st8_ppc64(t0, t1, flags);
  2492 + gen_qemu_st8_ppc64(arg0, arg1, flags);
2493 2493 }
2494 2494  
2495   -static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
  2495 +static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2496 2496 {
2497 2497 if (unlikely(flags & 1)) {
2498   - TCGv temp1, temp2;
2499   - temp1 = tcg_temp_new(TCG_TYPE_I32);
2500   - tcg_gen_trunc_tl_i32(temp1, t0);
2501   - tcg_gen_ext16u_i32(temp1, temp1);
2502   - tcg_gen_bswap16_i32(temp1, temp1);
2503   - temp2 = tcg_temp_new(TCG_TYPE_I64);
2504   - tcg_gen_extu_i32_tl(temp2, temp1);
2505   - tcg_temp_free(temp1);
2506   - gen_qemu_st16_ppc64(temp2, t1, flags);
2507   - tcg_temp_free(temp2);
  2498 + TCGv t0, t1;
  2499 + t0 = tcg_temp_new(TCG_TYPE_I32);
  2500 + tcg_gen_trunc_tl_i32(t0, arg0);
  2501 + tcg_gen_ext16u_i32(t0, t0);
  2502 + tcg_gen_bswap16_i32(t0, t0);
  2503 + t1 = tcg_temp_new(TCG_TYPE_I64);
  2504 + tcg_gen_extu_i32_tl(t1, t0);
  2505 + tcg_temp_free(t0);
  2506 + gen_qemu_st16_ppc64(t1, arg1, flags);
  2507 + tcg_temp_free(t1);
2508 2508 } else
2509   - gen_qemu_st16_ppc64(t0, t1, flags);
  2509 + gen_qemu_st16_ppc64(arg0, arg1, flags);
2510 2510 }
2511 2511  
2512   -static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
  2512 +static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2513 2513 {
2514 2514 if (unlikely(flags & 1)) {
2515   - TCGv temp1, temp2;
2516   - temp1 = tcg_temp_new(TCG_TYPE_I32);
2517   - tcg_gen_trunc_tl_i32(temp1, t0);
2518   - tcg_gen_bswap_i32(temp1, temp1);
2519   - temp2 = tcg_temp_new(TCG_TYPE_I64);
2520   - tcg_gen_extu_i32_tl(temp2, temp1);
2521   - tcg_temp_free(temp1);
2522   - gen_qemu_st32_ppc64(temp2, t1, flags);
2523   - tcg_temp_free(temp2);
  2515 + TCGv t0, t1;
  2516 + t0 = tcg_temp_new(TCG_TYPE_I32);
  2517 + tcg_gen_trunc_tl_i32(t0, arg0);
  2518 + tcg_gen_bswap_i32(t0, t0);
  2519 + t1 = tcg_temp_new(TCG_TYPE_I64);
  2520 + tcg_gen_extu_i32_tl(t1, t0);
  2521 + tcg_temp_free(t0);
  2522 + gen_qemu_st32_ppc64(t1, arg1, flags);
  2523 + tcg_temp_free(t1);
2524 2524 } else
2525   - gen_qemu_st32_ppc64(t0, t1, flags);
  2525 + gen_qemu_st32_ppc64(arg0, arg1, flags);
2526 2526 }
2527 2527  
2528   -static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
  2528 +static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2529 2529 {
2530 2530 if (unlikely(flags & 1)) {
2531   - TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2532   - tcg_gen_bswap_i64(temp, t0);
2533   - gen_qemu_st64_ppc64(temp, t1, flags);
2534   - tcg_temp_free(temp);
  2531 + TCGv t0 = tcg_temp_new(TCG_TYPE_I64);
  2532 + tcg_gen_bswap_i64(t0, arg0);
  2533 + gen_qemu_st64_ppc64(t0, arg1, flags);
  2534 + tcg_temp_free(t0);
2535 2535 } else
2536   - gen_qemu_st64_ppc64(t0, t1, flags);
  2536 + gen_qemu_st64_ppc64(arg0, arg1, flags);
2537 2537 }
2538 2538  
2539 2539  
2540 2540 #else /* defined(TARGET_PPC64) */
2541 2541 #define GEN_QEMU_LD_PPC32(width) \
2542   -static always_inline void gen_qemu_ld##width##_ppc32(TCGv t0, TCGv t1, int flags)\
  2542 +static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2543 2543 { \
2544   - tcg_gen_qemu_ld##width(t0, t1, flags >> 1); \
  2544 + tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
2545 2545 }
2546 2546 GEN_QEMU_LD_PPC32(8u)
2547 2547 GEN_QEMU_LD_PPC32(8s)
... ... @@ -2552,93 +2552,93 @@ GEN_QEMU_LD_PPC32(32s)
2552 2552 GEN_QEMU_LD_PPC32(64)
2553 2553  
2554 2554 #define GEN_QEMU_ST_PPC32(width) \
2555   -static always_inline void gen_qemu_st##width##_ppc32(TCGv t0, TCGv t1, int flags)\
  2555 +static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2556 2556 { \
2557   - tcg_gen_qemu_st##width(t0, t1, flags >> 1); \
  2557 + tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
2558 2558 }
2559 2559 GEN_QEMU_ST_PPC32(8)
2560 2560 GEN_QEMU_ST_PPC32(16)
2561 2561 GEN_QEMU_ST_PPC32(32)
2562 2562 GEN_QEMU_ST_PPC32(64)
2563 2563  
2564   -static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
  2564 +static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2565 2565 {
2566   - gen_qemu_ld8u_ppc32(t0, t1, flags >> 1);
  2566 + gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
2567 2567 }
2568 2568  
2569   -static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
  2569 +static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2570 2570 {
2571   - gen_qemu_ld8s_ppc32(t0, t1, flags >> 1);
  2571 + gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
2572 2572 }
2573 2573  
2574   -static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
  2574 +static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2575 2575 {
2576   - gen_qemu_ld16u_ppc32(t0, t1, flags >> 1);
  2576 + gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
2577 2577 if (unlikely(flags & 1))
2578   - tcg_gen_bswap16_i32(t0, t0);
  2578 + tcg_gen_bswap16_i32(arg0, arg0);
2579 2579 }
2580 2580  
2581   -static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
  2581 +static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2582 2582 {
2583 2583 if (unlikely(flags & 1)) {
2584   - gen_qemu_ld16u_ppc32(t0, t1, flags);
2585   - tcg_gen_bswap16_i32(t0, t0);
2586   - tcg_gen_ext16s_i32(t0, t0);
  2584 + gen_qemu_ld16u_ppc32(arg0, arg1, flags);
  2585 + tcg_gen_bswap16_i32(arg0, arg0);
  2586 + tcg_gen_ext16s_i32(arg0, arg0);
2587 2587 } else
2588   - gen_qemu_ld16s_ppc32(t0, t1, flags);
  2588 + gen_qemu_ld16s_ppc32(arg0, arg1, flags);
2589 2589 }
2590 2590  
2591   -static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
  2591 +static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2592 2592 {
2593   - gen_qemu_ld32u_ppc32(t0, t1, flags);
  2593 + gen_qemu_ld32u_ppc32(arg0, arg1, flags);
2594 2594 if (unlikely(flags & 1))
2595   - tcg_gen_bswap_i32(t0, t0);
  2595 + tcg_gen_bswap_i32(arg0, arg0);
2596 2596 }
2597 2597  
2598   -static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
  2598 +static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2599 2599 {
2600   - gen_qemu_ld64_ppc32(t0, t1, flags);
  2600 + gen_qemu_ld64_ppc32(arg0, arg1, flags);
2601 2601 if (unlikely(flags & 1))
2602   - tcg_gen_bswap_i64(t0, t0);
  2602 + tcg_gen_bswap_i64(arg0, arg0);
2603 2603 }
2604 2604  
2605   -static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
  2605 +static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2606 2606 {
2607   - gen_qemu_st8_ppc32(t0, t1, flags >> 1);
  2607 + gen_qemu_st8_ppc32(arg0, arg1, flags >> 1);
2608 2608 }
2609 2609  
2610   -static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
  2610 +static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2611 2611 {
2612 2612 if (unlikely(flags & 1)) {
2613 2613 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2614   - tcg_gen_ext16u_i32(temp, t0);
  2614 + tcg_gen_ext16u_i32(temp, arg0);
2615 2615 tcg_gen_bswap16_i32(temp, temp);
2616   - gen_qemu_st16_ppc32(temp, t1, flags >> 1);
  2616 + gen_qemu_st16_ppc32(temp, arg1, flags >> 1);
2617 2617 tcg_temp_free(temp);
2618 2618 } else
2619   - gen_qemu_st16_ppc32(t0, t1, flags >> 1);
  2619 + gen_qemu_st16_ppc32(arg0, arg1, flags >> 1);
2620 2620 }
2621 2621  
2622   -static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
  2622 +static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2623 2623 {
2624 2624 if (unlikely(flags & 1)) {
2625 2625 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2626   - tcg_gen_bswap_i32(temp, t0);
2627   - gen_qemu_st32_ppc32(temp, t1, flags >> 1);
  2626 + tcg_gen_bswap_i32(temp, arg0);
  2627 + gen_qemu_st32_ppc32(temp, arg1, flags >> 1);
2628 2628 tcg_temp_free(temp);
2629 2629 } else
2630   - gen_qemu_st32_ppc32(t0, t1, flags >> 1);
  2630 + gen_qemu_st32_ppc32(arg0, arg1, flags >> 1);
2631 2631 }
2632 2632  
2633   -static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
  2633 +static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2634 2634 {
2635 2635 if (unlikely(flags & 1)) {
2636 2636 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2637   - tcg_gen_bswap_i64(temp, t0);
2638   - gen_qemu_st64_ppc32(temp, t1, flags >> 1);
  2637 + tcg_gen_bswap_i64(temp, arg0);
  2638 + gen_qemu_st64_ppc32(temp, arg1, flags >> 1);
2639 2639 tcg_temp_free(temp);
2640 2640 } else
2641   - gen_qemu_st64_ppc32(t0, t1, flags >> 1);
  2641 + gen_qemu_st64_ppc32(arg0, arg1, flags >> 1);
2642 2642 }
2643 2643  
2644 2644 #endif
... ...