Commit ea026b2fc32bdddad6df22f7ab952761a29d9e6b
1 parent
4017190e
Improve PPC device debugging
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6126 c046a42c-6fe2-441c-8c8c-71466251a162
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6 changed files
with
90 additions
and
36 deletions
hw/adb.c
| @@ -25,6 +25,16 @@ | @@ -25,6 +25,16 @@ | ||
| 25 | #include "ppc_mac.h" | 25 | #include "ppc_mac.h" |
| 26 | #include "console.h" | 26 | #include "console.h" |
| 27 | 27 | ||
| 28 | +/* debug ADB */ | ||
| 29 | +//#define DEBUG_ADB | ||
| 30 | + | ||
| 31 | +#ifdef DEBUG_ADB | ||
| 32 | +#define ADB_DPRINTF(fmt, args...) \ | ||
| 33 | +do { printf("ADB: " fmt , ##args); } while (0) | ||
| 34 | +#else | ||
| 35 | +#define ADB_DPRINTF(fmt, args...) | ||
| 36 | +#endif | ||
| 37 | + | ||
| 28 | /* ADB commands */ | 38 | /* ADB commands */ |
| 29 | #define ADB_BUSRESET 0x00 | 39 | #define ADB_BUSRESET 0x00 |
| 30 | #define ADB_FLUSH 0x01 | 40 | #define ADB_FLUSH 0x01 |
| @@ -351,6 +361,7 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf, | @@ -351,6 +361,7 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf, | ||
| 351 | olen = 0; | 361 | olen = 0; |
| 352 | switch(cmd) { | 362 | switch(cmd) { |
| 353 | case ADB_WRITEREG: | 363 | case ADB_WRITEREG: |
| 364 | + ADB_DPRINTF("write reg %d val 0x%2.2x\n", reg, buf[1]); | ||
| 354 | switch(reg) { | 365 | switch(reg) { |
| 355 | case 2: | 366 | case 2: |
| 356 | break; | 367 | break; |
| @@ -383,6 +394,8 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf, | @@ -383,6 +394,8 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf, | ||
| 383 | olen = 2; | 394 | olen = 2; |
| 384 | break; | 395 | break; |
| 385 | } | 396 | } |
| 397 | + ADB_DPRINTF("read reg %d obuf[0] 0x%2.2x obuf[1] 0x%2.2x\n", reg, | ||
| 398 | + obuf[0], obuf[1]); | ||
| 386 | break; | 399 | break; |
| 387 | } | 400 | } |
| 388 | return olen; | 401 | return olen; |
hw/cuda.c
| @@ -29,9 +29,19 @@ | @@ -29,9 +29,19 @@ | ||
| 29 | 29 | ||
| 30 | /* XXX: implement all timer modes */ | 30 | /* XXX: implement all timer modes */ |
| 31 | 31 | ||
| 32 | +/* debug CUDA */ | ||
| 32 | //#define DEBUG_CUDA | 33 | //#define DEBUG_CUDA |
| 34 | + | ||
| 35 | +/* debug CUDA packets */ | ||
| 33 | //#define DEBUG_CUDA_PACKET | 36 | //#define DEBUG_CUDA_PACKET |
| 34 | 37 | ||
| 38 | +#ifdef DEBUG_CUDA | ||
| 39 | +#define CUDA_DPRINTF(fmt, args...) \ | ||
| 40 | +do { printf("CUDA: " fmt , ##args); } while (0) | ||
| 41 | +#else | ||
| 42 | +#define CUDA_DPRINTF(fmt, args...) | ||
| 43 | +#endif | ||
| 44 | + | ||
| 35 | /* Bits in B data register: all active low */ | 45 | /* Bits in B data register: all active low */ |
| 36 | #define TREQ 0x08 /* Transfer request (input) */ | 46 | #define TREQ 0x08 /* Transfer request (input) */ |
| 37 | #define TACK 0x10 /* Transfer acknowledge (output) */ | 47 | #define TACK 0x10 /* Transfer acknowledge (output) */ |
| @@ -176,10 +186,7 @@ static unsigned int get_counter(CUDATimer *s) | @@ -176,10 +186,7 @@ static unsigned int get_counter(CUDATimer *s) | ||
| 176 | 186 | ||
| 177 | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) | 187 | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
| 178 | { | 188 | { |
| 179 | -#ifdef DEBUG_CUDA | ||
| 180 | - printf("cuda: T%d.counter=%d\n", | ||
| 181 | - 1 + (ti->timer == NULL), val); | ||
| 182 | -#endif | 189 | + CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val); |
| 183 | ti->load_time = qemu_get_clock(vm_clock); | 190 | ti->load_time = qemu_get_clock(vm_clock); |
| 184 | ti->counter_value = val; | 191 | ti->counter_value = val; |
| 185 | cuda_timer_update(s, ti, ti->load_time); | 192 | cuda_timer_update(s, ti, ti->load_time); |
| @@ -209,12 +216,8 @@ static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) | @@ -209,12 +216,8 @@ static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) | ||
| 209 | } else { | 216 | } else { |
| 210 | next_time = d + counter; | 217 | next_time = d + counter; |
| 211 | } | 218 | } |
| 212 | -#if 0 | ||
| 213 | -#ifdef DEBUG_CUDA | ||
| 214 | - printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", | ||
| 215 | - s->latch, d, next_time - d); | ||
| 216 | -#endif | ||
| 217 | -#endif | 219 | + CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", |
| 220 | + s->latch, d, next_time - d); | ||
| 218 | next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + | 221 | next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
| 219 | s->load_time; | 222 | s->load_time; |
| 220 | if (next_time <= current_time) | 223 | if (next_time <= current_time) |
| @@ -311,10 +314,8 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) | @@ -311,10 +314,8 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) | ||
| 311 | val = s->anh; | 314 | val = s->anh; |
| 312 | break; | 315 | break; |
| 313 | } | 316 | } |
| 314 | -#ifdef DEBUG_CUDA | ||
| 315 | if (addr != 13 || val != 0) | 317 | if (addr != 13 || val != 0) |
| 316 | - printf("cuda: read: reg=0x%x val=%02x\n", addr, val); | ||
| 317 | -#endif | 318 | + CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val); |
| 318 | return val; | 319 | return val; |
| 319 | } | 320 | } |
| 320 | 321 | ||
| @@ -323,9 +324,7 @@ static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | @@ -323,9 +324,7 @@ static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
| 323 | CUDAState *s = opaque; | 324 | CUDAState *s = opaque; |
| 324 | 325 | ||
| 325 | addr = (addr >> 9) & 0xf; | 326 | addr = (addr >> 9) & 0xf; |
| 326 | -#ifdef DEBUG_CUDA | ||
| 327 | - printf("cuda: write: reg=0x%x val=%02x\n", addr, val); | ||
| 328 | -#endif | 327 | + CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val); |
| 329 | 328 | ||
| 330 | switch(addr) { | 329 | switch(addr) { |
| 331 | case 0: | 330 | case 0: |
| @@ -412,9 +411,7 @@ static void cuda_update(CUDAState *s) | @@ -412,9 +411,7 @@ static void cuda_update(CUDAState *s) | ||
| 412 | /* data output */ | 411 | /* data output */ |
| 413 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { | 412 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { |
| 414 | if (s->data_out_index < sizeof(s->data_out)) { | 413 | if (s->data_out_index < sizeof(s->data_out)) { |
| 415 | -#ifdef DEBUG_CUDA | ||
| 416 | - printf("cuda: send: %02x\n", s->sr); | ||
| 417 | -#endif | 414 | + CUDA_DPRINTF("send: %02x\n", s->sr); |
| 418 | s->data_out[s->data_out_index++] = s->sr; | 415 | s->data_out[s->data_out_index++] = s->sr; |
| 419 | s->ifr |= SR_INT; | 416 | s->ifr |= SR_INT; |
| 420 | cuda_update_irq(s); | 417 | cuda_update_irq(s); |
| @@ -425,9 +422,7 @@ static void cuda_update(CUDAState *s) | @@ -425,9 +422,7 @@ static void cuda_update(CUDAState *s) | ||
| 425 | /* data input */ | 422 | /* data input */ |
| 426 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { | 423 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { |
| 427 | s->sr = s->data_in[s->data_in_index++]; | 424 | s->sr = s->data_in[s->data_in_index++]; |
| 428 | -#ifdef DEBUG_CUDA | ||
| 429 | - printf("cuda: recv: %02x\n", s->sr); | ||
| 430 | -#endif | 425 | + CUDA_DPRINTF("recv: %02x\n", s->sr); |
| 431 | /* indicate end of transfer */ | 426 | /* indicate end of transfer */ |
| 432 | if (s->data_in_index >= s->data_in_size) { | 427 | if (s->data_in_index >= s->data_in_size) { |
| 433 | s->b = (s->b | TREQ); | 428 | s->b = (s->b | TREQ); |
hw/grackle_pci.c
| @@ -27,6 +27,16 @@ | @@ -27,6 +27,16 @@ | ||
| 27 | #include "ppc_mac.h" | 27 | #include "ppc_mac.h" |
| 28 | #include "pci.h" | 28 | #include "pci.h" |
| 29 | 29 | ||
| 30 | +/* debug Grackle */ | ||
| 31 | +//#define DEBUG_GRACKLE | ||
| 32 | + | ||
| 33 | +#ifdef DEBUG_GRACKLE | ||
| 34 | +#define GRACKLE_DPRINTF(fmt, args...) \ | ||
| 35 | +do { printf("GRACKLE: " fmt , ##args); } while (0) | ||
| 36 | +#else | ||
| 37 | +#define GRACKLE_DPRINTF(fmt, args...) | ||
| 38 | +#endif | ||
| 39 | + | ||
| 30 | typedef target_phys_addr_t pci_addr_t; | 40 | typedef target_phys_addr_t pci_addr_t; |
| 31 | #include "pci_host.h" | 41 | #include "pci_host.h" |
| 32 | 42 | ||
| @@ -36,6 +46,9 @@ static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, | @@ -36,6 +46,9 @@ static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, | ||
| 36 | uint32_t val) | 46 | uint32_t val) |
| 37 | { | 47 | { |
| 38 | GrackleState *s = opaque; | 48 | GrackleState *s = opaque; |
| 49 | + | ||
| 50 | + GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, | ||
| 51 | + val); | ||
| 39 | #ifdef TARGET_WORDS_BIGENDIAN | 52 | #ifdef TARGET_WORDS_BIGENDIAN |
| 40 | val = bswap32(val); | 53 | val = bswap32(val); |
| 41 | #endif | 54 | #endif |
| @@ -51,6 +64,8 @@ static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) | @@ -51,6 +64,8 @@ static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) | ||
| 51 | #ifdef TARGET_WORDS_BIGENDIAN | 64 | #ifdef TARGET_WORDS_BIGENDIAN |
| 52 | val = bswap32(val); | 65 | val = bswap32(val); |
| 53 | #endif | 66 | #endif |
| 67 | + GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, | ||
| 68 | + val); | ||
| 54 | return val; | 69 | return val; |
| 55 | } | 70 | } |
| 56 | 71 | ||
| @@ -86,6 +101,7 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) | @@ -86,6 +101,7 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) | ||
| 86 | 101 | ||
| 87 | static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) | 102 | static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) |
| 88 | { | 103 | { |
| 104 | + GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level); | ||
| 89 | qemu_set_irq(pic[irq_num + 0x15], level); | 105 | qemu_set_irq(pic[irq_num + 0x15], level); |
| 90 | } | 106 | } |
| 91 | 107 |
hw/heathrow_pic.c
| @@ -25,7 +25,15 @@ | @@ -25,7 +25,15 @@ | ||
| 25 | #include "hw.h" | 25 | #include "hw.h" |
| 26 | #include "ppc_mac.h" | 26 | #include "ppc_mac.h" |
| 27 | 27 | ||
| 28 | -//#define DEBUG | 28 | +/* debug PIC */ |
| 29 | +//#define DEBUG_PIC | ||
| 30 | + | ||
| 31 | +#ifdef DEBUG_PIC | ||
| 32 | +#define PIC_DPRINTF(fmt, args...) \ | ||
| 33 | +do { printf("PIC: " fmt , ##args); } while (0) | ||
| 34 | +#else | ||
| 35 | +#define PIC_DPRINTF(fmt, args...) | ||
| 36 | +#endif | ||
| 29 | 37 | ||
| 30 | typedef struct HeathrowPIC { | 38 | typedef struct HeathrowPIC { |
| 31 | uint32_t events; | 39 | uint32_t events; |
| @@ -64,9 +72,7 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | @@ -64,9 +72,7 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | ||
| 64 | value = bswap32(value); | 72 | value = bswap32(value); |
| 65 | #endif | 73 | #endif |
| 66 | n = ((addr & 0xfff) - 0x10) >> 4; | 74 | n = ((addr & 0xfff) - 0x10) >> 4; |
| 67 | -#ifdef DEBUG | ||
| 68 | - printf("pic_writel: " PADDRX " %u: %08x\n", addr, n, value); | ||
| 69 | -#endif | 75 | + PIC_DPRINTF("writel: " TARGET_FMT_plx " %u: %08x\n", addr, n, value); |
| 70 | if (n >= 2) | 76 | if (n >= 2) |
| 71 | return; | 77 | return; |
| 72 | pic = &s->pics[n]; | 78 | pic = &s->pics[n]; |
| @@ -113,9 +119,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) | @@ -113,9 +119,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) | ||
| 113 | break; | 119 | break; |
| 114 | } | 120 | } |
| 115 | } | 121 | } |
| 116 | -#ifdef DEBUG | ||
| 117 | - printf("pic_readl: " PADDRX " %u: %08x\n", addr, n, value); | ||
| 118 | -#endif | 122 | + PIC_DPRINTF("readl: " TARGET_FMT_plx " %u: %08x\n", addr, n, value); |
| 119 | #ifdef TARGET_WORDS_BIGENDIAN | 123 | #ifdef TARGET_WORDS_BIGENDIAN |
| 120 | value = bswap32(value); | 124 | value = bswap32(value); |
| 121 | #endif | 125 | #endif |
| @@ -145,7 +149,7 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level) | @@ -145,7 +149,7 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level) | ||
| 145 | { | 149 | { |
| 146 | static int last_level[64]; | 150 | static int last_level[64]; |
| 147 | if (last_level[num] != level) { | 151 | if (last_level[num] != level) { |
| 148 | - printf("set_irq: num=0x%02x level=%d\n", num, level); | 152 | + PIC_DPRINTF("set_irq: num=0x%02x level=%d\n", num, level); |
| 149 | last_level[num] = level; | 153 | last_level[num] = level; |
| 150 | } | 154 | } |
| 151 | } | 155 | } |
hw/mac_dbdma.c
| @@ -25,38 +25,54 @@ | @@ -25,38 +25,54 @@ | ||
| 25 | #include "hw.h" | 25 | #include "hw.h" |
| 26 | #include "ppc_mac.h" | 26 | #include "ppc_mac.h" |
| 27 | 27 | ||
| 28 | +/* debug DBDMA */ | ||
| 29 | +//#define DEBUG_DBDMA | ||
| 30 | + | ||
| 31 | +#ifdef DEBUG_DBDMA | ||
| 32 | +#define DBDMA_DPRINTF(fmt, args...) \ | ||
| 33 | +do { printf("DBDMA: " fmt , ##args); } while (0) | ||
| 34 | +#else | ||
| 35 | +#define DBDMA_DPRINTF(fmt, args...) | ||
| 36 | +#endif | ||
| 37 | + | ||
| 28 | /* DBDMA: currently no op - should suffice right now */ | 38 | /* DBDMA: currently no op - should suffice right now */ |
| 29 | 39 | ||
| 30 | static void dbdma_writeb (void *opaque, | 40 | static void dbdma_writeb (void *opaque, |
| 31 | target_phys_addr_t addr, uint32_t value) | 41 | target_phys_addr_t addr, uint32_t value) |
| 32 | { | 42 | { |
| 33 | - printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value); | 43 | + DBDMA_DPRINTF("writeb 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value); |
| 34 | } | 44 | } |
| 35 | 45 | ||
| 36 | static void dbdma_writew (void *opaque, | 46 | static void dbdma_writew (void *opaque, |
| 37 | target_phys_addr_t addr, uint32_t value) | 47 | target_phys_addr_t addr, uint32_t value) |
| 38 | { | 48 | { |
| 49 | + DBDMA_DPRINTF("writew 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value); | ||
| 39 | } | 50 | } |
| 40 | 51 | ||
| 41 | static void dbdma_writel (void *opaque, | 52 | static void dbdma_writel (void *opaque, |
| 42 | target_phys_addr_t addr, uint32_t value) | 53 | target_phys_addr_t addr, uint32_t value) |
| 43 | { | 54 | { |
| 55 | + DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value); | ||
| 44 | } | 56 | } |
| 45 | 57 | ||
| 46 | static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) | 58 | static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) |
| 47 | { | 59 | { |
| 48 | - printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr); | 60 | + DBDMA_DPRINTF("readb 0x" TARGET_FMT_plx " => 0\n", addr); |
| 49 | 61 | ||
| 50 | return 0; | 62 | return 0; |
| 51 | } | 63 | } |
| 52 | 64 | ||
| 53 | static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) | 65 | static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) |
| 54 | { | 66 | { |
| 67 | + DBDMA_DPRINTF("readw 0x" TARGET_FMT_plx " => 0\n", addr); | ||
| 68 | + | ||
| 55 | return 0; | 69 | return 0; |
| 56 | } | 70 | } |
| 57 | 71 | ||
| 58 | static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) | 72 | static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) |
| 59 | { | 73 | { |
| 74 | + DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0\n", addr); | ||
| 75 | + | ||
| 60 | return 0; | 76 | return 0; |
| 61 | } | 77 | } |
| 62 | 78 |
hw/mac_nvram.c
| @@ -25,6 +25,16 @@ | @@ -25,6 +25,16 @@ | ||
| 25 | #include "hw.h" | 25 | #include "hw.h" |
| 26 | #include "ppc_mac.h" | 26 | #include "ppc_mac.h" |
| 27 | 27 | ||
| 28 | +/* debug NVR */ | ||
| 29 | +//#define DEBUG_NVR | ||
| 30 | + | ||
| 31 | +#ifdef DEBUG_NVR | ||
| 32 | +#define NVR_DPRINTF(fmt, args...) \ | ||
| 33 | +do { printf("NVR: " fmt , ##args); } while (0) | ||
| 34 | +#else | ||
| 35 | +#define NVR_DPRINTF(fmt, args...) | ||
| 36 | +#endif | ||
| 37 | + | ||
| 28 | struct MacIONVRAMState { | 38 | struct MacIONVRAMState { |
| 29 | target_phys_addr_t size; | 39 | target_phys_addr_t size; |
| 30 | int mem_index; | 40 | int mem_index; |
| @@ -37,11 +47,11 @@ uint32_t macio_nvram_read (void *opaque, uint32_t addr) | @@ -37,11 +47,11 @@ uint32_t macio_nvram_read (void *opaque, uint32_t addr) | ||
| 37 | MacIONVRAMState *s = opaque; | 47 | MacIONVRAMState *s = opaque; |
| 38 | uint32_t ret; | 48 | uint32_t ret; |
| 39 | 49 | ||
| 40 | - // printf("%s: %p addr %04x\n", __func__, s, addr); | ||
| 41 | if (addr < 0x2000) | 50 | if (addr < 0x2000) |
| 42 | ret = s->data[addr]; | 51 | ret = s->data[addr]; |
| 43 | else | 52 | else |
| 44 | ret = -1; | 53 | ret = -1; |
| 54 | + NVR_DPRINTF("read addr %04x val %x\n", addr, ret); | ||
| 45 | 55 | ||
| 46 | return ret; | 56 | return ret; |
| 47 | } | 57 | } |
| @@ -50,7 +60,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val) | @@ -50,7 +60,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val) | ||
| 50 | { | 60 | { |
| 51 | MacIONVRAMState *s = opaque; | 61 | MacIONVRAMState *s = opaque; |
| 52 | 62 | ||
| 53 | - // printf("%s: %p addr %04x val %02x\n", __func__, s, addr, val); | 63 | + NVR_DPRINTF("write addr %04x val %x\n", addr, val); |
| 54 | if (addr < 0x2000) | 64 | if (addr < 0x2000) |
| 55 | s->data[addr] = val; | 65 | s->data[addr] = val; |
| 56 | } | 66 | } |
| @@ -63,7 +73,7 @@ static void macio_nvram_writeb (void *opaque, | @@ -63,7 +73,7 @@ static void macio_nvram_writeb (void *opaque, | ||
| 63 | 73 | ||
| 64 | addr = (addr >> 4) & 0x1fff; | 74 | addr = (addr >> 4) & 0x1fff; |
| 65 | s->data[addr] = value; | 75 | s->data[addr] = value; |
| 66 | - // printf("macio_nvram_writeb %04x = %02x\n", addr, value); | 76 | + NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value); |
| 67 | } | 77 | } |
| 68 | 78 | ||
| 69 | static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) | 79 | static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) |
| @@ -73,7 +83,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) | @@ -73,7 +83,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) | ||
| 73 | 83 | ||
| 74 | addr = (addr >> 4) & 0x1fff; | 84 | addr = (addr >> 4) & 0x1fff; |
| 75 | value = s->data[addr]; | 85 | value = s->data[addr]; |
| 76 | - // printf("macio_nvram_readb %04x = %02x\n", addr, value); | 86 | + NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value); |
| 77 | 87 | ||
| 78 | return value; | 88 | return value; |
| 79 | } | 89 | } |