gwj / at91sam9263 · Commits

Commit e9ebed4d41fc0630e433a32ecfd1057cae8b10bf

Authored by blueswir1
1 parent 3d834c78

Sparc64 update: more VIS ops 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2714 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 884 additions and 36 deletions
target-sparc/cpu.h
  View file @e9ebed4
... ... @@ -225,6 +225,9 @@ typedef struct CPUSPARCState {
225 225 uint64_t fprs;
226 226 uint64_t tick_cmpr, stick_cmpr;
227 227 uint64_t gsr;
  228 + uint32_t gl; // UA2005
  229 + /* UA 2005 hyperprivileged registers */
  230 + uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
228 231 #endif
229 232 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
230 233 target_ulong t2;
... ...
target-sparc/op.c
  View file @e9ebed4
... ... @@ -1095,7 +1095,7 @@ void OPPROTO op_rdtick(void)
1095 1095  
1096 1096 void OPPROTO op_wrtick(void)
1097 1097 {
1098   - // XXX write cycle counter and bit 31
  1098 + T0 = 0; // XXX write cycle counter and bit 31
1099 1099 }
1100 1100  
1101 1101 void OPPROTO op_rdtpc(void)
... ... @@ -1818,8 +1818,7 @@ void OPPROTO op_retry(void)
1818 1818  
1819 1819 void OPPROTO op_sir(void)
1820 1820 {
1821   - // XXX
1822   -
  1821 + T0 = 0; // XXX
1823 1822 }
1824 1823  
1825 1824 void OPPROTO op_ld_asi_reg()
... ... @@ -1846,6 +1845,44 @@ void OPPROTO op_st_asi()
1846 1845 }
1847 1846  
1848 1847 #ifdef TARGET_SPARC64
  1848 +// This function uses non-native bit order
  1849 +#define GET_FIELD(X, FROM, TO) \
  1850 + ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
  1851 +
  1852 +// This function uses the order in the manuals, i.e. bit 0 is 2^0
  1853 +#define GET_FIELD_SP(X, FROM, TO) \
  1854 + GET_FIELD(X, 63 - (TO), 63 - (FROM))
  1855 +
  1856 +void OPPROTO op_array8()
  1857 +{
  1858 + T0 = (GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
  1859 + (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
  1860 + (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
  1861 + (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
  1862 + (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
  1863 + (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12);
  1864 +}
  1865 +
  1866 +void OPPROTO op_array16()
  1867 +{
  1868 + T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
  1869 + (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
  1870 + (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
  1871 + (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
  1872 + (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
  1873 + (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 1;
  1874 +}
  1875 +
  1876 +void OPPROTO op_array32()
  1877 +{
  1878 + T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
  1879 + (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
  1880 + (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
  1881 + (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
  1882 + (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
  1883 + (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 2;
  1884 +}
  1885 +
1849 1886 void OPPROTO op_alignaddr()
1850 1887 {
1851 1888 uint64_t tmp;
... ... @@ -1862,26 +1899,440 @@ void OPPROTO op_faligndata()
1862 1899  
1863 1900 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
1864 1901 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
1865   - (*((uint64_t *)&DT0)) = tmp;
  1902 + *((uint64_t *)&DT0) = tmp;
1866 1903 }
1867 1904  
1868 1905 void OPPROTO op_movl_FT0_0(void)
1869 1906 {
1870   - (*((uint32_t *)&FT0)) = 0;
  1907 + *((uint32_t *)&FT0) = 0;
1871 1908 }
1872 1909  
1873 1910 void OPPROTO op_movl_DT0_0(void)
1874 1911 {
1875   - (*((uint64_t *)&DT0)) = 0;
  1912 + *((uint64_t *)&DT0) = 0;
1876 1913 }
1877 1914  
1878 1915 void OPPROTO op_movl_FT0_1(void)
1879 1916 {
1880   - (*((uint32_t *)&FT0)) = 0xffffffff;
  1917 + *((uint32_t *)&FT0) = 0xffffffff;
1881 1918 }
1882 1919  
1883 1920 void OPPROTO op_movl_DT0_1(void)
1884 1921 {
1885   - (*((uint64_t *)&DT0)) = 0xffffffffffffffffULL;
  1922 + *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
  1923 +}
  1924 +
  1925 +void OPPROTO op_fnot(void)
  1926 +{
  1927 + *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
  1928 +}
  1929 +
  1930 +void OPPROTO op_fnots(void)
  1931 +{
  1932 + *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
  1933 +}
  1934 +
  1935 +void OPPROTO op_fnor(void)
  1936 +{
  1937 + *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
  1938 +}
  1939 +
  1940 +void OPPROTO op_fnors(void)
  1941 +{
  1942 + *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
  1943 +}
  1944 +
  1945 +void OPPROTO op_for(void)
  1946 +{
  1947 + *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
  1948 +}
  1949 +
  1950 +void OPPROTO op_fors(void)
  1951 +{
  1952 + *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
  1953 +}
  1954 +
  1955 +void OPPROTO op_fxor(void)
  1956 +{
  1957 + *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
  1958 +}
  1959 +
  1960 +void OPPROTO op_fxors(void)
  1961 +{
  1962 + *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
  1963 +}
  1964 +
  1965 +void OPPROTO op_fand(void)
  1966 +{
  1967 + *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
  1968 +}
  1969 +
  1970 +void OPPROTO op_fands(void)
  1971 +{
  1972 + *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
  1973 +}
  1974 +
  1975 +void OPPROTO op_fornot(void)
  1976 +{
  1977 + *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
  1978 +}
  1979 +
  1980 +void OPPROTO op_fornots(void)
  1981 +{
  1982 + *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
  1983 +}
  1984 +
  1985 +void OPPROTO op_fandnot(void)
  1986 +{
  1987 + *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
  1988 +}
  1989 +
  1990 +void OPPROTO op_fandnots(void)
  1991 +{
  1992 + *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
  1993 +}
  1994 +
  1995 +void OPPROTO op_fnand(void)
  1996 +{
  1997 + *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
  1998 +}
  1999 +
  2000 +void OPPROTO op_fnands(void)
  2001 +{
  2002 + *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
  2003 +}
  2004 +
  2005 +void OPPROTO op_fxnor(void)
  2006 +{
  2007 + *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
  2008 +}
  2009 +
  2010 +void OPPROTO op_fxnors(void)
  2011 +{
  2012 + *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
  2013 +}
  2014 +
  2015 +#ifdef WORDS_BIGENDIAN
  2016 +#define VIS_B64(n) b[7 - (n)]
  2017 +#define VIS_W64(n) w[3 - (n)]
  2018 +#define VIS_SW64(n) sw[3 - (n)]
  2019 +#define VIS_L64(n) l[1 - (n)]
  2020 +#define VIS_B32(n) b[3 - (n)]
  2021 +#define VIS_W32(n) w[1 - (n)]
  2022 +#else
  2023 +#define VIS_B64(n) b[n]
  2024 +#define VIS_W64(n) w[n]
  2025 +#define VIS_SW64(n) sw[n]
  2026 +#define VIS_L64(n) l[n]
  2027 +#define VIS_B32(n) b[n]
  2028 +#define VIS_W32(n) w[n]
  2029 +#endif
  2030 +
  2031 +typedef union {
  2032 + uint8_t b[8];
  2033 + uint16_t w[4];
  2034 + int16_t sw[4];
  2035 + uint32_t l[2];
  2036 + float64 d;
  2037 +} vis64;
  2038 +
  2039 +typedef union {
  2040 + uint8_t b[4];
  2041 + uint16_t w[2];
  2042 + uint32_t l;
  2043 + float32 f;
  2044 +} vis32;
  2045 +
  2046 +void OPPROTO op_fpmerge(void)
  2047 +{
  2048 + vis64 s, d;
  2049 +
  2050 + s.d = DT0;
  2051 + d.d = DT1;
  2052 +
  2053 + // Reverse calculation order to handle overlap
  2054 + d.VIS_B64(7) = s.VIS_B64(3);
  2055 + d.VIS_B64(6) = d.VIS_B64(3);
  2056 + d.VIS_B64(5) = s.VIS_B64(2);
  2057 + d.VIS_B64(4) = d.VIS_B64(2);
  2058 + d.VIS_B64(3) = s.VIS_B64(1);
  2059 + d.VIS_B64(2) = d.VIS_B64(1);
  2060 + d.VIS_B64(1) = s.VIS_B64(0);
  2061 + //d.VIS_B64(0) = d.VIS_B64(0);
  2062 +
  2063 + DT0 = d.d;
  2064 +}
  2065 +
  2066 +void OPPROTO op_fmul8x16(void)
  2067 +{
  2068 + vis64 s, d;
  2069 + uint32_t tmp;
  2070 +
  2071 + s.d = DT0;
  2072 + d.d = DT1;
  2073 +
  2074 +#define PMUL(r) \
  2075 + tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
  2076 + if ((tmp & 0xff) > 0x7f) \
  2077 + tmp += 0x100; \
  2078 + d.VIS_W64(r) = tmp >> 8;
  2079 +
  2080 + PMUL(0);
  2081 + PMUL(1);
  2082 + PMUL(2);
  2083 + PMUL(3);
  2084 +#undef PMUL
  2085 +
  2086 + DT0 = d.d;
  2087 +}
  2088 +
  2089 +void OPPROTO op_fmul8x16al(void)
  2090 +{
  2091 + vis64 s, d;
  2092 + uint32_t tmp;
  2093 +
  2094 + s.d = DT0;
  2095 + d.d = DT1;
  2096 +
  2097 +#define PMUL(r) \
  2098 + tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
  2099 + if ((tmp & 0xff) > 0x7f) \
  2100 + tmp += 0x100; \
  2101 + d.VIS_W64(r) = tmp >> 8;
  2102 +
  2103 + PMUL(0);
  2104 + PMUL(1);
  2105 + PMUL(2);
  2106 + PMUL(3);
  2107 +#undef PMUL
  2108 +
  2109 + DT0 = d.d;
1886 2110 }
  2111 +
  2112 +void OPPROTO op_fmul8x16au(void)
  2113 +{
  2114 + vis64 s, d;
  2115 + uint32_t tmp;
  2116 +
  2117 + s.d = DT0;
  2118 + d.d = DT1;
  2119 +
  2120 +#define PMUL(r) \
  2121 + tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
  2122 + if ((tmp & 0xff) > 0x7f) \
  2123 + tmp += 0x100; \
  2124 + d.VIS_W64(r) = tmp >> 8;
  2125 +
  2126 + PMUL(0);
  2127 + PMUL(1);
  2128 + PMUL(2);
  2129 + PMUL(3);
  2130 +#undef PMUL
  2131 +
  2132 + DT0 = d.d;
  2133 +}
  2134 +
  2135 +void OPPROTO op_fmul8sux16(void)
  2136 +{
  2137 + vis64 s, d;
  2138 + uint32_t tmp;
  2139 +
  2140 + s.d = DT0;
  2141 + d.d = DT1;
  2142 +
  2143 +#define PMUL(r) \
  2144 + tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
  2145 + if ((tmp & 0xff) > 0x7f) \
  2146 + tmp += 0x100; \
  2147 + d.VIS_W64(r) = tmp >> 8;
  2148 +
  2149 + PMUL(0);
  2150 + PMUL(1);
  2151 + PMUL(2);
  2152 + PMUL(3);
  2153 +#undef PMUL
  2154 +
  2155 + DT0 = d.d;
  2156 +}
  2157 +
  2158 +void OPPROTO op_fmul8ulx16(void)
  2159 +{
  2160 + vis64 s, d;
  2161 + uint32_t tmp;
  2162 +
  2163 + s.d = DT0;
  2164 + d.d = DT1;
  2165 +
  2166 +#define PMUL(r) \
  2167 + tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
  2168 + if ((tmp & 0xff) > 0x7f) \
  2169 + tmp += 0x100; \
  2170 + d.VIS_W64(r) = tmp >> 8;
  2171 +
  2172 + PMUL(0);
  2173 + PMUL(1);
  2174 + PMUL(2);
  2175 + PMUL(3);
  2176 +#undef PMUL
  2177 +
  2178 + DT0 = d.d;
  2179 +}
  2180 +
  2181 +void OPPROTO op_fmuld8sux16(void)
  2182 +{
  2183 + vis64 s, d;
  2184 + uint32_t tmp;
  2185 +
  2186 + s.d = DT0;
  2187 + d.d = DT1;
  2188 +
  2189 +#define PMUL(r) \
  2190 + tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
  2191 + if ((tmp & 0xff) > 0x7f) \
  2192 + tmp += 0x100; \
  2193 + d.VIS_L64(r) = tmp;
  2194 +
  2195 + // Reverse calculation order to handle overlap
  2196 + PMUL(1);
  2197 + PMUL(0);
  2198 +#undef PMUL
  2199 +
  2200 + DT0 = d.d;
  2201 +}
  2202 +
  2203 +void OPPROTO op_fmuld8ulx16(void)
  2204 +{
  2205 + vis64 s, d;
  2206 + uint32_t tmp;
  2207 +
  2208 + s.d = DT0;
  2209 + d.d = DT1;
  2210 +
  2211 +#define PMUL(r) \
  2212 + tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
  2213 + if ((tmp & 0xff) > 0x7f) \
  2214 + tmp += 0x100; \
  2215 + d.VIS_L64(r) = tmp;
  2216 +
  2217 + // Reverse calculation order to handle overlap
  2218 + PMUL(1);
  2219 + PMUL(0);
  2220 +#undef PMUL
  2221 +
  2222 + DT0 = d.d;
  2223 +}
  2224 +
  2225 +void OPPROTO op_fexpand(void)
  2226 +{
  2227 + vis32 s;
  2228 + vis64 d;
  2229 +
  2230 + s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
  2231 + d.d = DT1;
  2232 + d.VIS_L64(0) = s.VIS_W32(0) << 4;
  2233 + d.VIS_L64(1) = s.VIS_W32(1) << 4;
  2234 + d.VIS_L64(2) = s.VIS_W32(2) << 4;
  2235 + d.VIS_L64(3) = s.VIS_W32(3) << 4;
  2236 +
  2237 + DT0 = d.d;
  2238 +}
  2239 +
  2240 +#define VIS_OP(name, F) \
  2241 + void OPPROTO name##16(void) \
  2242 + { \
  2243 + vis64 s, d; \
  2244 + \
  2245 + s.d = DT0; \
  2246 + d.d = DT1; \
  2247 + \
  2248 + d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
  2249 + d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
  2250 + d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
  2251 + d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
  2252 + \
  2253 + DT0 = d.d; \
  2254 + } \
  2255 + \
  2256 + void OPPROTO name##16s(void) \
  2257 + { \
  2258 + vis32 s, d; \
  2259 + \
  2260 + s.f = FT0; \
  2261 + d.f = FT1; \
  2262 + \
  2263 + d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
  2264 + d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
  2265 + \
  2266 + FT0 = d.f; \
  2267 + } \
  2268 + \
  2269 + void OPPROTO name##32(void) \
  2270 + { \
  2271 + vis64 s, d; \
  2272 + \
  2273 + s.d = DT0; \
  2274 + d.d = DT1; \
  2275 + \
  2276 + d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
  2277 + d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
  2278 + \
  2279 + DT0 = d.d; \
  2280 + } \
  2281 + \
  2282 + void OPPROTO name##32s(void) \
  2283 + { \
  2284 + vis32 s, d; \
  2285 + \
  2286 + s.f = FT0; \
  2287 + d.f = FT1; \
  2288 + \
  2289 + d.l = F(d.l, s.l); \
  2290 + \
  2291 + FT0 = d.f; \
  2292 + }
  2293 +
  2294 +#define FADD(a, b) ((a) + (b))
  2295 +#define FSUB(a, b) ((a) - (b))
  2296 +VIS_OP(op_fpadd, FADD)
  2297 +VIS_OP(op_fpsub, FSUB)
  2298 +
  2299 +#define VIS_CMPOP(name, F) \
  2300 + void OPPROTO name##16(void) \
  2301 + { \
  2302 + vis64 s, d; \
  2303 + \
  2304 + s.d = DT0; \
  2305 + d.d = DT1; \
  2306 + \
  2307 + d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
  2308 + d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
  2309 + d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
  2310 + d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
  2311 + \
  2312 + DT0 = d.d; \
  2313 + } \
  2314 + \
  2315 + void OPPROTO name##32(void) \
  2316 + { \
  2317 + vis64 s, d; \
  2318 + \
  2319 + s.d = DT0; \
  2320 + d.d = DT1; \
  2321 + \
  2322 + d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
  2323 + d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
  2324 + \
  2325 + DT0 = d.d; \
  2326 + }
  2327 +
  2328 +#define FCMPGT(a, b) ((a) > (b))
  2329 +#define FCMPEQ(a, b) ((a) == (b))
  2330 +#define FCMPLE(a, b) ((a) <= (b))
  2331 +#define FCMPNE(a, b) ((a) != (b))
  2332 +
  2333 +VIS_CMPOP(op_fcmpgt, FCMPGT)
  2334 +VIS_CMPOP(op_fcmpeq, FCMPEQ)
  2335 +VIS_CMPOP(op_fcmple, FCMPLE)
  2336 +VIS_CMPOP(op_fcmpne, FCMPNE)
  2337 +
1887 2338 #endif
... ...
target-sparc/translate.c
  View file @e9ebed4
... ... @@ -350,6 +350,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
350 350 // 'a' versions allowed to user depending on asi
351 351 #if defined(CONFIG_USER_ONLY)
352 352 #define supervisor(dc) 0
  353 +#define hypervisor(dc) 0
353 354 #define gen_op_ldst(name) gen_op_##name##_raw()
354 355 #define OP_LD_TABLE(width) \
355 356 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
... ... @@ -405,6 +406,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
405 406 }
406 407  
407 408 #define supervisor(dc) (dc->mem_idx == 1)
  409 +#define hypervisor(dc) (dc->mem_idx == 2)
408 410 #endif
409 411 #else
410 412 #if defined(CONFIG_USER_ONLY)
... ... @@ -1218,14 +1220,40 @@ static void disas_sparc_insn(DisasContext * dc)
1218 1220 goto illegal_insn;
1219 1221 }
1220 1222 #if !defined(CONFIG_USER_ONLY)
  1223 + } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1221 1224 #ifndef TARGET_SPARC64
1222   - } else if (xop == 0x29) { /* rdpsr / V9 unimp */
1223 1225 if (!supervisor(dc))
1224 1226 goto priv_insn;
1225 1227 gen_op_rdpsr();
  1228 +#else
  1229 + if (!hypervisor(dc))
  1230 + goto priv_insn;
  1231 + rs1 = GET_FIELD(insn, 13, 17);
  1232 + switch (rs1) {
  1233 + case 0: // hpstate
  1234 + // gen_op_rdhpstate();
  1235 + break;
  1236 + case 1: // htstate
  1237 + // gen_op_rdhtstate();
  1238 + break;
  1239 + case 3: // hintp
  1240 + gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
  1241 + break;
  1242 + case 5: // htba
  1243 + gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
  1244 + break;
  1245 + case 6: // hver
  1246 + gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
  1247 + break;
  1248 + case 31: // hstick_cmpr
  1249 + gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
  1250 + break;
  1251 + default:
  1252 + goto illegal_insn;
  1253 + }
  1254 +#endif
1226 1255 gen_movl_T0_reg(rd);
1227 1256 break;
1228   -#endif
1229 1257 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1230 1258 if (!supervisor(dc))
1231 1259 goto priv_insn;
... ... @@ -1277,6 +1305,14 @@ static void disas_sparc_insn(DisasContext * dc)
1277 1305 case 14: // wstate
1278 1306 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1279 1307 break;
  1308 + case 16: // UA2005 gl
  1309 + gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
  1310 + break;
  1311 + case 26: // UA2005 strand status
  1312 + if (!hypervisor(dc))
  1313 + goto priv_insn;
  1314 + gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
  1315 + break;
1280 1316 case 31: // ver
1281 1317 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1282 1318 break;
... ... @@ -1997,6 +2033,11 @@ static void disas_sparc_insn(DisasContext * dc)
1997 2033 case 1:
1998 2034 gen_op_restored();
1999 2035 break;
  2036 + case 2: /* UA2005 allclean */
  2037 + case 3: /* UA2005 otherw */
  2038 + case 4: /* UA2005 normalw */
  2039 + case 5: /* UA2005 invalw */
  2040 + // XXX
2000 2041 default:
2001 2042 goto illegal_insn;
2002 2043 }
... ... @@ -2068,6 +2109,14 @@ static void disas_sparc_insn(DisasContext * dc)
2068 2109 case 14: // wstate
2069 2110 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2070 2111 break;
  2112 + case 16: // UA2005 gl
  2113 + gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
  2114 + break;
  2115 + case 26: // UA2005 strand status
  2116 + if (!hypervisor(dc))
  2117 + goto priv_insn;
  2118 + gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
  2119 + break;
2071 2120 default:
2072 2121 goto illegal_insn;
2073 2122 }
... ... @@ -2076,17 +2125,46 @@ static void disas_sparc_insn(DisasContext * dc)
2076 2125 #endif
2077 2126 }
2078 2127 break;
2079   -#ifndef TARGET_SPARC64
2080   - case 0x33: /* wrtbr, V9 unimp */
  2128 + case 0x33: /* wrtbr, UA2005 wrhpr */
2081 2129 {
  2130 +#ifndef TARGET_SPARC64
2082 2131 if (!supervisor(dc))
2083 2132 goto priv_insn;
2084 2133 gen_op_xor_T1_T0();
2085   - gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
  2134 + gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
  2135 +#else
  2136 + if (!hypervisor(dc))
  2137 + goto priv_insn;
  2138 + gen_op_xor_T1_T0();
  2139 + switch (rd) {
  2140 + case 0: // hpstate
  2141 + // XXX gen_op_wrhpstate();
  2142 + save_state(dc);
  2143 + gen_op_next_insn();
  2144 + gen_op_movl_T0_0();
  2145 + gen_op_exit_tb();
  2146 + dc->is_br = 1;
  2147 + break;
  2148 + case 1: // htstate
  2149 + // XXX gen_op_wrhtstate();
  2150 + break;
  2151 + case 3: // hintp
  2152 + gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
  2153 + break;
  2154 + case 5: // htba
  2155 + gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
  2156 + break;
  2157 + case 31: // hstick_cmpr
  2158 + gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
  2159 + break;
  2160 + case 6: // hver readonly
  2161 + default:
  2162 + goto illegal_insn;
  2163 + }
  2164 +#endif
2086 2165 }
2087 2166 break;
2088 2167 #endif
2089   -#endif
2090 2168 #ifdef TARGET_SPARC64
2091 2169 case 0x2c: /* V9 movcc */
2092 2170 {
... ... @@ -2164,77 +2242,393 @@ static void disas_sparc_insn(DisasContext * dc)
2164 2242 int opf = GET_FIELD_SP(insn, 5, 13);
2165 2243 rs1 = GET_FIELD(insn, 13, 17);
2166 2244 rs2 = GET_FIELD(insn, 27, 31);
  2245 + if (gen_trap_ifnofpu(dc))
  2246 + goto jmp_insn;
2167 2247  
2168 2248 switch (opf) {
  2249 + case 0x000: /* VIS I edge8cc */
  2250 + case 0x001: /* VIS II edge8n */
  2251 + case 0x002: /* VIS I edge8lcc */
  2252 + case 0x003: /* VIS II edge8ln */
  2253 + case 0x004: /* VIS I edge16cc */
  2254 + case 0x005: /* VIS II edge16n */
  2255 + case 0x006: /* VIS I edge16lcc */
  2256 + case 0x007: /* VIS II edge16ln */
  2257 + case 0x008: /* VIS I edge32cc */
  2258 + case 0x009: /* VIS II edge32n */
  2259 + case 0x00a: /* VIS I edge32lcc */
  2260 + case 0x00b: /* VIS II edge32ln */
  2261 + // XXX
  2262 + goto illegal_insn;
  2263 + case 0x010: /* VIS I array8 */
  2264 + gen_movl_reg_T0(rs1);
  2265 + gen_movl_reg_T1(rs2);
  2266 + gen_op_array8();
  2267 + gen_movl_T0_reg(rd);
  2268 + break;
  2269 + case 0x012: /* VIS I array16 */
  2270 + gen_movl_reg_T0(rs1);
  2271 + gen_movl_reg_T1(rs2);
  2272 + gen_op_array16();
  2273 + gen_movl_T0_reg(rd);
  2274 + break;
  2275 + case 0x014: /* VIS I array32 */
  2276 + gen_movl_reg_T0(rs1);
  2277 + gen_movl_reg_T1(rs2);
  2278 + gen_op_array32();
  2279 + gen_movl_T0_reg(rd);
  2280 + break;
2169 2281 case 0x018: /* VIS I alignaddr */
2170   - if (gen_trap_ifnofpu(dc))
2171   - goto jmp_insn;
2172 2282 gen_movl_reg_T0(rs1);
2173 2283 gen_movl_reg_T1(rs2);
2174 2284 gen_op_alignaddr();
2175 2285 gen_movl_T0_reg(rd);
2176 2286 break;
  2287 + case 0x019: /* VIS II bmask */
2177 2288 case 0x01a: /* VIS I alignaddrl */
2178   - if (gen_trap_ifnofpu(dc))
2179   - goto jmp_insn;
2180 2289 // XXX
  2290 + goto illegal_insn;
  2291 + case 0x020: /* VIS I fcmple16 */
  2292 + gen_op_load_fpr_DT0(rs1);
  2293 + gen_op_load_fpr_DT1(rs2);
  2294 + gen_op_fcmple16();
  2295 + gen_op_store_DT0_fpr(rd);
  2296 + break;
  2297 + case 0x022: /* VIS I fcmpne16 */
  2298 + gen_op_load_fpr_DT0(rs1);
  2299 + gen_op_load_fpr_DT1(rs2);
  2300 + gen_op_fcmpne16();
  2301 + gen_op_store_DT0_fpr(rd);
2181 2302 break;
  2303 + case 0x024: /* VIS I fcmple32 */
  2304 + gen_op_load_fpr_DT0(rs1);
  2305 + gen_op_load_fpr_DT1(rs2);
  2306 + gen_op_fcmple32();
  2307 + gen_op_store_DT0_fpr(rd);
  2308 + break;
  2309 + case 0x026: /* VIS I fcmpne32 */
  2310 + gen_op_load_fpr_DT0(rs1);
  2311 + gen_op_load_fpr_DT1(rs2);
  2312 + gen_op_fcmpne32();
  2313 + gen_op_store_DT0_fpr(rd);
  2314 + break;
  2315 + case 0x028: /* VIS I fcmpgt16 */
  2316 + gen_op_load_fpr_DT0(rs1);
  2317 + gen_op_load_fpr_DT1(rs2);
  2318 + gen_op_fcmpgt16();
  2319 + gen_op_store_DT0_fpr(rd);
  2320 + break;
  2321 + case 0x02a: /* VIS I fcmpeq16 */
  2322 + gen_op_load_fpr_DT0(rs1);
  2323 + gen_op_load_fpr_DT1(rs2);
  2324 + gen_op_fcmpeq16();
  2325 + gen_op_store_DT0_fpr(rd);
  2326 + break;
  2327 + case 0x02c: /* VIS I fcmpgt32 */
  2328 + gen_op_load_fpr_DT0(rs1);
  2329 + gen_op_load_fpr_DT1(rs2);
  2330 + gen_op_fcmpgt32();
  2331 + gen_op_store_DT0_fpr(rd);
  2332 + break;
  2333 + case 0x02e: /* VIS I fcmpeq32 */
  2334 + gen_op_load_fpr_DT0(rs1);
  2335 + gen_op_load_fpr_DT1(rs2);
  2336 + gen_op_fcmpeq32();
  2337 + gen_op_store_DT0_fpr(rd);
  2338 + break;
  2339 + case 0x031: /* VIS I fmul8x16 */
  2340 + gen_op_load_fpr_DT0(rs1);
  2341 + gen_op_load_fpr_DT1(rs2);
  2342 + gen_op_fmul8x16();
  2343 + gen_op_store_DT0_fpr(rd);
  2344 + break;
  2345 + case 0x033: /* VIS I fmul8x16au */
  2346 + gen_op_load_fpr_DT0(rs1);
  2347 + gen_op_load_fpr_DT1(rs2);
  2348 + gen_op_fmul8x16au();
  2349 + gen_op_store_DT0_fpr(rd);
  2350 + break;
  2351 + case 0x035: /* VIS I fmul8x16al */
  2352 + gen_op_load_fpr_DT0(rs1);
  2353 + gen_op_load_fpr_DT1(rs2);
  2354 + gen_op_fmul8x16al();
  2355 + gen_op_store_DT0_fpr(rd);
  2356 + break;
  2357 + case 0x036: /* VIS I fmul8sux16 */
  2358 + gen_op_load_fpr_DT0(rs1);
  2359 + gen_op_load_fpr_DT1(rs2);
  2360 + gen_op_fmul8sux16();
  2361 + gen_op_store_DT0_fpr(rd);
  2362 + break;
  2363 + case 0x037: /* VIS I fmul8ulx16 */
  2364 + gen_op_load_fpr_DT0(rs1);
  2365 + gen_op_load_fpr_DT1(rs2);
  2366 + gen_op_fmul8ulx16();
  2367 + gen_op_store_DT0_fpr(rd);
  2368 + break;
  2369 + case 0x038: /* VIS I fmuld8sux16 */
  2370 + gen_op_load_fpr_DT0(rs1);
  2371 + gen_op_load_fpr_DT1(rs2);
  2372 + gen_op_fmuld8sux16();
  2373 + gen_op_store_DT0_fpr(rd);
  2374 + break;
  2375 + case 0x039: /* VIS I fmuld8ulx16 */
  2376 + gen_op_load_fpr_DT0(rs1);
  2377 + gen_op_load_fpr_DT1(rs2);
  2378 + gen_op_fmuld8ulx16();
  2379 + gen_op_store_DT0_fpr(rd);
  2380 + break;
  2381 + case 0x03a: /* VIS I fpack32 */
  2382 + case 0x03b: /* VIS I fpack16 */
  2383 + case 0x03d: /* VIS I fpackfix */
  2384 + case 0x03e: /* VIS I pdist */
  2385 + // XXX
  2386 + goto illegal_insn;
2182 2387 case 0x048: /* VIS I faligndata */
2183   - if (gen_trap_ifnofpu(dc))
2184   - goto jmp_insn;
2185 2388 gen_op_load_fpr_DT0(rs1);
2186 2389 gen_op_load_fpr_DT1(rs2);
2187 2390 gen_op_faligndata();
2188 2391 gen_op_store_DT0_fpr(rd);
2189 2392 break;
  2393 + case 0x04b: /* VIS I fpmerge */
  2394 + gen_op_load_fpr_DT0(rs1);
  2395 + gen_op_load_fpr_DT1(rs2);
  2396 + gen_op_fpmerge();
  2397 + gen_op_store_DT0_fpr(rd);
  2398 + break;
  2399 + case 0x04c: /* VIS II bshuffle */
  2400 + // XXX
  2401 + goto illegal_insn;
  2402 + case 0x04d: /* VIS I fexpand */
  2403 + gen_op_load_fpr_DT0(rs1);
  2404 + gen_op_load_fpr_DT1(rs2);
  2405 + gen_op_fexpand();
  2406 + gen_op_store_DT0_fpr(rd);
  2407 + break;
  2408 + case 0x050: /* VIS I fpadd16 */
  2409 + gen_op_load_fpr_DT0(rs1);
  2410 + gen_op_load_fpr_DT1(rs2);
  2411 + gen_op_fpadd16();
  2412 + gen_op_store_DT0_fpr(rd);
  2413 + break;
  2414 + case 0x051: /* VIS I fpadd16s */
  2415 + gen_op_load_fpr_FT0(rs1);
  2416 + gen_op_load_fpr_FT1(rs2);
  2417 + gen_op_fpadd16s();
  2418 + gen_op_store_FT0_fpr(rd);
  2419 + break;
  2420 + case 0x052: /* VIS I fpadd32 */
  2421 + gen_op_load_fpr_DT0(rs1);
  2422 + gen_op_load_fpr_DT1(rs2);
  2423 + gen_op_fpadd32();
  2424 + gen_op_store_DT0_fpr(rd);
  2425 + break;
  2426 + case 0x053: /* VIS I fpadd32s */
  2427 + gen_op_load_fpr_FT0(rs1);
  2428 + gen_op_load_fpr_FT1(rs2);
  2429 + gen_op_fpadd32s();
  2430 + gen_op_store_FT0_fpr(rd);
  2431 + break;
  2432 + case 0x054: /* VIS I fpsub16 */
  2433 + gen_op_load_fpr_DT0(rs1);
  2434 + gen_op_load_fpr_DT1(rs2);
  2435 + gen_op_fpsub16();
  2436 + gen_op_store_DT0_fpr(rd);
  2437 + break;
  2438 + case 0x055: /* VIS I fpsub16s */
  2439 + gen_op_load_fpr_FT0(rs1);
  2440 + gen_op_load_fpr_FT1(rs2);
  2441 + gen_op_fpsub16s();
  2442 + gen_op_store_FT0_fpr(rd);
  2443 + break;
  2444 + case 0x056: /* VIS I fpsub32 */
  2445 + gen_op_load_fpr_DT0(rs1);
  2446 + gen_op_load_fpr_DT1(rs2);
  2447 + gen_op_fpadd32();
  2448 + gen_op_store_DT0_fpr(rd);
  2449 + break;
  2450 + case 0x057: /* VIS I fpsub32s */
  2451 + gen_op_load_fpr_FT0(rs1);
  2452 + gen_op_load_fpr_FT1(rs2);
  2453 + gen_op_fpsub32s();
  2454 + gen_op_store_FT0_fpr(rd);
  2455 + break;
2190 2456 case 0x060: /* VIS I fzero */
2191   - if (gen_trap_ifnofpu(dc))
2192   - goto jmp_insn;
2193 2457 gen_op_movl_DT0_0();
2194 2458 gen_op_store_DT0_fpr(rd);
2195 2459 break;
2196 2460 case 0x061: /* VIS I fzeros */
2197   - if (gen_trap_ifnofpu(dc))
2198   - goto jmp_insn;
2199 2461 gen_op_movl_FT0_0();
2200 2462 gen_op_store_FT0_fpr(rd);
2201 2463 break;
  2464 + case 0x062: /* VIS I fnor */
  2465 + gen_op_load_fpr_DT0(rs1);
  2466 + gen_op_load_fpr_DT1(rs2);
  2467 + gen_op_fnor();
  2468 + gen_op_store_DT0_fpr(rd);
  2469 + break;
  2470 + case 0x063: /* VIS I fnors */
  2471 + gen_op_load_fpr_FT0(rs1);
  2472 + gen_op_load_fpr_FT1(rs2);
  2473 + gen_op_fnors();
  2474 + gen_op_store_FT0_fpr(rd);
  2475 + break;
  2476 + case 0x064: /* VIS I fandnot2 */
  2477 + gen_op_load_fpr_DT1(rs1);
  2478 + gen_op_load_fpr_DT0(rs2);
  2479 + gen_op_fandnot();
  2480 + gen_op_store_DT0_fpr(rd);
  2481 + break;
  2482 + case 0x065: /* VIS I fandnot2s */
  2483 + gen_op_load_fpr_FT1(rs1);
  2484 + gen_op_load_fpr_FT0(rs2);
  2485 + gen_op_fandnots();
  2486 + gen_op_store_FT0_fpr(rd);
  2487 + break;
  2488 + case 0x066: /* VIS I fnot2 */
  2489 + gen_op_load_fpr_DT1(rs2);
  2490 + gen_op_fnot();
  2491 + gen_op_store_DT0_fpr(rd);
  2492 + break;
  2493 + case 0x067: /* VIS I fnot2s */
  2494 + gen_op_load_fpr_FT1(rs2);
  2495 + gen_op_fnot();
  2496 + gen_op_store_FT0_fpr(rd);
  2497 + break;
  2498 + case 0x068: /* VIS I fandnot1 */
  2499 + gen_op_load_fpr_DT0(rs1);
  2500 + gen_op_load_fpr_DT1(rs2);
  2501 + gen_op_fandnot();
  2502 + gen_op_store_DT0_fpr(rd);
  2503 + break;
  2504 + case 0x069: /* VIS I fandnot1s */
  2505 + gen_op_load_fpr_FT0(rs1);
  2506 + gen_op_load_fpr_FT1(rs2);
  2507 + gen_op_fandnots();
  2508 + gen_op_store_FT0_fpr(rd);
  2509 + break;
  2510 + case 0x06a: /* VIS I fnot1 */
  2511 + gen_op_load_fpr_DT1(rs1);
  2512 + gen_op_fnot();
  2513 + gen_op_store_DT0_fpr(rd);
  2514 + break;
  2515 + case 0x06b: /* VIS I fnot1s */
  2516 + gen_op_load_fpr_FT1(rs1);
  2517 + gen_op_fnot();
  2518 + gen_op_store_FT0_fpr(rd);
  2519 + break;
  2520 + case 0x06c: /* VIS I fxor */
  2521 + gen_op_load_fpr_DT0(rs1);
  2522 + gen_op_load_fpr_DT1(rs2);
  2523 + gen_op_fxor();
  2524 + gen_op_store_DT0_fpr(rd);
  2525 + break;
  2526 + case 0x06d: /* VIS I fxors */
  2527 + gen_op_load_fpr_FT0(rs1);
  2528 + gen_op_load_fpr_FT1(rs2);
  2529 + gen_op_fxors();
  2530 + gen_op_store_FT0_fpr(rd);
  2531 + break;
  2532 + case 0x06e: /* VIS I fnand */
  2533 + gen_op_load_fpr_DT0(rs1);
  2534 + gen_op_load_fpr_DT1(rs2);
  2535 + gen_op_fnand();
  2536 + gen_op_store_DT0_fpr(rd);
  2537 + break;
  2538 + case 0x06f: /* VIS I fnands */
  2539 + gen_op_load_fpr_FT0(rs1);
  2540 + gen_op_load_fpr_FT1(rs2);
  2541 + gen_op_fnands();
  2542 + gen_op_store_FT0_fpr(rd);
  2543 + break;
  2544 + case 0x070: /* VIS I fand */
  2545 + gen_op_load_fpr_DT0(rs1);
  2546 + gen_op_load_fpr_DT1(rs2);
  2547 + gen_op_fand();
  2548 + gen_op_store_DT0_fpr(rd);
  2549 + break;
  2550 + case 0x071: /* VIS I fands */
  2551 + gen_op_load_fpr_FT0(rs1);
  2552 + gen_op_load_fpr_FT1(rs2);
  2553 + gen_op_fands();
  2554 + gen_op_store_FT0_fpr(rd);
  2555 + break;
  2556 + case 0x072: /* VIS I fxnor */
  2557 + gen_op_load_fpr_DT0(rs1);
  2558 + gen_op_load_fpr_DT1(rs2);
  2559 + gen_op_fxnor();
  2560 + gen_op_store_DT0_fpr(rd);
  2561 + break;
  2562 + case 0x073: /* VIS I fxnors */
  2563 + gen_op_load_fpr_FT0(rs1);
  2564 + gen_op_load_fpr_FT1(rs2);
  2565 + gen_op_fxnors();
  2566 + gen_op_store_FT0_fpr(rd);
  2567 + break;
2202 2568 case 0x074: /* VIS I fsrc1 */
2203   - if (gen_trap_ifnofpu(dc))
2204   - goto jmp_insn;
2205 2569 gen_op_load_fpr_DT0(rs1);
2206 2570 gen_op_store_DT0_fpr(rd);
2207 2571 break;
2208 2572 case 0x075: /* VIS I fsrc1s */
2209   - if (gen_trap_ifnofpu(dc))
2210   - goto jmp_insn;
2211 2573 gen_op_load_fpr_FT0(rs1);
2212 2574 gen_op_store_FT0_fpr(rd);
2213 2575 break;
  2576 + case 0x076: /* VIS I fornot2 */
  2577 + gen_op_load_fpr_DT1(rs1);
  2578 + gen_op_load_fpr_DT0(rs2);
  2579 + gen_op_fornot();
  2580 + gen_op_store_DT0_fpr(rd);
  2581 + break;
  2582 + case 0x077: /* VIS I fornot2s */
  2583 + gen_op_load_fpr_FT1(rs1);
  2584 + gen_op_load_fpr_FT0(rs2);
  2585 + gen_op_fornots();
  2586 + gen_op_store_FT0_fpr(rd);
  2587 + break;
2214 2588 case 0x078: /* VIS I fsrc2 */
2215   - if (gen_trap_ifnofpu(dc))
2216   - goto jmp_insn;
2217 2589 gen_op_load_fpr_DT0(rs2);
2218 2590 gen_op_store_DT0_fpr(rd);
2219 2591 break;
2220 2592 case 0x079: /* VIS I fsrc2s */
2221   - if (gen_trap_ifnofpu(dc))
2222   - goto jmp_insn;
2223 2593 gen_op_load_fpr_FT0(rs2);
2224 2594 gen_op_store_FT0_fpr(rd);
2225 2595 break;
  2596 + case 0x07a: /* VIS I fornot1 */
  2597 + gen_op_load_fpr_DT0(rs1);
  2598 + gen_op_load_fpr_DT1(rs2);
  2599 + gen_op_fornot();
  2600 + gen_op_store_DT0_fpr(rd);
  2601 + break;
  2602 + case 0x07b: /* VIS I fornot1s */
  2603 + gen_op_load_fpr_FT0(rs1);
  2604 + gen_op_load_fpr_FT1(rs2);
  2605 + gen_op_fornots();
  2606 + gen_op_store_FT0_fpr(rd);
  2607 + break;
  2608 + case 0x07c: /* VIS I for */
  2609 + gen_op_load_fpr_DT0(rs1);
  2610 + gen_op_load_fpr_DT1(rs2);
  2611 + gen_op_for();
  2612 + gen_op_store_DT0_fpr(rd);
  2613 + break;
  2614 + case 0x07d: /* VIS I fors */
  2615 + gen_op_load_fpr_FT0(rs1);
  2616 + gen_op_load_fpr_FT1(rs2);
  2617 + gen_op_fors();
  2618 + gen_op_store_FT0_fpr(rd);
  2619 + break;
2226 2620 case 0x07e: /* VIS I fone */
2227   - if (gen_trap_ifnofpu(dc))
2228   - goto jmp_insn;
2229 2621 gen_op_movl_DT0_1();
2230 2622 gen_op_store_DT0_fpr(rd);
2231 2623 break;
2232 2624 case 0x07f: /* VIS I fones */
2233   - if (gen_trap_ifnofpu(dc))
2234   - goto jmp_insn;
2235 2625 gen_op_movl_FT0_1();
2236 2626 gen_op_store_FT0_fpr(rd);
2237 2627 break;
  2628 + case 0x080: /* VIS I shutdown */
  2629 + case 0x081: /* VIS II siam */
  2630 + // XXX
  2631 + goto illegal_insn;
2238 2632 default:
2239 2633 goto illegal_insn;
2240 2634 }
... ...