gwj / at91sam9263 · Commits

Commit e97b640d471ed15bc35ce4784c2d93eb369d3ba0

Authored by blueswir1
1 parent 2991990b

Try to avoid glibc global register mangling, again 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 45 additions and 26 deletions
Makefile.target
  View file @e97b640
... ... @@ -121,10 +121,12 @@ ifeq ($(ARCH),sparc)
121 121 endif
122 122  
123 123 ifeq ($(ARCH),sparc64)
124   - CFLAGS+=-ffixed-g1 -ffixed-g4 -ffixed-g5 -ffixed-g7
125 124 OP_CFLAGS+=-mcpu=ultrasparc -m64 -fno-delayed-branch -ffixed-i0
126 125 ifneq ($(CONFIG_SOLARIS),yes)
127   - OP_CFLAGS+=-ffixed-g1 -ffixed-g4 -ffixed-g5 -ffixed-g7
  126 + CFLAGS+=-ffixed-g5 -ffixed-g6 -ffixed-g7
  127 + OP_CFLAGS+=-ffixed-g5 -ffixed-g6 -ffixed-g7
  128 + else
  129 + CFLAGS+=-ffixed-g1 -ffixed-g4 -ffixed-g5 -ffixed-g7
128 130 endif
129 131 endif
130 132  
... ...
dyngen-exec.h
  View file @e97b640
... ... @@ -146,10 +146,9 @@ extern int printf(const char *, ...);
146 146 #define AREG4 "g6"
147 147 #else
148 148 #ifdef __sparc_v9__
149   -#define AREG0 "g1"
150   -#define AREG1 "g4"
151   -#define AREG2 "g5"
152   -#define AREG3 "g7"
  149 +#define AREG0 "g5"
  150 +#define AREG1 "g6"
  151 +#define AREG2 "g7"
153 152 #else
154 153 #define AREG0 "g6"
155 154 #define AREG1 "g1"
... ...
tcg/sparc/tcg-target.c
  View file @e97b640
... ... @@ -839,16 +839,34 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
839 839 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
840 840 break;
841 841 case INDEX_op_call:
842   - if (const_args[0]) {
843   - tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
844   - - (tcg_target_ulong)s->code_ptr) >> 2)
845   - & 0x3fffffff));
846   - tcg_out_nop(s);
847   - } else {
848   - tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
849   - tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
850   - INSN_RS2(TCG_REG_G0));
851   - tcg_out_nop(s);
  842 + {
  843 + unsigned int st_op, ld_op;
  844 +
  845 +#ifdef __arch64__
  846 + st_op = STX;
  847 + ld_op = LDX;
  848 +#else
  849 + st_op = STW;
  850 + ld_op = LDUW;
  851 +#endif
  852 + if (const_args[0])
  853 + tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
  854 + - (tcg_target_ulong)s->code_ptr) >> 2)
  855 + & 0x3fffffff));
  856 + else {
  857 + tcg_out_ld_ptr(s, TCG_REG_I5,
  858 + (tcg_target_long)(s->tb_next + args[0]));
  859 + tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
  860 + INSN_RS2(TCG_REG_G0));
  861 + }
  862 + /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
  863 + global registers */
  864 + tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
  865 + TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
  866 + st_op); // delay slot
  867 + tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
  868 + TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
  869 + ld_op);
852 870 }
853 871 break;
854 872 case INDEX_op_jmp:
... ...
tcg/sparc/tcg-target.h
  View file @e97b640
... ... @@ -72,14 +72,15 @@ enum {
72 72 #define TCG_CT_CONST_S13 0x200
73 73  
74 74 /* used for function call generation */
75   -#define TCG_REG_CALL_STACK TCG_REG_O6
  75 +#define TCG_REG_CALL_STACK TCG_REG_I6
76 76 #ifdef __arch64__
77   -#define TCG_TARGET_STACK_MINFRAME 176
78   -#define TCG_TARGET_CALL_STACK_OFFSET (2047 + 176)
  77 +// Reserve space for AREG0
  78 +#define TCG_TARGET_STACK_MINFRAME (176 + 2 * sizeof(long))
  79 +#define TCG_TARGET_CALL_STACK_OFFSET (2047 + TCG_TARGET_STACK_MINFRAME)
79 80 #define TCG_TARGET_STACK_ALIGN 16
80 81 #else
81   -#define TCG_TARGET_STACK_MINFRAME 92
82   -#define TCG_TARGET_CALL_STACK_OFFSET 92
  82 +#define TCG_TARGET_STACK_MINFRAME (92 + 2 * sizeof(long))
  83 +#define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
83 84 #define TCG_TARGET_STACK_ALIGN 8
84 85 #endif
85 86  
... ... @@ -90,7 +91,7 @@ enum {
90 91 //#define TCG_TARGET_HAS_neg_i64
91 92  
92 93  
93   -/* Note: must be synced with dyngen-exec.h */
  94 +/* Note: must be synced with dyngen-exec.h and Makefile.target */
94 95 #ifdef HOST_SOLARIS
95 96 #define TCG_AREG0 TCG_REG_G2
96 97 #define TCG_AREG1 TCG_REG_G3
... ... @@ -98,10 +99,9 @@ enum {
98 99 #define TCG_AREG3 TCG_REG_G5
99 100 #define TCG_AREG4 TCG_REG_G6
100 101 #elif defined(__sparc_v9__)
101   -#define TCG_AREG0 TCG_REG_G1
102   -#define TCG_AREG1 TCG_REG_G4
103   -#define TCG_AREG2 TCG_REG_G5
104   -#define TCG_AREG3 TCG_REG_G7
  102 +#define TCG_AREG0 TCG_REG_G5
  103 +#define TCG_AREG1 TCG_REG_G6
  104 +#define TCG_AREG2 TCG_REG_G7
105 105 #else
106 106 #define TCG_AREG0 TCG_REG_G6
107 107 #define TCG_AREG1 TCG_REG_G1
... ...