gwj / at91sam9263 · Commits

Commit e927bb0070c9f946cfe4a276ebccfab9c5f03e0e

Authored by balrog
1 parent a350e694

Nokia N810 basic system emulation. 

Add TSC2005 touchscreen controller.
Add N810 machine definition.
Unify N800 and N810 ATAG list generation.
Pass a word length parameter on every SPI transfer.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4374 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 7 changed files with 324 additions and 210 deletions
Makefile.target
  View file @e927bb0
... ... @@ -622,6 +622,7 @@ OBJS+= omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
622 622 OBJS+= omap2.o omap_dss.o
623 623 OBJS+= palm.o tsc210x.o
624 624 OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
  625 +OBJS+= tsc2005.o
625 626 OBJS+= mst_fpga.o mainstone.o
626 627 OBJS+= musicpal.o pflash_cfi02.o
627 628 CPPFLAGS += -DHAS_AUDIO
... ...
hw/boards.h
  View file @e927bb0
... ... @@ -86,6 +86,7 @@ extern QEMUMachine palmte_machine;
86 86  
87 87 /* nseries.c */
88 88 extern QEMUMachine n800_machine;
  89 +extern QEMUMachine n810_machine;
89 90  
90 91 /* gumstix.c */
91 92 extern QEMUMachine connex_machine;
... ...
hw/devices.h
  View file @e927bb0
... ... @@ -23,11 +23,16 @@ struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
23 23 struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
24 24 qemu_irq dav, AudioState *audio);
25 25 struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
26   -uint32_t tsc210x_txrx(void *opaque, uint32_t value);
  26 +uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
27 27 void tsc210x_set_transform(struct uwire_slave_s *chip,
28 28 struct mouse_transform_info_s *info);
29 29 void tsc210x_key_event(struct uwire_slave_s *chip, int key, int down);
30 30  
  31 +/* tsc2005.c */
  32 +void *tsc2005_init(qemu_irq pintdav);
  33 +uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
  34 +void tsc2005_set_transform(void *opaque, struct mouse_transform_info_s *info);
  35 +
31 36 /* stellaris_input.c */
32 37 void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
33 38  
... ...
hw/nseries.c
  View file @e927bb0
... ... @@ -37,7 +37,11 @@ struct n800_s {
37 37 struct omap_mpu_state_s *cpu;
38 38  
39 39 struct rfbi_chip_s blizzard;
40   - struct uwire_slave_s *ts;
  40 + struct {
  41 + void *opaque;
  42 + uint32_t (*txrx)(void *opaque, uint32_t value, int len);
  43 + struct uwire_slave_s *chip;
  44 + } ts;
41 45 i2c_bus *i2c;
42 46  
43 47 int keymap[0x80];
... ... @@ -48,34 +52,38 @@ struct n800_s {
48 52 };
49 53  
50 54 /* GPIO pins */
51   -#define N800_TUSB_ENABLE_GPIO 0
  55 +#define N8X0_TUSB_ENABLE_GPIO 0
52 56 #define N800_MMC2_WP_GPIO 8
53 57 #define N800_UNKNOWN_GPIO0 9 /* out */
54 58 #define N800_UNKNOWN_GPIO1 10 /* out */
55 59 #define N800_CAM_TURN_GPIO 12
  60 +#define N810_GPS_RESET_GPIO 12
56 61 #define N800_BLIZZARD_POWERDOWN_GPIO 15
57 62 #define N800_MMC1_WP_GPIO 23
58 63 #define N8X0_ONENAND_GPIO 26
  64 +#define N810_BLIZZARD_RESET_GPIO 30
59 65 #define N800_UNKNOWN_GPIO2 53 /* out */
60 66 #define N8X0_TUSB_INT_GPIO 58
61   -#define N800_BT_WKUP_GPIO 61
62   -#define N800_STI_GPIO 62
  67 +#define N8X0_BT_WKUP_GPIO 61
  68 +#define N8X0_STI_GPIO 62
63 69 #define N8X0_CBUS_SEL_GPIO 64
64   -#define N8X0_CBUS_CLK_GPIO 65 /* sure? */
65   -#define N8X0_CBUS_DAT_GPIO 66
66   -#define N800_WLAN_IRQ_GPIO 87
67   -#define N800_BT_RESET_GPIO 92
68   -#define N800_TEA5761_CS_GPIO 93
  70 +#define N8X0_CBUS_DAT_GPIO 65
  71 +#define N8X0_CBUS_CLK_GPIO 66
  72 +#define N8X0_WLAN_IRQ_GPIO 87
  73 +#define N8X0_BT_RESET_GPIO 92
  74 +#define N8X0_TEA5761_CS_GPIO 93
69 75 #define N800_UNKNOWN_GPIO 94
  76 +#define N810_TSC_RESET_GPIO 94
70 77 #define N800_CAM_ACT_GPIO 95
71   -#define N800_MMC_CS_GPIO 96
72   -#define N800_WLAN_PWR_GPIO 97
  78 +#define N810_GPS_WAKEUP_GPIO 95
  79 +#define N8X0_MMC_CS_GPIO 96
  80 +#define N8X0_WLAN_PWR_GPIO 97
73 81 #define N8X0_BT_HOST_WKUP_GPIO 98
74 82 #define N800_UNKNOWN_GPIO3 101 /* out */
75 83 #define N810_KB_LOCK_GPIO 102
76 84 #define N800_TSC_TS_GPIO 103
77   -#define N810_TSC2005_GPIO 106
78   -#define N800_HEADPHONE_GPIO 107
  85 +#define N810_TSC_TS_GPIO 106
  86 +#define N8X0_HEADPHONE_GPIO 107
79 87 #define N8X0_RETU_GPIO 108
80 88 #define N800_TSC_KP_IRQ_GPIO 109
81 89 #define N810_KEYBOARD_GPIO 109
... ... @@ -83,7 +91,8 @@ struct n800_s {
83 91 #define N810_SLIDE_GPIO 110
84 92 #define N8X0_TAHVO_GPIO 111
85 93 #define N800_UNKNOWN_GPIO4 112 /* out */
86   -#define N810_TSC_RESET_GPIO 118
  94 +#define N810_SLEEPX_LED_GPIO 112
  95 +#define N810_TSC_UNKNOWN_GPIO 118 /* out */
87 96 #define N800_TSC_RESET_GPIO 119 /* ? */
88 97 #define N8X0_TMP105_GPIO 125
89 98  
... ... @@ -108,10 +117,10 @@ static void n800_mmc_cs_cb(void *opaque, int line, int level)
108 117 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
109 118 }
110 119  
111   -static void n800_gpio_setup(struct n800_s *s)
  120 +static void n8x0_gpio_setup(struct n800_s *s)
112 121 {
113 122 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
114   - omap2_gpio_out_set(s->cpu->gpif, N800_MMC_CS_GPIO, mmc_cs[0]);
  123 + omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]);
115 124  
116 125 qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]);
117 126 }
... ... @@ -126,7 +135,7 @@ static void n8x0_nand_setup(struct n800_s *s)
126 135 N8X0_ONENAND_GPIO)[0]));
127 136 }
128 137  
129   -static void n800_i2c_setup(struct n800_s *s)
  138 +static void n8x0_i2c_setup(struct n800_s *s)
130 139 {
131 140 qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0];
132 141  
... ... @@ -144,6 +153,18 @@ static void n800_i2c_setup(struct n800_s *s)
144 153 }
145 154  
146 155 /* Touchscreen and keypad controller */
  156 +static struct mouse_transform_info_s n800_pointercal = {
  157 + .x = 800,
  158 + .y = 480,
  159 + .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
  160 +};
  161 +
  162 +static struct mouse_transform_info_s n810_pointercal = {
  163 + .x = 800,
  164 + .y = 480,
  165 + .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
  166 +};
  167 +
147 168 #define RETU_KEYCODE 61 /* F3 */
148 169  
149 170 static void n800_key_event(void *opaque, int keycode)
... ... @@ -157,7 +178,7 @@ static void n800_key_event(void *opaque, int keycode)
157 178 return;
158 179 }
159 180  
160   - tsc210x_key_event(s->ts, code, !(keycode & 0x80));
  181 + tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
161 182 }
162 183  
163 184 static const int n800_keys[16] = {
... ... @@ -179,13 +200,7 @@ static const int n800_keys[16] = {
179 200 -1,
180 201 };
181 202  
182   -static struct mouse_transform_info_s n800_pointercal = {
183   - .x = 800,
184   - .y = 480,
185   - .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
186   -};
187   -
188   -static void n800_tsc_setup(struct n800_s *s)
  203 +static void n800_tsc_kbd_setup(struct n800_s *s)
189 204 {
190 205 int i;
191 206  
... ... @@ -195,7 +210,9 @@ static void n800_tsc_setup(struct n800_s *s)
195 210 qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];
196 211 qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];
197 212  
198   - s->ts = tsc2301_init(penirq, kbirq, dav, 0);
  213 + s->ts.chip = tsc2301_init(penirq, kbirq, dav, 0);
  214 + s->ts.opaque = s->ts.chip->opaque;
  215 + s->ts.txrx = tsc210x_txrx;
199 216  
200 217 for (i = 0; i < 0x80; i ++)
201 218 s->keymap[i] = -1;
... ... @@ -205,7 +222,17 @@ static void n800_tsc_setup(struct n800_s *s)
205 222  
206 223 qemu_add_kbd_event_handler(n800_key_event, s);
207 224  
208   - tsc210x_set_transform(s->ts, &n800_pointercal);
  225 + tsc210x_set_transform(s->ts.chip, &n800_pointercal);
  226 +}
  227 +
  228 +static void n810_tsc_setup(struct n800_s *s)
  229 +{
  230 + qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0];
  231 +
  232 + s->ts.opaque = tsc2005_init(pintdav);
  233 + s->ts.txrx = tsc2005_txrx;
  234 +
  235 + tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
209 236 }
210 237  
211 238 /* LCD MIPI DBI-C controller (URAL) */
... ... @@ -252,11 +279,15 @@ static void mipid_reset(struct mipid_s *s)
252 279 s->gamma = 0;
253 280 }
254 281  
255   -static uint32_t mipid_txrx(void *opaque, uint32_t cmd)
  282 +static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
256 283 {
257 284 struct mipid_s *s = (struct mipid_s *) opaque;
258 285 uint8_t ret;
259 286  
  287 + if (len > 9)
  288 + cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
  289 + __FUNCTION__, len);
  290 +
260 291 if (s->p >= sizeof(s->resp) / sizeof(*s->resp))
261 292 ret = 0;
262 293 else
... ... @@ -486,12 +517,12 @@ static void *mipid_init(void)
486 517 return s;
487 518 }
488 519  
489   -static void n800_spi_setup(struct n800_s *s)
  520 +static void n8x0_spi_setup(struct n800_s *s)
490 521 {
491   - void *tsc2301 = s->ts->opaque;
  522 + void *tsc = s->ts.opaque;
492 523 void *mipid = mipid_init();
493 524  
494   - omap_mcspi_attach(s->cpu->mcspi[0], tsc210x_txrx, tsc2301, 0);
  525 + omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
495 526 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
496 527 }
497 528  
... ... @@ -540,7 +571,7 @@ static void n800_dss_init(struct rfbi_chip_s *chip)
540 571 free(fb_blank);
541 572 }
542 573  
543   -static void n800_dss_setup(struct n800_s *s, DisplayState *ds)
  574 +static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds)
544 575 {
545 576 s->blizzard.opaque = s1d13745_init(0, ds);
546 577 s->blizzard.block = s1d13745_write_block;
... ... @@ -550,7 +581,7 @@ static void n800_dss_setup(struct n800_s *s, DisplayState *ds)
550 581 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
551 582 }
552 583  
553   -static void n800_cbus_setup(struct n800_s *s)
  584 +static void n8x0_cbus_setup(struct n800_s *s)
554 585 {
555 586 qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0];
556 587 qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
... ... @@ -566,17 +597,17 @@ static void n800_cbus_setup(struct n800_s *s)
566 597 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
567 598 }
568 599  
569   -static void n800_usb_power_cb(void *opaque, int line, int level)
  600 +static void n8x0_usb_power_cb(void *opaque, int line, int level)
570 601 {
571 602 struct n800_s *s = opaque;
572 603  
573 604 tusb6010_power(s->usb, level);
574 605 }
575 606  
576   -static void n800_usb_setup(struct n800_s *s)
  607 +static void n8x0_usb_setup(struct n800_s *s)
577 608 {
578 609 qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
579   - qemu_irq tusb_pwr = qemu_allocate_irqs(n800_usb_power_cb, s, 1)[0];
  610 + qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
580 611 struct tusb_s *tusb = tusb6010_init(tusb_irq);
581 612  
582 613 /* Using the NOR interface */
... ... @@ -586,7 +617,7 @@ static void n800_usb_setup(struct n800_s *s)
586 617 tusb6010_sync_io(tusb), 0, 0, tusb);
587 618  
588 619 s->usb = tusb;
589   - omap2_gpio_out_set(s->cpu->gpif, N800_TUSB_ENABLE_GPIO, tusb_pwr);
  620 + omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
590 621 }
591 622  
592 623 /* This task is normally performed by the bootloader. If we're loading
... ... @@ -603,7 +634,7 @@ static void n800_gpmc_init(struct n800_s *s)
603 634 }
604 635  
605 636 /* Setup sequence done by the bootloader */
606   -static void n800_boot_init(void *opaque)
  637 +static void n8x0_boot_init(void *opaque)
607 638 {
608 639 struct n800_s *s = (struct n800_s *) opaque;
609 640 uint32_t buf;
... ... @@ -667,11 +698,79 @@ static void n800_boot_init(void *opaque)
667 698 #define OMAP_TAG_CBUS 0x4e03
668 699 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
669 700  
670   -static int n800_atag_setup(struct arm_boot_info *info, void *p)
  701 +static struct omap_gpiosw_info_s {
  702 + const char *name;
  703 + int line;
  704 + int type;
  705 +} n800_gpiosw_info[] = {
  706 + {
  707 + "bat_cover", N800_BAT_COVER_GPIO,
  708 + OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
  709 + }, {
  710 + "cam_act", N800_CAM_ACT_GPIO,
  711 + OMAP_GPIOSW_TYPE_ACTIVITY,
  712 + }, {
  713 + "cam_turn", N800_CAM_TURN_GPIO,
  714 + OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
  715 + }, {
  716 + "headphone", N8X0_HEADPHONE_GPIO,
  717 + OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
  718 + },
  719 + { 0 }
  720 +}, n810_gpiosw_info[] = {
  721 + {
  722 + "gps_reset", N810_GPS_RESET_GPIO,
  723 + OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
  724 + }, {
  725 + "gps_wakeup", N810_GPS_WAKEUP_GPIO,
  726 + OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
  727 + }, {
  728 + "headphone", N8X0_HEADPHONE_GPIO,
  729 + OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
  730 + }, {
  731 + "kb_lock", N810_KB_LOCK_GPIO,
  732 + OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
  733 + }, {
  734 + "sleepx_led", N810_SLEEPX_LED_GPIO,
  735 + OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
  736 + }, {
  737 + "slide", N810_SLIDE_GPIO,
  738 + OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
  739 + },
  740 + { 0 }
  741 +};
  742 +
  743 +static struct omap_partition_info_s {
  744 + uint32_t offset;
  745 + uint32_t size;
  746 + int mask;
  747 + const char *name;
  748 +} n800_part_info[] = {
  749 + { 0x00000000, 0x00020000, 0x3, "bootloader" },
  750 + { 0x00020000, 0x00060000, 0x0, "config" },
  751 + { 0x00080000, 0x00200000, 0x0, "kernel" },
  752 + { 0x00280000, 0x00200000, 0x3, "initfs" },
  753 + { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
  754 +
  755 + { 0, 0, 0, 0 }
  756 +}, n810_part_info[] = {
  757 + { 0x00000000, 0x00020000, 0x3, "bootloader" },
  758 + { 0x00020000, 0x00060000, 0x0, "config" },
  759 + { 0x00080000, 0x00220000, 0x0, "kernel" },
  760 + { 0x002a0000, 0x00400000, 0x0, "initfs" },
  761 + { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
  762 +
  763 + { 0, 0, 0, 0 }
  764 +};
  765 +
  766 +static int n8x0_atag_setup(void *p, int model)
671 767 {
672 768 uint8_t *b;
673 769 uint16_t *w;
674 770 uint32_t *l;
  771 + struct omap_gpiosw_info_s *gpiosw;
  772 + struct omap_partition_info_s *partition;
  773 + const char *tag;
675 774  
676 775 w = p;
677 776  
... ... @@ -680,10 +779,21 @@ static int n800_atag_setup(struct arm_boot_info *info, void *p)
680 779 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
681 780 w ++;
682 781  
683   - stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
  782 +#if 0
  783 + stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
684 784 stw_raw(w ++, 4); /* u16 len */
685   - stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
686   - stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
  785 + stw_raw(w ++, XLDR_LL_UART); /* u8 console_uart */
  786 + stw_raw(w ++, 115200); /* u32 console_speed */
  787 +#endif
  788 +
  789 + stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
  790 + stw_raw(w ++, 36); /* u16 len */
  791 + strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
  792 + w += 8;
  793 + strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
  794 + w += 8;
  795 + stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
  796 + stw_raw(w ++, 24); /* u8 data_lines */
687 797  
688 798 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
689 799 stw_raw(w ++, 8); /* u16 len */
... ... @@ -692,49 +802,30 @@ static int n800_atag_setup(struct arm_boot_info *info, void *p)
692 802 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
693 803 w ++;
694 804  
695   - stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
696   - stw_raw(w ++, 20); /* u16 len */
697   - strcpy((void *) w, "bat_cover"); /* char name[12] */
698   - w += 6;
699   - stw_raw(w ++, N800_BAT_COVER_GPIO); /* u16 gpio */
700   - stw_raw(w ++, 0x01);
701   - stw_raw(w ++, 0);
702   - stw_raw(w ++, 0);
703   -
704   - stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
705   - stw_raw(w ++, 20); /* u16 len */
706   - strcpy((void *) w, "cam_act"); /* char name[12] */
707   - w += 6;
708   - stw_raw(w ++, N800_CAM_ACT_GPIO); /* u16 gpio */
709   - stw_raw(w ++, 0x20);
710   - stw_raw(w ++, 0);
711   - stw_raw(w ++, 0);
712   -
713   - stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
714   - stw_raw(w ++, 20); /* u16 len */
715   - strcpy((void *) w, "cam_turn"); /* char name[12] */
716   - w += 6;
717   - stw_raw(w ++, N800_CAM_TURN_GPIO); /* u16 gpio */
718   - stw_raw(w ++, 0x21);
719   - stw_raw(w ++, 0);
720   - stw_raw(w ++, 0);
721   -
722   - stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
723   - stw_raw(w ++, 20); /* u16 len */
724   - strcpy((void *) w, "headphone"); /* char name[12] */
725   - w += 6;
726   - stw_raw(w ++, N800_HEADPHONE_GPIO); /* u16 gpio */
727   - stw_raw(w ++, 0x11);
728   - stw_raw(w ++, 0);
729   - stw_raw(w ++, 0);
  805 + stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
  806 + stw_raw(w ++, 4); /* u16 len */
  807 + stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
  808 + stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
  809 +
  810 + gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
  811 + for (; gpiosw->name; gpiosw ++) {
  812 + stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
  813 + stw_raw(w ++, 20); /* u16 len */
  814 + strcpy((void *) w, gpiosw->name); /* char name[12] */
  815 + w += 6;
  816 + stw_raw(w ++, gpiosw->line); /* u16 gpio */
  817 + stw_raw(w ++, gpiosw->type);
  818 + stw_raw(w ++, 0);
  819 + stw_raw(w ++, 0);
  820 + }
730 821  
731 822 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
732 823 stw_raw(w ++, 12); /* u16 len */
733 824 b = (void *) w;
734 825 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
735   - stb_raw(b ++, N800_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
  826 + stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
736 827 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
737   - stb_raw(b ++, N800_BT_RESET_GPIO); /* u8 reset_gpio */
  828 + stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
738 829 stb_raw(b ++, 1); /* u8 bt_uart */
739 830 memset(b, 0, 6); /* u8 bd_addr[6] */
740 831 b += 6;
... ... @@ -744,70 +835,48 @@ static int n800_atag_setup(struct arm_boot_info *info, void *p)
744 835 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
745 836 stw_raw(w ++, 8); /* u16 len */
746 837 stw_raw(w ++, 0x25); /* u8 chip_type */
747   - stw_raw(w ++, N800_WLAN_PWR_GPIO); /* s16 power_gpio */
748   - stw_raw(w ++, N800_WLAN_IRQ_GPIO); /* s16 irq_gpio */
  838 + stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
  839 + stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
749 840 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
750 841  
751 842 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
752 843 stw_raw(w ++, 16); /* u16 len */
753   - stw_raw(w ++, 0xf); /* unsigned flags */
754   - stw_raw(w ++, -1); /* s16 power_pin */
755   - stw_raw(w ++, -1); /* s16 switch_pin */
756   - stw_raw(w ++, -1); /* s16 wp_pin */
757   - stw_raw(w ++, 0); /* unsigned flags */
758   - stw_raw(w ++, 0); /* s16 power_pin */
759   - stw_raw(w ++, 0); /* s16 switch_pin */
760   - stw_raw(w ++, 0); /* s16 wp_pin */
  844 + if (model == 810) {
  845 + stw_raw(w ++, 0x23f); /* unsigned flags */
  846 + stw_raw(w ++, -1); /* s16 power_pin */
  847 + stw_raw(w ++, -1); /* s16 switch_pin */
  848 + stw_raw(w ++, -1); /* s16 wp_pin */
  849 + stw_raw(w ++, 0x240); /* unsigned flags */
  850 + stw_raw(w ++, 0xc000); /* s16 power_pin */
  851 + stw_raw(w ++, 0x0248); /* s16 switch_pin */
  852 + stw_raw(w ++, 0xc000); /* s16 wp_pin */
  853 + } else {
  854 + stw_raw(w ++, 0xf); /* unsigned flags */
  855 + stw_raw(w ++, -1); /* s16 power_pin */
  856 + stw_raw(w ++, -1); /* s16 switch_pin */
  857 + stw_raw(w ++, -1); /* s16 wp_pin */
  858 + stw_raw(w ++, 0); /* unsigned flags */
  859 + stw_raw(w ++, 0); /* s16 power_pin */
  860 + stw_raw(w ++, 0); /* s16 switch_pin */
  861 + stw_raw(w ++, 0); /* s16 wp_pin */
  862 + }
761 863  
762 864 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
763 865 stw_raw(w ++, 4); /* u16 len */
764   - stw_raw(w ++, N800_TEA5761_CS_GPIO); /* u16 enable_gpio */
  866 + stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
765 867 w ++;
766 868  
767   - stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
768   - stw_raw(w ++, 28); /* u16 len */
769   - strcpy((void *) w, "bootloader"); /* char name[16] */
770   - l = (void *) (w + 8);
771   - stl_raw(l ++, 0x00020000); /* unsigned int size */
772   - stl_raw(l ++, 0x00000000); /* unsigned int offset */
773   - stl_raw(l ++, 0x3); /* unsigned int mask_flags */
774   - w = (void *) l;
775   -
776   - stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
777   - stw_raw(w ++, 28); /* u16 len */
778   - strcpy((void *) w, "config"); /* char name[16] */
779   - l = (void *) (w + 8);
780   - stl_raw(l ++, 0x00060000); /* unsigned int size */
781   - stl_raw(l ++, 0x00020000); /* unsigned int offset */
782   - stl_raw(l ++, 0x0); /* unsigned int mask_flags */
783   - w = (void *) l;
784   -
785   - stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
786   - stw_raw(w ++, 28); /* u16 len */
787   - strcpy((void *) w, "kernel"); /* char name[16] */
788   - l = (void *) (w + 8);
789   - stl_raw(l ++, 0x00200000); /* unsigned int size */
790   - stl_raw(l ++, 0x00080000); /* unsigned int offset */
791   - stl_raw(l ++, 0x0); /* unsigned int mask_flags */
792   - w = (void *) l;
793   -
794   - stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
795   - stw_raw(w ++, 28); /* u16 len */
796   - strcpy((void *) w, "initfs"); /* char name[16] */
797   - l = (void *) (w + 8);
798   - stl_raw(l ++, 0x00200000); /* unsigned int size */
799   - stl_raw(l ++, 0x00280000); /* unsigned int offset */
800   - stl_raw(l ++, 0x3); /* unsigned int mask_flags */
801   - w = (void *) l;
802   -
803   - stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
804   - stw_raw(w ++, 28); /* u16 len */
805   - strcpy((void *) w, "rootfs"); /* char name[16] */
806   - l = (void *) (w + 8);
807   - stl_raw(l ++, 0x0fb80000); /* unsigned int size */
808   - stl_raw(l ++, 0x00480000); /* unsigned int offset */
809   - stl_raw(l ++, 0x3); /* unsigned int mask_flags */
810   - w = (void *) l;
  869 + partition = (model == 810) ? n810_part_info : n800_part_info;
  870 + for (; partition->name; partition ++) {
  871 + stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
  872 + stw_raw(w ++, 28); /* u16 len */
  873 + strcpy((void *) w, partition->name); /* char name[16] */
  874 + l = (void *) (w + 8);
  875 + stl_raw(l ++, partition->size); /* unsigned int size */
  876 + stl_raw(l ++, partition->offset); /* unsigned int offset */
  877 + stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
  878 + w = (void *) l;
  879 + }
811 880  
812 881 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
813 882 stw_raw(w ++, 12); /* u16 len */
... ... @@ -827,77 +896,49 @@ static int n800_atag_setup(struct arm_boot_info *info, void *p)
827 896 #endif
828 897 w += 6;
829 898  
830   -#if 0 /* N810 */
831   - stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
832   - stw_raw(w ++, 24); /* u16 len */
833   - strcpy((void *) w, "product"); /* char component[12] */
834   - w += 6;
835   - strcpy((void *) w, "RX-44"); /* char version[12] */
836   - w += 6;
837   -
838   - stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
839   - stw_raw(w ++, 24); /* u16 len */
840   - strcpy((void *) w, "hw-build"); /* char component[12] */
841   - w += 6;
842   - strcpy((void *) w, "QEMU"); /* char version[12] */
843   - w += 6;
844   -
845   - stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
846   - stw_raw(w ++, 24); /* u16 len */
847   - strcpy((void *) w, "nolo"); /* char component[12] */
848   - w += 6;
849   - strcpy((void *) w, "1.1.10-qemu"); /* char version[12] */
850   - w += 6;
851   -#else
  899 + tag = (model == 810) ? "RX-44" : "RX-34";
852 900 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
853 901 stw_raw(w ++, 24); /* u16 len */
854 902 strcpy((void *) w, "product"); /* char component[12] */
855 903 w += 6;
856   - strcpy((void *) w, "RX-34"); /* char version[12] */
  904 + strcpy((void *) w, tag); /* char version[12] */
857 905 w += 6;
858 906  
859 907 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
860 908 stw_raw(w ++, 24); /* u16 len */
861 909 strcpy((void *) w, "hw-build"); /* char component[12] */
862 910 w += 6;
863   - strcpy((void *) w, "QEMU"); /* char version[12] */
  911 + strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
864 912 w += 6;
865 913  
  914 + tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
866 915 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
867 916 stw_raw(w ++, 24); /* u16 len */
868 917 strcpy((void *) w, "nolo"); /* char component[12] */
869 918 w += 6;
870   - strcpy((void *) w, "1.1.6-qemu"); /* char version[12] */
  919 + strcpy((void *) w, tag); /* char version[12] */
871 920 w += 6;
872   -#endif
873   -
874   - stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
875   - stw_raw(w ++, 36); /* u16 len */
876   - strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
877   - w += 8;
878   - strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
879   - w += 8;
880   - stw_raw(w ++, 5); /* TODO s16 nreset_gpio */
881   - stw_raw(w ++, 16); /* u8 data_lines */
882 921  
883 922 return (void *) w - p;
884 923 }
885 924  
886   -static struct arm_boot_info n800_binfo = {
887   - .loader_start = OMAP2_Q2_BASE,
888   - /* Actually two chips of 0x4000000 bytes each */
889   - .ram_size = 0x08000000,
890   - .board_id = 0x4f7,
891   - .atag_board = n800_atag_setup,
892   -};
  925 +static int n800_atag_setup(struct arm_boot_info *info, void *p)
  926 +{
  927 + return n8x0_atag_setup(p, 800);
  928 +}
893 929  
894   -static void n800_init(ram_addr_t ram_size, int vga_ram_size,
895   - const char *boot_device, DisplayState *ds,
896   - const char *kernel_filename, const char *kernel_cmdline,
897   - const char *initrd_filename, const char *cpu_model)
  930 +static int n810_atag_setup(struct arm_boot_info *info, void *p)
  931 +{
  932 + return n8x0_atag_setup(p, 810);
  933 +}
  934 +
  935 +static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
  936 + DisplayState *ds, const char *kernel_filename,
  937 + const char *kernel_cmdline, const char *initrd_filename,
  938 + const char *cpu_model, struct arm_boot_info *binfo, int model)
898 939 {
899 940 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
900   - int sdram_size = n800_binfo.ram_size;
  941 + int sdram_size = binfo->ram_size;
901 942 int onenandram_size = 0x00010000;
902 943  
903 944 if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
... ... @@ -908,15 +949,18 @@ static void n800_init(ram_addr_t ram_size, int vga_ram_size,
908 949  
909 950 s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model);
910 951  
911   - n800_gpio_setup(s);
  952 + n8x0_gpio_setup(s);
912 953 n8x0_nand_setup(s);
913   - n800_i2c_setup(s);
914   - n800_tsc_setup(s);
915   - n800_spi_setup(s);
916   - n800_dss_setup(s, ds);
917   - n800_cbus_setup(s);
  954 + n8x0_i2c_setup(s);
  955 + if (model == 800)
  956 + n800_tsc_kbd_setup(s);
  957 + else if (model == 810)
  958 + n810_tsc_setup(s);
  959 + n8x0_spi_setup(s);
  960 + n8x0_dss_setup(s, ds);
  961 + n8x0_cbus_setup(s);
918 962 if (usb_enabled)
919   - n800_usb_setup(s);
  963 + n8x0_usb_setup(s);
920 964  
921 965 /* Setup initial (reset) machine state */
922 966  
... ... @@ -925,21 +969,66 @@ static void n800_init(ram_addr_t ram_size, int vga_ram_size,
925 969  
926 970 if (kernel_filename) {
927 971 /* Or at the linux loader. */
928   - n800_binfo.kernel_filename = kernel_filename;
929   - n800_binfo.kernel_cmdline = kernel_cmdline;
930   - n800_binfo.initrd_filename = initrd_filename;
931   - arm_load_kernel(s->cpu->env, &n800_binfo);
  972 + binfo->kernel_filename = kernel_filename;
  973 + binfo->kernel_cmdline = kernel_cmdline;
  974 + binfo->initrd_filename = initrd_filename;
  975 + arm_load_kernel(s->cpu->env, binfo);
932 976  
933   - qemu_register_reset(n800_boot_init, s);
934   - n800_boot_init(s);
  977 + qemu_register_reset(n8x0_boot_init, s);
  978 + n8x0_boot_init(s);
935 979 }
936 980  
937 981 dpy_resize(ds, 800, 480);
938 982 }
939 983  
  984 +static struct arm_boot_info n800_binfo = {
  985 + .loader_start = OMAP2_Q2_BASE,
  986 + /* Actually two chips of 0x4000000 bytes each */
  987 + .ram_size = 0x08000000,
  988 + .board_id = 0x4f7,
  989 + .atag_board = n800_atag_setup,
  990 +};
  991 +
  992 +static struct arm_boot_info n810_binfo = {
  993 + .loader_start = OMAP2_Q2_BASE,
  994 + /* Actually two chips of 0x4000000 bytes each */
  995 + .ram_size = 0x08000000,
  996 + /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
  997 + * used by some older versions of the bootloader and 5555 is used
  998 + * instead (including versions that shipped with many devices). */
  999 + .board_id = 0x60c,
  1000 + .atag_board = n810_atag_setup,
  1001 +};
  1002 +
  1003 +static void n800_init(ram_addr_t ram_size, int vga_ram_size,
  1004 + const char *boot_device, DisplayState *ds,
  1005 + const char *kernel_filename, const char *kernel_cmdline,
  1006 + const char *initrd_filename, const char *cpu_model)
  1007 +{
  1008 + return n8x0_init(ram_size, boot_device, ds,
  1009 + kernel_filename, kernel_cmdline, initrd_filename,
  1010 + cpu_model, &n800_binfo, 800);
  1011 +}
  1012 +
  1013 +static void n810_init(ram_addr_t ram_size, int vga_ram_size,
  1014 + const char *boot_device, DisplayState *ds,
  1015 + const char *kernel_filename, const char *kernel_cmdline,
  1016 + const char *initrd_filename, const char *cpu_model)
  1017 +{
  1018 + return n8x0_init(ram_size, boot_device, ds,
  1019 + kernel_filename, kernel_cmdline, initrd_filename,
  1020 + cpu_model, &n810_binfo, 810);
  1021 +}
  1022 +
940 1023 QEMUMachine n800_machine = {
941 1024 "n800",
942   - "Nokia N800 aka. RX-34 tablet (OMAP2420)",
  1025 + "Nokia N800 tablet aka. RX-34 (OMAP2420)",
943 1026 n800_init,
944 1027 (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED,
945 1028 };
  1029 +
  1030 +QEMUMachine n810_machine = {
  1031 + "n810",
  1032 + "Nokia N810 tablet aka. RX-44 (OMAP2420)",
  1033 + n810_init,
  1034 +};
... ...
hw/omap.h
  View file @e927bb0
... ... @@ -695,7 +695,7 @@ struct omap_mcspi_s;
695 695 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
696 696 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
697 697 void omap_mcspi_attach(struct omap_mcspi_s *s,
698   - uint32_t (*txrx)(void *opaque, uint32_t), void *opaque,
  698 + uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
699 699 int chipselect);
700 700  
701 701 struct omap_rtc_s;
... ... @@ -1012,6 +1012,15 @@ void omap_mpu_wakeup(void *opaque, int irq, int req);
1012 1012 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1013 1013 #define OMAP_TAG_VERSION_STR 0x4f82
1014 1014  
  1015 +enum {
  1016 + OMAP_GPIOSW_TYPE_COVER = 0 << 4,
  1017 + OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
  1018 + OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
  1019 +};
  1020 +
  1021 +#define OMAP_GPIOSW_INVERTED 0x0001
  1022 +#define OMAP_GPIOSW_OUTPUT 0x0002
  1023 +
1015 1024 # define TCMI_VERBOSE 1
1016 1025 //# define MEM_VERBOSE 1
1017 1026  
... ...
hw/omap2.c
  View file @e927bb0
... ... @@ -1109,7 +1109,7 @@ struct omap_mcspi_s {
1109 1109 struct omap_mcspi_ch_s {
1110 1110 qemu_irq txdrq;
1111 1111 qemu_irq rxdrq;
1112   - uint32_t (*txrx)(void *opaque, uint32_t);
  1112 + uint32_t (*txrx)(void *opaque, uint32_t, int);
1113 1113 void *opaque;
1114 1114  
1115 1115 uint32_t tx;
... ... @@ -1157,7 +1157,8 @@ static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
1157 1157 if (!(s->control & 1) || /* SINGLE */
1158 1158 (ch->config & (1 << 20))) { /* FORCE */
1159 1159 if (ch->txrx)
1160   - ch->rx = ch->txrx(ch->opaque, ch->tx);
  1160 + ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
  1161 + 1 + (0x1f & (ch->config >> 7)));
1161 1162 }
1162 1163  
1163 1164 ch->tx = 0;
... ... @@ -1408,7 +1409,7 @@ struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
1408 1409 }
1409 1410  
1410 1411 void omap_mcspi_attach(struct omap_mcspi_s *s,
1411   - uint32_t (*txrx)(void *opaque, uint32_t), void *opaque,
  1412 + uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
1412 1413 int chipselect)
1413 1414 {
1414 1415 if (chipselect < 0 || chipselect >= s->chnum)
... ... @@ -1476,7 +1477,8 @@ static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
1476 1477  
1477 1478 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
1478 1479 case 0x28: /* STI_RX_DR / XTI_RXDATA */
1479   - break;
  1480 + /* TODO */
  1481 + return 0;
1480 1482  
1481 1483 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
1482 1484 return s->clkcontrol;
... ... @@ -1527,6 +1529,9 @@ static void omap_sti_write(void *opaque, target_phys_addr_t addr,
1527 1529  
1528 1530 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
1529 1531 case 0x28: /* STI_RX_DR / XTI_RXDATA */
  1532 + /* TODO */
  1533 + return;
  1534 +
1530 1535 default:
1531 1536 OMAP_BAD_REG(addr);
1532 1537 return;
... ...
hw/tsc210x.c
  View file @e927bb0
... ... @@ -939,11 +939,15 @@ static void tsc210x_write(struct tsc210x_state_s *s, uint16_t value)
939 939 }
940 940 }
941 941  
942   -uint32_t tsc210x_txrx(void *opaque, uint32_t value)
  942 +uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
943 943 {
944 944 struct tsc210x_state_s *s = opaque;
945 945 uint32_t ret = 0;
946 946  
  947 + if (len != 16)
  948 + cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
  949 + __FUNCTION__, len);
  950 +
947 951 /* TODO: sequential reads etc - how do we make sure the host doesn't
948 952 * unintentionally read out a conversion result from a register while
949 953 * transmitting the command word of the next command? */
... ... @@ -1124,12 +1128,12 @@ struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio)
1124 1128  
1125 1129 s->tr[0] = 0;
1126 1130 s->tr[1] = 1;
1127   - s->tr[2] = 0;
1128   - s->tr[3] = 1;
  1131 + s->tr[2] = 1;
  1132 + s->tr[3] = 0;
1129 1133 s->tr[4] = 1;
1130 1134 s->tr[5] = 0;
1131   - s->tr[6] = 0;
1132   - s->tr[7] = 1;
  1135 + s->tr[6] = 1;
  1136 + s->tr[7] = 0;
1133 1137  
1134 1138 s->chip.opaque = s;
1135 1139 s->chip.send = (void *) tsc210x_write;
... ... @@ -1178,12 +1182,12 @@ struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
1178 1182  
1179 1183 s->tr[0] = 0;
1180 1184 s->tr[1] = 1;
1181   - s->tr[2] = 0;
1182   - s->tr[3] = 1;
  1185 + s->tr[2] = 1;
  1186 + s->tr[3] = 0;
1183 1187 s->tr[4] = 1;
1184 1188 s->tr[5] = 0;
1185   - s->tr[6] = 0;
1186   - s->tr[7] = 1;
  1189 + s->tr[6] = 1;
  1190 + s->tr[7] = 0;
1187 1191  
1188 1192 s->chip.opaque = s;
1189 1193 s->chip.send = (void *) tsc210x_write;
... ...