gwj / at91sam9263 · Commits

Commit e8eaa2c0125de7a1169601f99a225593d742cb66

Authored by Blue Swirl
1 parent 99e300ef

Clean up GEN_HANDLER2 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 1 changed file with 110 additions and 37 deletions
target-ppc/translate.c
  View file @e8eaa2c
... ... @@ -319,7 +319,6 @@ GEN_OPCODE(name, opc1, opc2, opc3, inval, type);
319 319 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
320 320 static void gen_##name (DisasContext *ctx); \
321 321 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
322   -static void gen_##name (DisasContext *ctx)
323 322  
324 323 typedef struct opcode_t {
325 324 unsigned char opc1, opc2, opc3;
... ... @@ -936,7 +935,9 @@ static void gen_addic(DisasContext *ctx)
936 935 {
937 936 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
938 937 }
939   -GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
  938 +GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER);
  939 +
  940 +static void gen_addic_(DisasContext *ctx)
940 941 {
941 942 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
942 943 }
... ... @@ -1378,13 +1379,17 @@ GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1378 1379 /* andc & andc. */
1379 1380 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1380 1381 /* andi. */
1381   -GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
  1382 +GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER);
  1383 +
  1384 +static void gen_andi_(DisasContext *ctx)
1382 1385 {
1383 1386 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1384 1387 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1385 1388 }
1386 1389 /* andis. */
1387   -GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
  1390 +GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER);
  1391 +
  1392 +static void gen_andis_(DisasContext *ctx)
1388 1393 {
1389 1394 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1390 1395 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
... ... @@ -1713,32 +1718,44 @@ static void gen_rlwnm(DisasContext *ctx)
1713 1718  
1714 1719 #if defined(TARGET_PPC64)
1715 1720 #define GEN_PPC64_R2(name, opc1, opc2) \
1716   -GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
  1721 +GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B);\
  1722 + \
  1723 +static void glue(gen_, name##0)(DisasContext *ctx) \
1717 1724 { \
1718 1725 gen_##name(ctx, 0); \
1719 1726 } \
1720 1727 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1721   - PPC_64B) \
  1728 + PPC_64B); \
  1729 + \
  1730 +static void glue(gen_, name##1)(DisasContext *ctx) \
1722 1731 { \
1723 1732 gen_##name(ctx, 1); \
1724 1733 }
1725 1734 #define GEN_PPC64_R4(name, opc1, opc2) \
1726   -GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
  1735 +GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B);\
  1736 + \
  1737 +static void glue(gen_, name##0)(DisasContext *ctx) \
1727 1738 { \
1728 1739 gen_##name(ctx, 0, 0); \
1729 1740 } \
1730 1741 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1731   - PPC_64B) \
  1742 + PPC_64B); \
  1743 + \
  1744 +static void glue(gen_, name##1)(DisasContext *ctx) \
1732 1745 { \
1733 1746 gen_##name(ctx, 0, 1); \
1734 1747 } \
1735 1748 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1736   - PPC_64B) \
  1749 + PPC_64B); \
  1750 + \
  1751 +static void glue(gen_, name##2)(DisasContext *ctx) \
1737 1752 { \
1738 1753 gen_##name(ctx, 1, 0); \
1739 1754 } \
1740 1755 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1741 1756 PPC_64B) \
  1757 + \
  1758 +static void glue(gen_, name##3)(DisasContext *ctx) \
1742 1759 { \
1743 1760 gen_##name(ctx, 1, 1); \
1744 1761 }
... ... @@ -2012,11 +2029,15 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
2012 2029 if (unlikely(Rc(ctx->opcode) != 0))
2013 2030 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2014 2031 }
2015   -GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
  2032 +GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B);
  2033 +
  2034 +static void gen_sradi0(DisasContext *ctx)
2016 2035 {
2017 2036 gen_sradi(ctx, 0);
2018 2037 }
2019   -GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
  2038 +GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B);
  2039 +
  2040 +static void gen_sradi1(DisasContext *ctx)
2020 2041 {
2021 2042 gen_sradi(ctx, 1);
2022 2043 }
... ... @@ -3173,7 +3194,9 @@ static void gen_lwarx(DisasContext *ctx)
3173 3194 }
3174 3195  
3175 3196 /* stwcx. */
3176   -GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
  3197 +GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES);
  3198 +
  3199 +static void gen_stwcx_(DisasContext *ctx)
3177 3200 {
3178 3201 int l1;
3179 3202 TCGv t0;
... ... @@ -3210,7 +3233,9 @@ static void gen_ldarx(DisasContext *ctx)
3210 3233 }
3211 3234  
3212 3235 /* stdcx. */
3213   -GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
  3236 +GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B);
  3237 +
  3238 +static void gen_stdcx_(DisasContext *ctx)
3214 3239 {
3215 3240 int l1;
3216 3241 TCGv t0;
... ... @@ -4189,7 +4214,9 @@ static void gen_dcbz(DisasContext *ctx)
4189 4214 tcg_temp_free(t0);
4190 4215 }
4191 4216  
4192   -GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
  4217 +GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT);
  4218 +
  4219 +static void gen_dcbz_970(DisasContext *ctx)
4193 4220 {
4194 4221 TCGv t0;
4195 4222 gen_set_access_type(ctx, ACCESS_CACHE);
... ... @@ -4349,7 +4376,9 @@ static void gen_mtsrin(DisasContext *ctx)
4349 4376 #if defined(TARGET_PPC64)
4350 4377 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4351 4378 /* mfsr */
4352   -GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
  4379 +GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B);
  4380 +
  4381 +static void gen_mfsr_64b(DisasContext *ctx)
4353 4382 {
4354 4383 #if defined(CONFIG_USER_ONLY)
4355 4384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
... ... @@ -4367,7 +4396,9 @@ GEN_HANDLER2(mfsr_64b, &quot;mfsr&quot;, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4367 4396  
4368 4397 /* mfsrin */
4369 4398 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4370   - PPC_SEGMENT_64B)
  4399 + PPC_SEGMENT_64B);
  4400 +
  4401 +static void gen_mfsrin_64b(DisasContext *ctx)
4371 4402 {
4372 4403 #if defined(CONFIG_USER_ONLY)
4373 4404 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
... ... @@ -4386,7 +4417,9 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001,
4386 4417 }
4387 4418  
4388 4419 /* mtsr */
4389   -GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
  4420 +GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B);
  4421 +
  4422 +static void gen_mtsr_64b(DisasContext *ctx)
4390 4423 {
4391 4424 #if defined(CONFIG_USER_ONLY)
4392 4425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
... ... @@ -4404,7 +4437,9 @@ GEN_HANDLER2(mtsr_64b, &quot;mtsr&quot;, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4404 4437  
4405 4438 /* mtsrin */
4406 4439 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4407   - PPC_SEGMENT_64B)
  4440 + PPC_SEGMENT_64B);
  4441 +
  4442 +static void gen_mtsrin_64b(DisasContext *ctx)
4408 4443 {
4409 4444 #if defined(CONFIG_USER_ONLY)
4410 4445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
... ... @@ -4423,7 +4458,9 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001,
4423 4458 }
4424 4459  
4425 4460 /* slbmte */
4426   -GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
  4461 +GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B);
  4462 +
  4463 +static void gen_slbmte(DisasContext *ctx)
4427 4464 {
4428 4465 #if defined(CONFIG_USER_ONLY)
4429 4466 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
... ... @@ -5326,7 +5363,9 @@ static void gen_mfrom(DisasContext *ctx)
5326 5363  
5327 5364 /* 602 - 603 - G2 TLB management */
5328 5365 /* tlbld */
5329   -GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
  5366 +GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB);
  5367 +
  5368 +static void gen_tlbld_6xx(DisasContext *ctx)
5330 5369 {
5331 5370 #if defined(CONFIG_USER_ONLY)
5332 5371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -5340,7 +5379,9 @@ GEN_HANDLER2(tlbld_6xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5340 5379 }
5341 5380  
5342 5381 /* tlbli */
5343   -GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
  5382 +GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB);
  5383 +
  5384 +static void gen_tlbli_6xx(DisasContext *ctx)
5344 5385 {
5345 5386 #if defined(CONFIG_USER_ONLY)
5346 5387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -5355,7 +5396,9 @@ GEN_HANDLER2(tlbli_6xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5355 5396  
5356 5397 /* 74xx TLB management */
5357 5398 /* tlbld */
5358   -GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
  5399 +GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB);
  5400 +
  5401 +static void gen_tlbld_74xx(DisasContext *ctx)
5359 5402 {
5360 5403 #if defined(CONFIG_USER_ONLY)
5361 5404 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -5369,7 +5412,9 @@ GEN_HANDLER2(tlbld_74xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5369 5412 }
5370 5413  
5371 5414 /* tlbli */
5372   -GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
  5415 +GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB);
  5416 +
  5417 +static void gen_tlbli_74xx(DisasContext *ctx)
5373 5418 {
5374 5419 #if defined(CONFIG_USER_ONLY)
5375 5420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6020,7 +6065,9 @@ static void gen_dcread(DisasContext *ctx)
6020 6065 }
6021 6066  
6022 6067 /* icbt */
6023   -GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
  6068 +GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT);
  6069 +
  6070 +static void gen_icbt_40x(DisasContext *ctx)
6024 6071 {
6025 6072 /* interpreted as no-op */
6026 6073 /* XXX: specification say this is treated as a load by the MMU
... ... @@ -6061,7 +6108,9 @@ static void gen_icread(DisasContext *ctx)
6061 6108 }
6062 6109  
6063 6110 /* rfci (mem_idx only) */
6064   -GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
  6111 +GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP);
  6112 +
  6113 +static void gen_rfci_40x(DisasContext *ctx)
6065 6114 {
6066 6115 #if defined(CONFIG_USER_ONLY)
6067 6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6132,7 +6181,9 @@ static void gen_rfmci(DisasContext *ctx)
6132 6181  
6133 6182 /* TLB management - PowerPC 405 implementation */
6134 6183 /* tlbre */
6135   -GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
  6184 +GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB);
  6185 +
  6186 +static void gen_tlbre_40x(DisasContext *ctx)
6136 6187 {
6137 6188 #if defined(CONFIG_USER_ONLY)
6138 6189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6156,7 +6207,9 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
6156 6207 }
6157 6208  
6158 6209 /* tlbsx - tlbsx. */
6159   -GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
  6210 +GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB);
  6211 +
  6212 +static void gen_tlbsx_40x(DisasContext *ctx)
6160 6213 {
6161 6214 #if defined(CONFIG_USER_ONLY)
6162 6215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6183,7 +6236,9 @@ GEN_HANDLER2(tlbsx_40x, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
6183 6236 }
6184 6237  
6185 6238 /* tlbwe */
6186   -GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
  6239 +GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB);
  6240 +
  6241 +static void gen_tlbwe_40x(DisasContext *ctx)
6187 6242 {
6188 6243 #if defined(CONFIG_USER_ONLY)
6189 6244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6208,7 +6263,9 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
6208 6263  
6209 6264 /* TLB management - PowerPC 440 implementation */
6210 6265 /* tlbre */
6211   -GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
  6266 +GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE);
  6267 +
  6268 +static void gen_tlbre_440(DisasContext *ctx)
6212 6269 {
6213 6270 #if defined(CONFIG_USER_ONLY)
6214 6271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6235,7 +6292,9 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
6235 6292 }
6236 6293  
6237 6294 /* tlbsx - tlbsx. */
6238   -GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
  6295 +GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE);
  6296 +
  6297 +static void gen_tlbsx_440(DisasContext *ctx)
6239 6298 {
6240 6299 #if defined(CONFIG_USER_ONLY)
6241 6300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6262,7 +6321,9 @@ GEN_HANDLER2(tlbsx_440, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
6262 6321 }
6263 6322  
6264 6323 /* tlbwe */
6265   -GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
  6324 +GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE);
  6325 +
  6326 +static void gen_tlbwe_440(DisasContext *ctx)
6266 6327 {
6267 6328 #if defined(CONFIG_USER_ONLY)
6268 6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
... ... @@ -6364,7 +6425,9 @@ static void gen_msync(DisasContext *ctx)
6364 6425 }
6365 6426  
6366 6427 /* icbt */
6367   -GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
  6428 +GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE);
  6429 +
  6430 +static void gen_icbt_440(DisasContext *ctx)
6368 6431 {
6369 6432 /* interpreted as no-op */
6370 6433 /* XXX: specification say this is treated as a load by the MMU
... ... @@ -6683,7 +6746,9 @@ GEN_VXFORM(vmaxfp, 5, 16);
6683 6746 GEN_VXFORM(vminfp, 5, 17);
6684 6747  
6685 6748 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6686   - GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
  6749 + GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC); \
  6750 + \
  6751 +static void glue(gen_, name)(DisasContext *ctx) \
6687 6752 { \
6688 6753 TCGv_ptr ra, rb, rd; \
6689 6754 if (unlikely(!ctx->altivec_enabled)) { \
... ... @@ -7452,19 +7517,27 @@ static always_inline void gen_evsel (DisasContext *ctx)
7452 7517 tcg_temp_free(t2);
7453 7518 #endif
7454 7519 }
7455   -GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
  7520 +GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE);
  7521 +
  7522 +static void gen_evsel0(DisasContext *ctx)
7456 7523 {
7457 7524 gen_evsel(ctx);
7458 7525 }
7459   -GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
  7526 +GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE);
  7527 +
  7528 +static void gen_evsel1(DisasContext *ctx)
7460 7529 {
7461 7530 gen_evsel(ctx);
7462 7531 }
7463   -GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
  7532 +GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE);
  7533 +
  7534 +static void gen_evsel2(DisasContext *ctx)
7464 7535 {
7465 7536 gen_evsel(ctx);
7466 7537 }
7467   -GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
  7538 +GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE);
  7539 +
  7540 +static void gen_evsel3(DisasContext *ctx)
7468 7541 {
7469 7542 gen_evsel(ctx);
7470 7543 }
... ...