Commit e748ba4f5352061474668a47341abe2a898e03ad
1 parent
b8ed223b
ARM half word load/store fix (Ulrich Hecht)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@438 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
1 changed file
with
3 additions
and
2 deletions
target-arm/translate.c
| @@ -546,8 +546,7 @@ static void disas_arm_insn(DisasContext *s) | @@ -546,8 +546,7 @@ static void disas_arm_insn(DisasContext *s) | ||
| 546 | rn = (insn >> 16) & 0xf; | 546 | rn = (insn >> 16) & 0xf; |
| 547 | rd = (insn >> 12) & 0xf; | 547 | rd = (insn >> 12) & 0xf; |
| 548 | gen_movl_T1_reg(s, rn); | 548 | gen_movl_T1_reg(s, rn); |
| 549 | - if (insn & (1 << 25)) | ||
| 550 | - gen_add_datah_offset(s, insn); | 549 | + gen_add_datah_offset(s, insn); |
| 551 | if (insn & (1 << 20)) { | 550 | if (insn & (1 << 20)) { |
| 552 | /* load */ | 551 | /* load */ |
| 553 | switch(sh) { | 552 | switch(sh) { |
| @@ -562,8 +561,10 @@ static void disas_arm_insn(DisasContext *s) | @@ -562,8 +561,10 @@ static void disas_arm_insn(DisasContext *s) | ||
| 562 | gen_op_ldsw_T0_T1(); | 561 | gen_op_ldsw_T0_T1(); |
| 563 | break; | 562 | break; |
| 564 | } | 563 | } |
| 564 | + gen_movl_reg_T0(s, rd); | ||
| 565 | } else { | 565 | } else { |
| 566 | /* store */ | 566 | /* store */ |
| 567 | + gen_movl_T0_reg(s, rd); | ||
| 567 | gen_op_stw_T0_T1(); | 568 | gen_op_stw_T0_T1(); |
| 568 | } | 569 | } |
| 569 | if (!(insn & (1 << 24))) { | 570 | if (!(insn & (1 << 24))) { |