gwj / at91sam9263 · Commits

Commit e6e514c529446824c638d47286338db8da7edf0e

Authored by aurel32
1 parent aa923101

bios: disable processor SSDT generation. Fixes high idle load on 

x86/x86-64.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4270 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 67 additions and 44 deletions
pc-bios/bios.bin
View file @e6e514c
No preview for this file type
pc-bios/bios.diff
  View file @e6e514c
1 Index: rombios.c 1 Index: rombios.c
2 =================================================================== 2 ===================================================================
3 RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v 3 RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
4 -retrieving revision 1.205  
5 -diff -u -d -p -r1.205 rombios.c  
6 ---- rombios.c 21 Mar 2008 19:06:31 -0000 1.205  
7 -+++ rombios.c 10 Apr 2008 09:47:48 -0000  
8 -@@ -4395,22 +4395,25 @@ BX_DEBUG_INT15("case default:\n"); 4 +retrieving revision 1.207
  5 +diff -u -d -p -r1.207 rombios.c
  6 +--- rombios.c 21 Apr 2008 14:22:01 -0000 1.207
  7 ++++ rombios.c 27 Apr 2008 23:40:19 -0000
  8 +@@ -4404,22 +4404,25 @@ BX_DEBUG_INT15("case default:\n");
9 #endif // BX_USE_PS2_MOUSE 9 #endif // BX_USE_PS2_MOUSE
10 -  
11 - 10 +
  11 +
12 -void set_e820_range(ES, DI, start, end, type) 12 -void set_e820_range(ES, DI, start, end, type)
13 +void set_e820_range(ES, DI, start, end, extra_start, extra_end, type) 13 +void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
14 Bit16u ES; 14 Bit16u ES;
@@ -24,7 +24,7 @@ diff -u -d -p -r1.205 rombios.c @@ -24,7 +24,7 @@ diff -u -d -p -r1.205 rombios.c
24 - write_word(ES, DI+4, 0x00); 24 - write_word(ES, DI+4, 0x00);
25 + write_word(ES, DI+4, extra_start); 25 + write_word(ES, DI+4, extra_start);
26 write_word(ES, DI+6, 0x00); 26 write_word(ES, DI+6, 0x00);
27 - 27 +
28 end -= start; 28 end -= start;
29 + extra_end -= extra_start; 29 + extra_end -= extra_start;
30 write_word(ES, DI+8, end); 30 write_word(ES, DI+8, end);
@@ -32,22 +32,22 @@ diff -u -d -p -r1.205 rombios.c @@ -32,22 +32,22 @@ diff -u -d -p -r1.205 rombios.c
32 - write_word(ES, DI+12, 0x0000); 32 - write_word(ES, DI+12, 0x0000);
33 + write_word(ES, DI+12, extra_end); 33 + write_word(ES, DI+12, extra_end);
34 write_word(ES, DI+14, 0x0000); 34 write_word(ES, DI+14, 0x0000);
35 - 35 +
36 write_word(ES, DI+16, type); 36 write_word(ES, DI+16, type);
37 -@@ -4423,7 +4426,9 @@ int15_function32(regs, ES, DS, FLAGS) 37 +@@ -4432,7 +4435,9 @@ int15_function32(regs, ES, DS, FLAGS)
38 Bit16u ES, DS, FLAGS; 38 Bit16u ES, DS, FLAGS;
39 { 39 {
40 Bit32u extended_memory_size=0; // 64bits long 40 Bit32u extended_memory_size=0; // 64bits long
41 + Bit32u extra_lowbits_memory_size=0; 41 + Bit32u extra_lowbits_memory_size=0;
42 Bit16u CX,DX; 42 Bit16u CX,DX;
43 + Bit8u extra_highbits_memory_size=0; 43 + Bit8u extra_highbits_memory_size=0;
44 - 44 +
45 BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax); 45 BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
46 -  
47 -@@ -4497,11 +4502,18 @@ ASM_END 46 +
  47 +@@ -4506,11 +4511,18 @@ ASM_END
48 extended_memory_size += (1L * 1024 * 1024); 48 extended_memory_size += (1L * 1024 * 1024);
49 } 49 }
50 - 50 +
51 + extra_lowbits_memory_size = inb_cmos(0x5c); 51 + extra_lowbits_memory_size = inb_cmos(0x5c);
52 + extra_lowbits_memory_size <<= 8; 52 + extra_lowbits_memory_size <<= 8;
53 + extra_lowbits_memory_size |= inb_cmos(0x5b); 53 + extra_lowbits_memory_size |= inb_cmos(0x5b);
@@ -64,7 +64,7 @@ diff -u -d -p -r1.205 rombios.c @@ -64,7 +64,7 @@ diff -u -d -p -r1.205 rombios.c
64 regs.u.r32.ebx = 1; 64 regs.u.r32.ebx = 1;
65 regs.u.r32.eax = 0x534D4150; 65 regs.u.r32.eax = 0x534D4150;
66 regs.u.r32.ecx = 0x14; 66 regs.u.r32.ecx = 0x14;
67 -@@ -4510,7 +4522,7 @@ ASM_END 67 +@@ -4519,7 +4531,7 @@ ASM_END
68 break; 68 break;
69 case 1: 69 case 1:
70 set_e820_range(ES, regs.u.r16.di, 70 set_e820_range(ES, regs.u.r16.di,
@@ -73,7 +73,7 @@ diff -u -d -p -r1.205 rombios.c @@ -73,7 +73,7 @@ diff -u -d -p -r1.205 rombios.c
73 regs.u.r32.ebx = 2; 73 regs.u.r32.ebx = 2;
74 regs.u.r32.eax = 0x534D4150; 74 regs.u.r32.eax = 0x534D4150;
75 regs.u.r32.ecx = 0x14; 75 regs.u.r32.ecx = 0x14;
76 -@@ -4519,7 +4531,7 @@ ASM_END 76 +@@ -4528,7 +4540,7 @@ ASM_END
77 break; 77 break;
78 case 2: 78 case 2:
79 set_e820_range(ES, regs.u.r16.di, 79 set_e820_range(ES, regs.u.r16.di,
@@ -82,16 +82,16 @@ diff -u -d -p -r1.205 rombios.c @@ -82,16 +82,16 @@ diff -u -d -p -r1.205 rombios.c
82 regs.u.r32.ebx = 3; 82 regs.u.r32.ebx = 3;
83 regs.u.r32.eax = 0x534D4150; 83 regs.u.r32.eax = 0x534D4150;
84 regs.u.r32.ecx = 0x14; 84 regs.u.r32.ecx = 0x14;
85 -@@ -4529,7 +4541,7 @@ ASM_END  
86 - case 3: 85 +@@ -4539,7 +4551,7 @@ ASM_END
  86 + #if BX_ROMBIOS32
87 set_e820_range(ES, regs.u.r16.di, 87 set_e820_range(ES, regs.u.r16.di,
88 0x00100000L, 88 0x00100000L,
89 - extended_memory_size - ACPI_DATA_SIZE, 1); 89 - extended_memory_size - ACPI_DATA_SIZE, 1);
90 + extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1); 90 + extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
91 regs.u.r32.ebx = 4; 91 regs.u.r32.ebx = 4;
92 - regs.u.r32.eax = 0x534D4150;  
93 - regs.u.r32.ecx = 0x14;  
94 -@@ -4539,7 +4551,7 @@ ASM_END 92 + #else
  93 + set_e820_range(ES, regs.u.r16.di,
  94 +@@ -4555,7 +4567,7 @@ ASM_END
95 case 4: 95 case 4:
96 set_e820_range(ES, regs.u.r16.di, 96 set_e820_range(ES, regs.u.r16.di,
97 extended_memory_size - ACPI_DATA_SIZE, 97 extended_memory_size - ACPI_DATA_SIZE,
@@ -100,7 +100,7 @@ diff -u -d -p -r1.205 rombios.c @@ -100,7 +100,7 @@ diff -u -d -p -r1.205 rombios.c
100 regs.u.r32.ebx = 5; 100 regs.u.r32.ebx = 5;
101 regs.u.r32.eax = 0x534D4150; 101 regs.u.r32.eax = 0x534D4150;
102 regs.u.r32.ecx = 0x14; 102 regs.u.r32.ecx = 0x14;
103 -@@ -4549,7 +4561,20 @@ ASM_END 103 +@@ -4565,7 +4577,20 @@ ASM_END
104 case 5: 104 case 5:
105 /* 256KB BIOS area at the end of 4 GB */ 105 /* 256KB BIOS area at the end of 4 GB */
106 set_e820_range(ES, regs.u.r16.di, 106 set_e820_range(ES, regs.u.r16.di,
@@ -128,7 +128,7 @@ RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v @@ -128,7 +128,7 @@ RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
128 retrieving revision 1.6 128 retrieving revision 1.6
129 diff -u -d -p -r1.6 rombios.h 129 diff -u -d -p -r1.6 rombios.h
130 --- rombios.h 26 Jan 2008 09:15:27 -0000 1.6 130 --- rombios.h 26 Jan 2008 09:15:27 -0000 1.6
131 -+++ rombios.h 10 Apr 2008 09:47:48 -0000 131 ++++ rombios.h 27 Apr 2008 23:40:19 -0000
132 @@ -19,7 +19,7 @@ 132 @@ -19,7 +19,7 @@
133 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 133 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
134 134
@@ -141,11 +141,11 @@ diff -u -d -p -r1.6 rombios.h @@ -141,11 +141,11 @@ diff -u -d -p -r1.6 rombios.h
141 Index: rombios32.c 141 Index: rombios32.c
142 =================================================================== 142 ===================================================================
143 RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v 143 RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
144 -retrieving revision 1.24  
145 -diff -u -d -p -r1.24 rombios32.c  
146 ---- rombios32.c 6 Mar 2008 20:18:20 -0000 1.24  
147 -+++ rombios32.c 10 Apr 2008 09:47:48 -0000  
148 -@@ -477,7 +477,12 @@ void smp_probe(void) 144 +retrieving revision 1.26
  145 +diff -u -d -p -r1.26 rombios32.c
  146 +--- rombios32.c 8 Apr 2008 16:41:18 -0000 1.26
  147 ++++ rombios32.c 27 Apr 2008 23:40:19 -0000
  148 +@@ -478,7 +478,12 @@ void smp_probe(void)
149 sipi_vector = AP_BOOT_ADDR >> 12; 149 sipi_vector = AP_BOOT_ADDR >> 12;
150 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector); 150 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
151 151
@@ -158,19 +158,42 @@ diff -u -d -p -r1.24 rombios32.c @@ -158,19 +158,42 @@ diff -u -d -p -r1.24 rombios32.c
158 158
159 smp_cpus = readw((void *)CPU_COUNT_ADDR); 159 smp_cpus = readw((void *)CPU_COUNT_ADDR);
160 } 160 }
161 -Index: rombios32start.S  
162 -===================================================================  
163 -RCS file: /cvsroot/bochs/bochs/bios/rombios32start.S,v  
164 -retrieving revision 1.4  
165 -diff -u -d -p -r1.4 rombios32start.S  
166 ---- rombios32start.S 26 Jan 2008 09:15:27 -0000 1.4  
167 -+++ rombios32start.S 10 Apr 2008 09:47:48 -0000  
168 -@@ -42,7 +42,7 @@ _start:  
169 - smp_ap_boot_code_start:  
170 - xor %ax, %ax  
171 - mov %ax, %ds  
172 -- incw CPU_COUNT_ADDR  
173 -+ lock incw CPU_COUNT_ADDR  
174 - 1:  
175 - hlt  
176 - jmp 1b 161 +@@ -1081,7 +1086,7 @@ struct rsdp_descriptor /* Root S
  162 + struct rsdt_descriptor_rev1
  163 + {
  164 + ACPI_TABLE_HEADER_DEF /* ACPI common table header */
  165 +- uint32_t table_offset_entry [3]; /* Array of pointers to other */
  166 ++ uint32_t table_offset_entry [2]; /* Array of pointers to other */
  167 + /* ACPI tables */
  168 + };
  169 +
  170 +@@ -1335,8 +1340,8 @@ void acpi_bios_init(void)
  171 + struct fadt_descriptor_rev1 *fadt;
  172 + struct facs_descriptor_rev1 *facs;
  173 + struct multiple_apic_table *madt;
  174 +- uint8_t *dsdt, *ssdt;
  175 +- uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
  176 ++ uint8_t *dsdt;
  177 ++ uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
  178 + uint32_t acpi_tables_size, madt_addr, madt_size;
  179 + int i;
  180 +
  181 +@@ -1370,10 +1375,6 @@ void acpi_bios_init(void)
  182 + dsdt = (void *)(addr);
  183 + addr += sizeof(AmlCode);
  184 +
  185 +- ssdt_addr = addr;
  186 +- ssdt = (void *)(addr);
  187 +- addr += acpi_build_processor_ssdt(ssdt);
  188 +-
  189 + addr = (addr + 7) & ~7;
  190 + madt_addr = addr;
  191 + madt_size = sizeof(*madt) +
  192 +@@ -1403,7 +1404,6 @@ void acpi_bios_init(void)
  193 + memset(rsdt, 0, sizeof(*rsdt));
  194 + rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
  195 + rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
  196 +- rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
  197 + acpi_build_table_header((struct acpi_table_header *)rsdt,
  198 + "RSDT", sizeof(*rsdt), 1);
  199 +