Commit e6afc2f4b9a93403b20cad9cecb05478f9067ea2
1 parent
1000822b
SH4: convert a few helpers to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
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4 changed files
with
52 additions
and
58 deletions
target-sh4/helper.h
... | ... | @@ -2,3 +2,9 @@ |
2 | 2 | #define DEF_HELPER(ret, name, params) ret name params; |
3 | 3 | #endif |
4 | 4 | |
5 | +DEF_HELPER(void, helper_ldtlb, (void)) | |
6 | +DEF_HELPER(void, helper_raise_illegal_instruction, (void)) | |
7 | +DEF_HELPER(void, helper_raise_slot_illegal_instruction, (void)) | |
8 | +DEF_HELPER(void, helper_debug, (void)) | |
9 | +DEF_HELPER(void, helper_sleep, (void)) | |
10 | +DEF_HELPER(void, helper_trapa, (uint32_t)) | ... | ... |
target-sh4/op.c
... | ... | @@ -37,12 +37,6 @@ static inline void cond_t(int cond) |
37 | 37 | clr_t(); |
38 | 38 | } |
39 | 39 | |
40 | -void OPPROTO op_ldtlb(void) | |
41 | -{ | |
42 | - helper_ldtlb(); | |
43 | - RETURN(); | |
44 | -} | |
45 | - | |
46 | 40 | void OPPROTO op_frchg(void) |
47 | 41 | { |
48 | 42 | env->fpscr ^= FPSCR_FR; |
... | ... | @@ -178,14 +172,6 @@ void OPPROTO op_subv_T0_T1(void) |
178 | 172 | RETURN(); |
179 | 173 | } |
180 | 174 | |
181 | -void OPPROTO op_trapa(void) | |
182 | -{ | |
183 | - env->tra = PARAM1 << 2; | |
184 | - env->exception_index = 0x160; | |
185 | - do_raise_exception(); | |
186 | - RETURN(); | |
187 | -} | |
188 | - | |
189 | 175 | void OPPROTO op_ldcl_rMplus_rN_bank(void) |
190 | 176 | { |
191 | 177 | env->gregs[PARAM2] = env->gregs[PARAM1]; |
... | ... | @@ -491,33 +477,6 @@ void OPPROTO op_movl_FT0_fpul(void) |
491 | 477 | RETURN(); |
492 | 478 | } |
493 | 479 | |
494 | -void OPPROTO op_raise_illegal_instruction(void) | |
495 | -{ | |
496 | - env->exception_index = 0x180; | |
497 | - do_raise_exception(); | |
498 | - RETURN(); | |
499 | -} | |
500 | - | |
501 | -void OPPROTO op_raise_slot_illegal_instruction(void) | |
502 | -{ | |
503 | - env->exception_index = 0x1a0; | |
504 | - do_raise_exception(); | |
505 | - RETURN(); | |
506 | -} | |
507 | - | |
508 | -void OPPROTO op_debug(void) | |
509 | -{ | |
510 | - env->exception_index = EXCP_DEBUG; | |
511 | - cpu_loop_exit(); | |
512 | -} | |
513 | - | |
514 | -void OPPROTO op_sleep(void) | |
515 | -{ | |
516 | - env->halted = 1; | |
517 | - env->exception_index = EXCP_HLT; | |
518 | - cpu_loop_exit(); | |
519 | -} | |
520 | - | |
521 | 480 | /* Load and store */ |
522 | 481 | #define MEMSUFFIX _raw |
523 | 482 | #include "op_mem.c" | ... | ... |
target-sh4/op_helper.c
... | ... | @@ -20,11 +20,6 @@ |
20 | 20 | #include <assert.h> |
21 | 21 | #include "exec.h" |
22 | 22 | |
23 | -void do_raise_exception(void) | |
24 | -{ | |
25 | - cpu_loop_exit(); | |
26 | -} | |
27 | - | |
28 | 23 | #ifndef CONFIG_USER_ONLY |
29 | 24 | |
30 | 25 | #define MMUSUFFIX _mmu |
... | ... | @@ -64,7 +59,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
64 | 59 | cpu_restore_state(tb, env, pc, NULL); |
65 | 60 | } |
66 | 61 | } |
67 | - do_raise_exception(); | |
62 | + cpu_loop_exit(); | |
68 | 63 | } |
69 | 64 | env = saved_env; |
70 | 65 | } |
... | ... | @@ -81,6 +76,38 @@ void helper_ldtlb(void) |
81 | 76 | #endif |
82 | 77 | } |
83 | 78 | |
79 | +void helper_raise_illegal_instruction(void) | |
80 | +{ | |
81 | + env->exception_index = 0x180; | |
82 | + cpu_loop_exit(); | |
83 | +} | |
84 | + | |
85 | +void helper_raise_slot_illegal_instruction(void) | |
86 | +{ | |
87 | + env->exception_index = 0x1a0; | |
88 | + cpu_loop_exit(); | |
89 | +} | |
90 | + | |
91 | +void helper_debug(void) | |
92 | +{ | |
93 | + env->exception_index = EXCP_DEBUG; | |
94 | + cpu_loop_exit(); | |
95 | +} | |
96 | + | |
97 | +void helper_sleep(void) | |
98 | +{ | |
99 | + env->halted = 1; | |
100 | + env->exception_index = EXCP_HLT; | |
101 | + cpu_loop_exit(); | |
102 | +} | |
103 | + | |
104 | +void helper_trapa(uint32_t tra) | |
105 | +{ | |
106 | + env->tra = tra << 2; | |
107 | + env->exception_index = 0x160; | |
108 | + cpu_loop_exit(); | |
109 | +} | |
110 | + | |
84 | 111 | void helper_addc_T0_T1(void) |
85 | 112 | { |
86 | 113 | uint32_t tmp0, tmp1; | ... | ... |
target-sh4/translate.c
... | ... | @@ -248,7 +248,7 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
248 | 248 | } else { |
249 | 249 | tcg_gen_movi_i32(cpu_pc, dest); |
250 | 250 | if (ctx->singlestep_enabled) |
251 | - gen_op_debug(); | |
251 | + tcg_gen_helper_0_0(helper_debug); | |
252 | 252 | tcg_gen_exit_tb(0); |
253 | 253 | } |
254 | 254 | } |
... | ... | @@ -260,7 +260,7 @@ static void gen_jump(DisasContext * ctx) |
260 | 260 | delayed jump as immediate jump are conditinal jumps */ |
261 | 261 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
262 | 262 | if (ctx->singlestep_enabled) |
263 | - gen_op_debug(); | |
263 | + tcg_gen_helper_0_0(helper_debug); | |
264 | 264 | tcg_gen_exit_tb(0); |
265 | 265 | } else { |
266 | 266 | gen_goto_tb(ctx, 0, ctx->delayed_pc); |
... | ... | @@ -368,7 +368,7 @@ static inline void gen_store_flags(uint32_t flags) |
368 | 368 | |
369 | 369 | #define CHECK_NOT_DELAY_SLOT \ |
370 | 370 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ |
371 | - {gen_op_raise_slot_illegal_instruction (); ctx->bstate = BS_EXCP; \ | |
371 | + {tcg_gen_helper_0_0(helper_raise_slot_illegal_instruction); ctx->bstate = BS_EXCP; \ | |
372 | 372 | return;} |
373 | 373 | |
374 | 374 | void _decode_opc(DisasContext * ctx) |
... | ... | @@ -400,7 +400,7 @@ void _decode_opc(DisasContext * ctx) |
400 | 400 | #if defined(CONFIG_USER_ONLY) |
401 | 401 | assert(0); /* XXXXX */ |
402 | 402 | #else |
403 | - gen_op_ldtlb(); | |
403 | + tcg_gen_helper_0_0(helper_ldtlb); | |
404 | 404 | #endif |
405 | 405 | return; |
406 | 406 | case 0x002b: /* rte */ |
... | ... | @@ -428,9 +428,9 @@ void _decode_opc(DisasContext * ctx) |
428 | 428 | return; |
429 | 429 | case 0x001b: /* sleep */ |
430 | 430 | if (ctx->memidx) { |
431 | - gen_op_sleep(); | |
431 | + tcg_gen_helper_0_0(helper_sleep); | |
432 | 432 | } else { |
433 | - gen_op_raise_illegal_instruction(); | |
433 | + tcg_gen_helper_0_0(helper_raise_illegal_instruction); | |
434 | 434 | ctx->bstate = BS_EXCP; |
435 | 435 | } |
436 | 436 | return; |
... | ... | @@ -1060,8 +1060,10 @@ void _decode_opc(DisasContext * ctx) |
1060 | 1060 | gen_op_stb_T0_T1(ctx); |
1061 | 1061 | return; |
1062 | 1062 | case 0xc300: /* trapa #imm */ |
1063 | - CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(cpu_pc, ctx->pc); | |
1064 | - gen_op_trapa(B7_0); | |
1063 | + CHECK_NOT_DELAY_SLOT | |
1064 | + tcg_gen_movi_i32(cpu_pc, ctx->pc); | |
1065 | + tcg_gen_movi_i32(cpu_T[0], B7_0); | |
1066 | + tcg_gen_helper_0_1(helper_trapa, cpu_T[0]); | |
1065 | 1067 | ctx->bstate = BS_BRANCH; |
1066 | 1068 | return; |
1067 | 1069 | case 0xc800: /* tst #imm,R0 */ |
... | ... | @@ -1355,7 +1357,7 @@ void _decode_opc(DisasContext * ctx) |
1355 | 1357 | |
1356 | 1358 | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", |
1357 | 1359 | ctx->opcode, ctx->pc); |
1358 | - gen_op_raise_illegal_instruction(); | |
1360 | + tcg_gen_helper_0_0(helper_raise_illegal_instruction); | |
1359 | 1361 | ctx->bstate = BS_EXCP; |
1360 | 1362 | } |
1361 | 1363 | |
... | ... | @@ -1434,7 +1436,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1434 | 1436 | if (ctx.pc == env->breakpoints[i]) { |
1435 | 1437 | /* We have hit a breakpoint - make sure PC is up-to-date */ |
1436 | 1438 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
1437 | - gen_op_debug(); | |
1439 | + tcg_gen_helper_0_0(helper_debug); | |
1438 | 1440 | ctx.bstate = BS_EXCP; |
1439 | 1441 | break; |
1440 | 1442 | } |
... | ... | @@ -1475,7 +1477,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1475 | 1477 | if (tb->cflags & CF_LAST_IO) |
1476 | 1478 | gen_io_end(); |
1477 | 1479 | if (env->singlestep_enabled) { |
1478 | - gen_op_debug(); | |
1480 | + tcg_gen_helper_0_0(helper_debug); | |
1479 | 1481 | } else { |
1480 | 1482 | switch (ctx.bstate) { |
1481 | 1483 | case BS_STOP: | ... | ... |