gwj / at91sam9263 · Commits

Commit e6a71ae327a388723182a504bb253777ec36869b

Authored by ths
1 parent 5f4da8c0

Add support for 82371FB (Step A1) and Improved support for 82371SB 

(Function 1), by Carlo Marcelo Arenas Belon.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2353 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 76 additions and 2 deletions
hw/ide.c
  View file @e6a71ae
... ... @@ -2577,6 +2577,55 @@ static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
2577 2577 return 0;
2578 2578 }
2579 2579  
  2580 +static void piix3_reset(PCIIDEState *d)
  2581 +{
  2582 + uint8_t *pci_conf = d->dev.config;
  2583 +
  2584 + pci_conf[0x04] = 0x00;
  2585 + pci_conf[0x05] = 0x00;
  2586 + pci_conf[0x06] = 0x80; /* FBC */
  2587 + pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  2588 + pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
  2589 +}
  2590 +
  2591 +void pci_piix_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
  2592 +{
  2593 + PCIIDEState *d;
  2594 + uint8_t *pci_conf;
  2595 +
  2596 + /* register a function 1 of PIIX */
  2597 + d = (PCIIDEState *)pci_register_device(bus, "PIIX IDE",
  2598 + sizeof(PCIIDEState),
  2599 + devfn,
  2600 + NULL, NULL);
  2601 + d->type = IDE_TYPE_PIIX3;
  2602 +
  2603 + pci_conf = d->dev.config;
  2604 + pci_conf[0x00] = 0x86; // Intel
  2605 + pci_conf[0x01] = 0x80;
  2606 + pci_conf[0x02] = 0x30;
  2607 + pci_conf[0x03] = 0x12;
  2608 + pci_conf[0x08] = 0x02; // Step A1
  2609 + pci_conf[0x09] = 0x80; // legacy ATA mode
  2610 + pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
  2611 + pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
  2612 + pci_conf[0x0e] = 0x00; // header_type
  2613 +
  2614 + piix3_reset(d);
  2615 +
  2616 + pci_register_io_region((PCIDevice *)d, 4, 0x10,
  2617 + PCI_ADDRESS_SPACE_IO, bmdma_map);
  2618 +
  2619 + ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
  2620 + pic_set_irq_new, isa_pic, 14);
  2621 + ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
  2622 + pic_set_irq_new, isa_pic, 15);
  2623 + ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
  2624 + ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
  2625 +
  2626 + register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
  2627 +}
  2628 +
2580 2629 /* hd_table must contain 4 block drivers */
2581 2630 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2582 2631 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
... ... @@ -2601,6 +2650,8 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
2601 2650 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2602 2651 pci_conf[0x0e] = 0x00; // header_type
2603 2652  
  2653 + piix3_reset(d);
  2654 +
2604 2655 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2605 2656 PCI_ADDRESS_SPACE_IO, bmdma_map);
2606 2657  
... ...
hw/piix_pci.c
  View file @e6a71ae
... ... @@ -246,7 +246,6 @@ static void piix3_reset(PCIDevice *d)
246 246 pci_conf[0x80] = 0x00;
247 247 pci_conf[0x82] = 0x00;
248 248 pci_conf[0xa0] = 0x08;
249   - pci_conf[0xa0] = 0x08;
250 249 pci_conf[0xa2] = 0x00;
251 250 pci_conf[0xa3] = 0x00;
252 251 pci_conf[0xa4] = 0x00;
... ... @@ -284,7 +283,6 @@ static void piix4_reset(PCIDevice *d)
284 283 pci_conf[0x80] = 0x00;
285 284 pci_conf[0x82] = 0x00;
286 285 pci_conf[0xa0] = 0x08;
287   - pci_conf[0xa0] = 0x08;
288 286 pci_conf[0xa2] = 0x00;
289 287 pci_conf[0xa3] = 0x00;
290 288 pci_conf[0xa4] = 0x00;
... ... @@ -312,6 +310,31 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id)
312 310 return pci_device_load(d, f);
313 311 }
314 312  
  313 +int piix_init(PCIBus *bus, int devfn)
  314 +{
  315 + PCIDevice *d;
  316 + uint8_t *pci_conf;
  317 +
  318 + d = pci_register_device(bus, "PIIX", sizeof(PCIDevice),
  319 + devfn, NULL, NULL);
  320 + register_savevm("PIIX", 0, 2, piix_save, piix_load, d);
  321 +
  322 + piix3_dev = d;
  323 + pci_conf = d->config;
  324 +
  325 + pci_conf[0x00] = 0x86; // Intel
  326 + pci_conf[0x01] = 0x80;
  327 + pci_conf[0x02] = 0x2E; // 82371FB PIIX PCI-to-ISA bridge
  328 + pci_conf[0x03] = 0x12;
  329 + pci_conf[0x08] = 0x02; // Step A1
  330 + pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
  331 + pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
  332 + pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
  333 +
  334 + piix3_reset(d);
  335 + return d->devfn;
  336 +}
  337 +
315 338 int piix3_init(PCIBus *bus, int devfn)
316 339 {
317 340 PCIDevice *d;
... ...