gwj / at91sam9263 · Commits

Commit e677137d996983b614c6612e9c09cb7742169045

Authored by pbrook
1 parent ad69471c

ARM TCG conversion 15/16. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4152 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 8 changed files with 1124 additions and 812 deletions
Makefile.target
  View file @e677137
@@ -211,7 +211,7 @@ LIBOBJS+= op_helper.o helper.o @@ -211,7 +211,7 @@ LIBOBJS+= op_helper.o helper.o
211 endif 211 endif
212 212
213 ifeq ($(TARGET_BASE_ARCH), arm) 213 ifeq ($(TARGET_BASE_ARCH), arm)
214 -LIBOBJS+= op_helper.o helper.o neon_helper.o 214 +LIBOBJS+= op_helper.o helper.o neon_helper.o iwmmxt_helper.o
215 endif 215 endif
216 216
217 ifeq ($(TARGET_BASE_ARCH), sh4) 217 ifeq ($(TARGET_BASE_ARCH), sh4)
target-arm/helpers.h
  View file @e677137
@@ -431,6 +431,103 @@ DEF_HELPER_1_2(neon_cgt_f32, uint32_t, (uint32_t, uint32_t)) @@ -431,6 +431,103 @@ DEF_HELPER_1_2(neon_cgt_f32, uint32_t, (uint32_t, uint32_t))
431 DEF_HELPER_1_2(neon_acge_f32, uint32_t, (uint32_t, uint32_t)) 431 DEF_HELPER_1_2(neon_acge_f32, uint32_t, (uint32_t, uint32_t))
432 DEF_HELPER_1_2(neon_acgt_f32, uint32_t, (uint32_t, uint32_t)) 432 DEF_HELPER_1_2(neon_acgt_f32, uint32_t, (uint32_t, uint32_t))
433 433
  434 +/* iwmmxt_helper.c */
  435 +DEF_HELPER_1_2(iwmmxt_maddsq, uint64_t, (uint64_t, uint64_t))
  436 +DEF_HELPER_1_2(iwmmxt_madduq, uint64_t, (uint64_t, uint64_t))
  437 +DEF_HELPER_1_2(iwmmxt_sadb, uint64_t, (uint64_t, uint64_t))
  438 +DEF_HELPER_1_2(iwmmxt_sadw, uint64_t, (uint64_t, uint64_t))
  439 +DEF_HELPER_1_2(iwmmxt_mulslw, uint64_t, (uint64_t, uint64_t))
  440 +DEF_HELPER_1_2(iwmmxt_mulshw, uint64_t, (uint64_t, uint64_t))
  441 +DEF_HELPER_1_2(iwmmxt_mululw, uint64_t, (uint64_t, uint64_t))
  442 +DEF_HELPER_1_2(iwmmxt_muluhw, uint64_t, (uint64_t, uint64_t))
  443 +DEF_HELPER_1_2(iwmmxt_macsw, uint64_t, (uint64_t, uint64_t))
  444 +DEF_HELPER_1_2(iwmmxt_macuw, uint64_t, (uint64_t, uint64_t))
  445 +DEF_HELPER_1_1(iwmmxt_setpsr_nz, uint32_t, (uint64_t))
  446 +
  447 +#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \
  448 +DEF_HELPER_1_3(iwmmxt_##name##b, uint64_t, (CPUState *, uint64_t, uint64_t)) \
  449 +DEF_HELPER_1_3(iwmmxt_##name##w, uint64_t, (CPUState *, uint64_t, uint64_t)) \
  450 +DEF_HELPER_1_3(iwmmxt_##name##l, uint64_t, (CPUState *, uint64_t, uint64_t)) \
  451 +
  452 +DEF_IWMMXT_HELPER_SIZE_ENV(unpackl)
  453 +DEF_IWMMXT_HELPER_SIZE_ENV(unpackh)
  454 +
  455 +DEF_HELPER_1_2(iwmmxt_unpacklub, uint64_t, (CPUState *, uint64_t))
  456 +DEF_HELPER_1_2(iwmmxt_unpackluw, uint64_t, (CPUState *, uint64_t))
  457 +DEF_HELPER_1_2(iwmmxt_unpacklul, uint64_t, (CPUState *, uint64_t))
  458 +DEF_HELPER_1_2(iwmmxt_unpackhub, uint64_t, (CPUState *, uint64_t))
  459 +DEF_HELPER_1_2(iwmmxt_unpackhuw, uint64_t, (CPUState *, uint64_t))
  460 +DEF_HELPER_1_2(iwmmxt_unpackhul, uint64_t, (CPUState *, uint64_t))
  461 +DEF_HELPER_1_2(iwmmxt_unpacklsb, uint64_t, (CPUState *, uint64_t))
  462 +DEF_HELPER_1_2(iwmmxt_unpacklsw, uint64_t, (CPUState *, uint64_t))
  463 +DEF_HELPER_1_2(iwmmxt_unpacklsl, uint64_t, (CPUState *, uint64_t))
  464 +DEF_HELPER_1_2(iwmmxt_unpackhsb, uint64_t, (CPUState *, uint64_t))
  465 +DEF_HELPER_1_2(iwmmxt_unpackhsw, uint64_t, (CPUState *, uint64_t))
  466 +DEF_HELPER_1_2(iwmmxt_unpackhsl, uint64_t, (CPUState *, uint64_t))
  467 +
  468 +DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq)
  469 +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu)
  470 +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts)
  471 +
  472 +DEF_IWMMXT_HELPER_SIZE_ENV(mins)
  473 +DEF_IWMMXT_HELPER_SIZE_ENV(minu)
  474 +DEF_IWMMXT_HELPER_SIZE_ENV(maxs)
  475 +DEF_IWMMXT_HELPER_SIZE_ENV(maxu)
  476 +
  477 +DEF_IWMMXT_HELPER_SIZE_ENV(subn)
  478 +DEF_IWMMXT_HELPER_SIZE_ENV(addn)
  479 +DEF_IWMMXT_HELPER_SIZE_ENV(subu)
  480 +DEF_IWMMXT_HELPER_SIZE_ENV(addu)
  481 +DEF_IWMMXT_HELPER_SIZE_ENV(subs)
  482 +DEF_IWMMXT_HELPER_SIZE_ENV(adds)
  483 +
  484 +DEF_HELPER_1_3(iwmmxt_avgb0, uint64_t, (CPUState *, uint64_t, uint64_t))
  485 +DEF_HELPER_1_3(iwmmxt_avgb1, uint64_t, (CPUState *, uint64_t, uint64_t))
  486 +DEF_HELPER_1_3(iwmmxt_avgw0, uint64_t, (CPUState *, uint64_t, uint64_t))
  487 +DEF_HELPER_1_3(iwmmxt_avgw1, uint64_t, (CPUState *, uint64_t, uint64_t))
  488 +
  489 +DEF_HELPER_1_2(iwmmxt_msadb, uint64_t, (uint64_t, uint64_t))
  490 +
  491 +DEF_HELPER_1_3(iwmmxt_align, uint64_t, (uint64_t, uint64_t, uint32_t))
  492 +DEF_HELPER_1_4(iwmmxt_insr, uint64_t, (uint64_t, uint32_t, uint32_t, uint32_t))
  493 +
  494 +DEF_HELPER_1_1(iwmmxt_bcstb, uint64_t, (uint32_t))
  495 +DEF_HELPER_1_1(iwmmxt_bcstw, uint64_t, (uint32_t))
  496 +DEF_HELPER_1_1(iwmmxt_bcstl, uint64_t, (uint32_t))
  497 +
  498 +DEF_HELPER_1_1(iwmmxt_addcb, uint64_t, (uint64_t))
  499 +DEF_HELPER_1_1(iwmmxt_addcw, uint64_t, (uint64_t))
  500 +DEF_HELPER_1_1(iwmmxt_addcl, uint64_t, (uint64_t))
  501 +
  502 +DEF_HELPER_1_1(iwmmxt_msbb, uint32_t, (uint64_t))
  503 +DEF_HELPER_1_1(iwmmxt_msbw, uint32_t, (uint64_t))
  504 +DEF_HELPER_1_1(iwmmxt_msbl, uint32_t, (uint64_t))
  505 +
  506 +DEF_HELPER_1_3(iwmmxt_srlw, uint64_t, (CPUState *, uint64_t, uint32_t))
  507 +DEF_HELPER_1_3(iwmmxt_srll, uint64_t, (CPUState *, uint64_t, uint32_t))
  508 +DEF_HELPER_1_3(iwmmxt_srlq, uint64_t, (CPUState *, uint64_t, uint32_t))
  509 +DEF_HELPER_1_3(iwmmxt_sllw, uint64_t, (CPUState *, uint64_t, uint32_t))
  510 +DEF_HELPER_1_3(iwmmxt_slll, uint64_t, (CPUState *, uint64_t, uint32_t))
  511 +DEF_HELPER_1_3(iwmmxt_sllq, uint64_t, (CPUState *, uint64_t, uint32_t))
  512 +DEF_HELPER_1_3(iwmmxt_sraw, uint64_t, (CPUState *, uint64_t, uint32_t))
  513 +DEF_HELPER_1_3(iwmmxt_sral, uint64_t, (CPUState *, uint64_t, uint32_t))
  514 +DEF_HELPER_1_3(iwmmxt_sraq, uint64_t, (CPUState *, uint64_t, uint32_t))
  515 +DEF_HELPER_1_3(iwmmxt_rorw, uint64_t, (CPUState *, uint64_t, uint32_t))
  516 +DEF_HELPER_1_3(iwmmxt_rorl, uint64_t, (CPUState *, uint64_t, uint32_t))
  517 +DEF_HELPER_1_3(iwmmxt_rorq, uint64_t, (CPUState *, uint64_t, uint32_t))
  518 +DEF_HELPER_1_3(iwmmxt_shufh, uint64_t, (CPUState *, uint64_t, uint32_t))
  519 +
  520 +DEF_HELPER_1_3(iwmmxt_packuw, uint64_t, (CPUState *, uint64_t, uint64_t))
  521 +DEF_HELPER_1_3(iwmmxt_packul, uint64_t, (CPUState *, uint64_t, uint64_t))
  522 +DEF_HELPER_1_3(iwmmxt_packuq, uint64_t, (CPUState *, uint64_t, uint64_t))
  523 +DEF_HELPER_1_3(iwmmxt_packsw, uint64_t, (CPUState *, uint64_t, uint64_t))
  524 +DEF_HELPER_1_3(iwmmxt_packsl, uint64_t, (CPUState *, uint64_t, uint64_t))
  525 +DEF_HELPER_1_3(iwmmxt_packsq, uint64_t, (CPUState *, uint64_t, uint64_t))
  526 +
  527 +DEF_HELPER_1_3(iwmmxt_muladdsl, uint64_t, (uint64_t, uint32_t, uint32_t))
  528 +DEF_HELPER_1_3(iwmmxt_muladdsw, uint64_t, (uint64_t, uint32_t, uint32_t))
  529 +DEF_HELPER_1_3(iwmmxt_muladdswl, uint64_t, (uint64_t, uint32_t, uint32_t))
  530 +
434 #undef DEF_HELPER 531 #undef DEF_HELPER
435 #undef DEF_HELPER_0_0 532 #undef DEF_HELPER_0_0
436 #undef DEF_HELPER_0_1 533 #undef DEF_HELPER_0_1
target-arm/iwmmxt_helper.c 0 → 100644
  View file @e677137
  1 +/*
  2 + * iwMMXt micro operations for XScale.
  3 + *
  4 + * Copyright (c) 2007 OpenedHand, Ltd.
  5 + * Written by Andrzej Zaborowski <andrew@openedhand.com>
  6 + * Copyright (c) 2008 CodeSourcery
  7 + *
  8 + * This library is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU Lesser General Public
  10 + * License as published by the Free Software Foundation; either
  11 + * version 2 of the License, or (at your option) any later version.
  12 + *
  13 + * This library is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16 + * Lesser General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU Lesser General Public
  19 + * License along with this library; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21 + */
  22 +
  23 +#include <stdlib.h>
  24 +#include <stdio.h>
  25 +
  26 +#include "cpu.h"
  27 +#include "exec-all.h"
  28 +#include "helpers.h"
  29 +
  30 +/* iwMMXt macros extracted from GNU gdb. */
  31 +
  32 +/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
  33 +#define SIMD8_SET( v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n)))
  34 +#define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n)))
  35 +#define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))
  36 +#define SIMD64_SET(v, n) ((v != 0) << (32 + (n)))
  37 +/* Flags to pass as "n" above. */
  38 +#define SIMD_NBIT -1
  39 +#define SIMD_ZBIT -2
  40 +#define SIMD_CBIT -3
  41 +#define SIMD_VBIT -4
  42 +/* Various status bit macros. */
  43 +#define NBIT8(x) ((x) & 0x80)
  44 +#define NBIT16(x) ((x) & 0x8000)
  45 +#define NBIT32(x) ((x) & 0x80000000)
  46 +#define NBIT64(x) ((x) & 0x8000000000000000ULL)
  47 +#define ZBIT8(x) (((x) & 0xff) == 0)
  48 +#define ZBIT16(x) (((x) & 0xffff) == 0)
  49 +#define ZBIT32(x) (((x) & 0xffffffff) == 0)
  50 +#define ZBIT64(x) (x == 0)
  51 +/* Sign extension macros. */
  52 +#define EXTEND8H(a) ((uint16_t) (int8_t) (a))
  53 +#define EXTEND8(a) ((uint32_t) (int8_t) (a))
  54 +#define EXTEND16(a) ((uint32_t) (int16_t) (a))
  55 +#define EXTEND16S(a) ((int32_t) (int16_t) (a))
  56 +#define EXTEND32(a) ((uint64_t) (int32_t) (a))
  57 +
  58 +uint64_t HELPER(iwmmxt_maddsq)(uint64_t a, uint64_t b)
  59 +{
  60 + a = ((
  61 + EXTEND16S((a >> 0) & 0xffff) * EXTEND16S((b >> 0) & 0xffff) +
  62 + EXTEND16S((a >> 16) & 0xffff) * EXTEND16S((b >> 16) & 0xffff)
  63 + ) & 0xffffffff) | ((uint64_t) (
  64 + EXTEND16S((a >> 32) & 0xffff) * EXTEND16S((b >> 32) & 0xffff) +
  65 + EXTEND16S((a >> 48) & 0xffff) * EXTEND16S((b >> 48) & 0xffff)
  66 + ) << 32);
  67 + return a;
  68 +}
  69 +
  70 +uint64_t HELPER(iwmmxt_madduq)(uint64_t a, uint64_t b)
  71 +{
  72 + a = ((
  73 + ((a >> 0) & 0xffff) * ((b >> 0) & 0xffff) +
  74 + ((a >> 16) & 0xffff) * ((b >> 16) & 0xffff)
  75 + ) & 0xffffffff) | ((
  76 + ((a >> 32) & 0xffff) * ((b >> 32) & 0xffff) +
  77 + ((a >> 48) & 0xffff) * ((b >> 48) & 0xffff)
  78 + ) << 32);
  79 + return a;
  80 +}
  81 +
  82 +uint64_t HELPER(iwmmxt_sadb)(uint64_t a, uint64_t b)
  83 +{
  84 +#define abs(x) (((x) >= 0) ? x : -x)
  85 +#define SADB(SHR) abs((int) ((a >> SHR) & 0xff) - (int) ((b >> SHR) & 0xff))
  86 + return
  87 + SADB(0) + SADB(8) + SADB(16) + SADB(24) +
  88 + SADB(32) + SADB(40) + SADB(48) + SADB(56);
  89 +#undef SADB
  90 +}
  91 +
  92 +uint64_t HELPER(iwmmxt_sadw)(uint64_t a, uint64_t b)
  93 +{
  94 +#define SADW(SHR) \
  95 + abs((int) ((a >> SHR) & 0xffff) - (int) ((b >> SHR) & 0xffff))
  96 + return SADW(0) + SADW(16) + SADW(32) + SADW(48);
  97 +#undef SADW
  98 +}
  99 +
  100 +uint64_t HELPER(iwmmxt_mulslw)(uint64_t a, uint64_t b)
  101 +{
  102 +#define MULS(SHR) ((uint64_t) ((( \
  103 + EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \
  104 + ) >> 0) & 0xffff) << SHR)
  105 + return MULS(0) | MULS(16) | MULS(32) | MULS(48);
  106 +#undef MULS
  107 +}
  108 +
  109 +uint64_t HELPER(iwmmxt_mulshw)(uint64_t a, uint64_t b)
  110 +{
  111 +#define MULS(SHR) ((uint64_t) ((( \
  112 + EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \
  113 + ) >> 16) & 0xffff) << SHR)
  114 + return MULS(0) | MULS(16) | MULS(32) | MULS(48);
  115 +#undef MULS
  116 +}
  117 +
  118 +uint64_t HELPER(iwmmxt_mululw)(uint64_t a, uint64_t b)
  119 +{
  120 +#define MULU(SHR) ((uint64_t) ((( \
  121 + ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \
  122 + ) >> 0) & 0xffff) << SHR)
  123 + return MULU(0) | MULU(16) | MULU(32) | MULU(48);
  124 +#undef MULU
  125 +}
  126 +
  127 +uint64_t HELPER(iwmmxt_muluhw)(uint64_t a, uint64_t b)
  128 +{
  129 +#define MULU(SHR) ((uint64_t) ((( \
  130 + ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \
  131 + ) >> 16) & 0xffff) << SHR)
  132 + return MULU(0) | MULU(16) | MULU(32) | MULU(48);
  133 +#undef MULU
  134 +}
  135 +
  136 +uint64_t HELPER(iwmmxt_macsw)(uint64_t a, uint64_t b)
  137 +{
  138 +#define MACS(SHR) ( \
  139 + EXTEND16((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff))
  140 + return (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48));
  141 +#undef MACS
  142 +}
  143 +
  144 +uint64_t HELPER(iwmmxt_macuw)(uint64_t a, uint64_t b)
  145 +{
  146 +#define MACU(SHR) ( \
  147 + (uint32_t) ((a >> SHR) & 0xffff) * \
  148 + (uint32_t) ((b >> SHR) & 0xffff))
  149 + return MACU(0) + MACU(16) + MACU(32) + MACU(48);
  150 +#undef MACU
  151 +}
  152 +
  153 +#define NZBIT8(x, i) \
  154 + SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \
  155 + SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)
  156 +#define NZBIT16(x, i) \
  157 + SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \
  158 + SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
  159 +#define NZBIT32(x, i) \
  160 + SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
  161 + SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
  162 +#define NZBIT64(x) \
  163 + SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
  164 + SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
  165 +#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
  166 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUState *env, \
  167 + uint64_t a, uint64_t b) \
  168 +{ \
  169 + a = \
  170 + (((a >> SH0) & 0xff) << 0) | (((b >> SH0) & 0xff) << 8) | \
  171 + (((a >> SH1) & 0xff) << 16) | (((b >> SH1) & 0xff) << 24) | \
  172 + (((a >> SH2) & 0xff) << 32) | (((b >> SH2) & 0xff) << 40) | \
  173 + (((a >> SH3) & 0xff) << 48) | (((b >> SH3) & 0xff) << 56); \
  174 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  175 + NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) | \
  176 + NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) | \
  177 + NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) | \
  178 + NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
  179 + return a; \
  180 +} \
  181 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUState *env, \
  182 + uint64_t a, uint64_t b) \
  183 +{ \
  184 + a = \
  185 + (((a >> SH0) & 0xffff) << 0) | \
  186 + (((b >> SH0) & 0xffff) << 16) | \
  187 + (((a >> SH2) & 0xffff) << 32) | \
  188 + (((b >> SH2) & 0xffff) << 48); \
  189 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  190 + NZBIT8(a >> 0, 0) | NZBIT8(a >> 16, 1) | \
  191 + NZBIT8(a >> 32, 2) | NZBIT8(a >> 48, 3); \
  192 + return a; \
  193 +} \
  194 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUState *env, \
  195 + uint64_t a, uint64_t b) \
  196 +{ \
  197 + a = \
  198 + (((a >> SH0) & 0xffffffff) << 0) | \
  199 + (((b >> SH0) & 0xffffffff) << 32); \
  200 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  201 + NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); \
  202 + return a; \
  203 +} \
  204 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUState *env, \
  205 + uint64_t x) \
  206 +{ \
  207 + x = \
  208 + (((x >> SH0) & 0xff) << 0) | \
  209 + (((x >> SH1) & 0xff) << 16) | \
  210 + (((x >> SH2) & 0xff) << 32) | \
  211 + (((x >> SH3) & 0xff) << 48); \
  212 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  213 + NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | \
  214 + NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
  215 + return x; \
  216 +} \
  217 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUState *env, \
  218 + uint64_t x) \
  219 +{ \
  220 + x = \
  221 + (((x >> SH0) & 0xffff) << 0) | \
  222 + (((x >> SH2) & 0xffff) << 32); \
  223 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  224 + NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
  225 + return x; \
  226 +} \
  227 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUState *env, \
  228 + uint64_t x) \
  229 +{ \
  230 + x = (((x >> SH0) & 0xffffffff) << 0); \
  231 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0); \
  232 + return x; \
  233 +} \
  234 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUState *env, \
  235 + uint64_t x) \
  236 +{ \
  237 + x = \
  238 + ((uint64_t) EXTEND8H((x >> SH0) & 0xff) << 0) | \
  239 + ((uint64_t) EXTEND8H((x >> SH1) & 0xff) << 16) | \
  240 + ((uint64_t) EXTEND8H((x >> SH2) & 0xff) << 32) | \
  241 + ((uint64_t) EXTEND8H((x >> SH3) & 0xff) << 48); \
  242 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  243 + NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | \
  244 + NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
  245 + return x; \
  246 +} \
  247 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUState *env, \
  248 + uint64_t x) \
  249 +{ \
  250 + x = \
  251 + ((uint64_t) EXTEND16((x >> SH0) & 0xffff) << 0) | \
  252 + ((uint64_t) EXTEND16((x >> SH2) & 0xffff) << 32); \
  253 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  254 + NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
  255 + return x; \
  256 +} \
  257 +uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUState *env, \
  258 + uint64_t x) \
  259 +{ \
  260 + x = EXTEND32((x >> SH0) & 0xffffffff); \
  261 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0); \
  262 + return x; \
  263 +}
  264 +IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
  265 +IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
  266 +
  267 +#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
  268 +uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUState *env, \
  269 + uint64_t a, uint64_t b) \
  270 +{ \
  271 + a = \
  272 + CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \
  273 + CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) | \
  274 + CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) | \
  275 + CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff); \
  276 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  277 + NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) | \
  278 + NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) | \
  279 + NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) | \
  280 + NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
  281 + return a; \
  282 +} \
  283 +uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUState *env, \
  284 + uint64_t a, uint64_t b) \
  285 +{ \
  286 + a = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \
  287 + CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \
  288 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  289 + NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) | \
  290 + NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3); \
  291 + return a; \
  292 +} \
  293 +uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUState *env, \
  294 + uint64_t a, uint64_t b) \
  295 +{ \
  296 + a = CMP(0, Tl, O, 0xffffffff) | \
  297 + CMP(32, Tl, O, 0xffffffff); \
  298 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  299 + NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); \
  300 + return a; \
  301 +}
  302 +#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \
  303 + (TYPE) ((b >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
  304 +IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==)
  305 +IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >)
  306 +IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >)
  307 +#undef CMP
  308 +#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \
  309 + (TYPE) ((b >> SHR) & MASK)) ? a : b) & ((uint64_t) MASK << SHR))
  310 +IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <)
  311 +IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <)
  312 +IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >)
  313 +IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >)
  314 +#undef CMP
  315 +#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \
  316 + OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
  317 +IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -)
  318 +IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +)
  319 +#undef CMP
  320 +/* TODO Signed- and Unsigned-Saturation */
  321 +#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \
  322 + OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
  323 +IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -)
  324 +IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +)
  325 +IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -)
  326 +IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
  327 +#undef CMP
  328 +#undef IWMMXT_OP_CMP
  329 +
  330 +#define AVGB(SHR) ((( \
  331 + ((a >> SHR) & 0xff) + ((b >> SHR) & 0xff) + round) >> 1) << SHR)
  332 +#define IWMMXT_OP_AVGB(r) \
  333 +uint64_t HELPER(iwmmxt_avgb##r)(CPUState *env, uint64_t a, uint64_t b) \
  334 +{ \
  335 + const int round = r; \
  336 + a = AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) | \
  337 + AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56); \
  338 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  339 + SIMD8_SET(ZBIT8((a >> 0) & 0xff), SIMD_ZBIT, 0) | \
  340 + SIMD8_SET(ZBIT8((a >> 8) & 0xff), SIMD_ZBIT, 1) | \
  341 + SIMD8_SET(ZBIT8((a >> 16) & 0xff), SIMD_ZBIT, 2) | \
  342 + SIMD8_SET(ZBIT8((a >> 24) & 0xff), SIMD_ZBIT, 3) | \
  343 + SIMD8_SET(ZBIT8((a >> 32) & 0xff), SIMD_ZBIT, 4) | \
  344 + SIMD8_SET(ZBIT8((a >> 40) & 0xff), SIMD_ZBIT, 5) | \
  345 + SIMD8_SET(ZBIT8((a >> 48) & 0xff), SIMD_ZBIT, 6) | \
  346 + SIMD8_SET(ZBIT8((a >> 56) & 0xff), SIMD_ZBIT, 7); \
  347 + return a; \
  348 +}
  349 +IWMMXT_OP_AVGB(0)
  350 +IWMMXT_OP_AVGB(1)
  351 +#undef IWMMXT_OP_AVGB
  352 +#undef AVGB
  353 +
  354 +#define AVGW(SHR) ((( \
  355 + ((a >> SHR) & 0xffff) + ((b >> SHR) & 0xffff) + round) >> 1) << SHR)
  356 +#define IWMMXT_OP_AVGW(r) \
  357 +uint64_t HELPER(iwmmxt_avgw##r)(CPUState *env, uint64_t a, uint64_t b) \
  358 +{ \
  359 + const int round = r; \
  360 + a = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48); \
  361 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
  362 + SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
  363 + SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
  364 + SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
  365 + SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
  366 + return a; \
  367 +}
  368 +IWMMXT_OP_AVGW(0)
  369 +IWMMXT_OP_AVGW(1)
  370 +#undef IWMMXT_OP_AVGW
  371 +#undef AVGW
  372 +
  373 +uint64_t HELPER(iwmmxt_msadb)(uint64_t a, uint64_t b)
  374 +{
  375 + a = ((((a >> 0 ) & 0xffff) * ((b >> 0) & 0xffff) +
  376 + ((a >> 16) & 0xffff) * ((b >> 16) & 0xffff)) & 0xffffffff) |
  377 + ((((a >> 32) & 0xffff) * ((b >> 32) & 0xffff) +
  378 + ((a >> 48) & 0xffff) * ((b >> 48) & 0xffff)) << 32);
  379 + return a;
  380 +}
  381 +
  382 +uint64_t HELPER(iwmmxt_align)(uint64_t a, uint64_t b, uint32_t n)
  383 +{
  384 + a >>= n << 3;
  385 + a |= b << (64 - (n << 3));
  386 + return a;
  387 +}
  388 +
  389 +uint64_t HELPER(iwmmxt_insr)(uint64_t x, uint32_t a, uint32_t b, uint32_t n)
  390 +{
  391 + x &= ~((uint64_t) b << n);
  392 + x |= (uint64_t) (a & b) << n;
  393 + return x;
  394 +}
  395 +
  396 +uint32_t HELPER(iwmmxt_setpsr_nz)(uint64_t x)
  397 +{
  398 + return SIMD64_SET((x == 0), SIMD_ZBIT) |
  399 + SIMD64_SET((x & (1ULL << 63)), SIMD_NBIT);
  400 +}
  401 +
  402 +uint64_t HELPER(iwmmxt_bcstb)(uint32_t arg)
  403 +{
  404 + arg &= 0xff;
  405 + return
  406 + ((uint64_t) arg << 0 ) | ((uint64_t) arg << 8 ) |
  407 + ((uint64_t) arg << 16) | ((uint64_t) arg << 24) |
  408 + ((uint64_t) arg << 32) | ((uint64_t) arg << 40) |
  409 + ((uint64_t) arg << 48) | ((uint64_t) arg << 56);
  410 +}
  411 +
  412 +uint64_t HELPER(iwmmxt_bcstw)(uint32_t arg)
  413 +{
  414 + arg &= 0xffff;
  415 + return
  416 + ((uint64_t) arg << 0 ) | ((uint64_t) arg << 16) |
  417 + ((uint64_t) arg << 32) | ((uint64_t) arg << 48);
  418 +}
  419 +
  420 +uint64_t HELPER(iwmmxt_bcstl)(uint32_t arg)
  421 +{
  422 + return arg | ((uint64_t) arg << 32);
  423 +}
  424 +
  425 +uint64_t HELPER(iwmmxt_addcb)(uint64_t x)
  426 +{
  427 + return
  428 + ((x >> 0) & 0xff) + ((x >> 8) & 0xff) +
  429 + ((x >> 16) & 0xff) + ((x >> 24) & 0xff) +
  430 + ((x >> 32) & 0xff) + ((x >> 40) & 0xff) +
  431 + ((x >> 48) & 0xff) + ((x >> 56) & 0xff);
  432 +}
  433 +
  434 +uint64_t HELPER(iwmmxt_addcw)(uint64_t x)
  435 +{
  436 + return
  437 + ((x >> 0) & 0xffff) + ((x >> 16) & 0xffff) +
  438 + ((x >> 32) & 0xffff) + ((x >> 48) & 0xffff);
  439 +}
  440 +
  441 +uint64_t HELPER(iwmmxt_addcl)(uint64_t x)
  442 +{
  443 + return (x & 0xffffffff) + (x >> 32);
  444 +}
  445 +
  446 +uint32_t HELPER(iwmmxt_msbb)(uint64_t x)
  447 +{
  448 + return
  449 + ((x >> 7) & 0x01) | ((x >> 14) & 0x02) |
  450 + ((x >> 21) & 0x04) | ((x >> 28) & 0x08) |
  451 + ((x >> 35) & 0x10) | ((x >> 42) & 0x20) |
  452 + ((x >> 49) & 0x40) | ((x >> 56) & 0x80);
  453 +}
  454 +
  455 +uint32_t HELPER(iwmmxt_msbw)(uint64_t x)
  456 +{
  457 + return
  458 + ((x >> 15) & 0x01) | ((x >> 30) & 0x02) |
  459 + ((x >> 45) & 0x04) | ((x >> 52) & 0x08);
  460 +}
  461 +
  462 +uint32_t HELPER(iwmmxt_msbl)(uint64_t x)
  463 +{
  464 + return ((x >> 31) & 0x01) | ((x >> 62) & 0x02);
  465 +}
  466 +
  467 +/* FIXME: Split wCASF setting into a separate op to avoid env use. */
  468 +uint64_t HELPER(iwmmxt_srlw)(CPUState *env, uint64_t x, uint32_t n)
  469 +{
  470 + x = (((x & (0xffffll << 0)) >> n) & (0xffffll << 0)) |
  471 + (((x & (0xffffll << 16)) >> n) & (0xffffll << 16)) |
  472 + (((x & (0xffffll << 32)) >> n) & (0xffffll << 32)) |
  473 + (((x & (0xffffll << 48)) >> n) & (0xffffll << 48));
  474 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  475 + NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
  476 + NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
  477 + return x;
  478 +}
  479 +
  480 +uint64_t HELPER(iwmmxt_srll)(CPUState *env, uint64_t x, uint32_t n)
  481 +{
  482 + x = ((x & (0xffffffffll << 0)) >> n) |
  483 + ((x >> n) & (0xffffffffll << 32));
  484 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  485 + NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
  486 + return x;
  487 +}
  488 +
  489 +uint64_t HELPER(iwmmxt_srlq)(CPUState *env, uint64_t x, uint32_t n)
  490 +{
  491 + x >>= n;
  492 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
  493 + return x;
  494 +}
  495 +
  496 +uint64_t HELPER(iwmmxt_sllw)(CPUState *env, uint64_t x, uint32_t n)
  497 +{
  498 + x = (((x & (0xffffll << 0)) << n) & (0xffffll << 0)) |
  499 + (((x & (0xffffll << 16)) << n) & (0xffffll << 16)) |
  500 + (((x & (0xffffll << 32)) << n) & (0xffffll << 32)) |
  501 + (((x & (0xffffll << 48)) << n) & (0xffffll << 48));
  502 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  503 + NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
  504 + NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
  505 + return x;
  506 +}
  507 +
  508 +uint64_t HELPER(iwmmxt_slll)(CPUState *env, uint64_t x, uint32_t n)
  509 +{
  510 + x = ((x << n) & (0xffffffffll << 0)) |
  511 + ((x & (0xffffffffll << 32)) << n);
  512 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  513 + NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
  514 + return x;
  515 +}
  516 +
  517 +uint64_t HELPER(iwmmxt_sllq)(CPUState *env, uint64_t x, uint32_t n)
  518 +{
  519 + x <<= n;
  520 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
  521 + return x;
  522 +}
  523 +
  524 +uint64_t HELPER(iwmmxt_sraw)(CPUState *env, uint64_t x, uint32_t n)
  525 +{
  526 + x = ((uint64_t) ((EXTEND16(x >> 0) >> n) & 0xffff) << 0) |
  527 + ((uint64_t) ((EXTEND16(x >> 16) >> n) & 0xffff) << 16) |
  528 + ((uint64_t) ((EXTEND16(x >> 32) >> n) & 0xffff) << 32) |
  529 + ((uint64_t) ((EXTEND16(x >> 48) >> n) & 0xffff) << 48);
  530 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  531 + NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
  532 + NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
  533 + return x;
  534 +}
  535 +
  536 +uint64_t HELPER(iwmmxt_sral)(CPUState *env, uint64_t x, uint32_t n)
  537 +{
  538 + x = (((EXTEND32(x >> 0) >> n) & 0xffffffff) << 0) |
  539 + (((EXTEND32(x >> 32) >> n) & 0xffffffff) << 32);
  540 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  541 + NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
  542 + return x;
  543 +}
  544 +
  545 +uint64_t HELPER(iwmmxt_sraq)(CPUState *env, uint64_t x, uint32_t n)
  546 +{
  547 + x = (int64_t) x >> n;
  548 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
  549 + return x;
  550 +}
  551 +
  552 +uint64_t HELPER(iwmmxt_rorw)(CPUState *env, uint64_t x, uint32_t n)
  553 +{
  554 + x = ((((x & (0xffffll << 0)) >> n) |
  555 + ((x & (0xffffll << 0)) << (16 - n))) & (0xffffll << 0)) |
  556 + ((((x & (0xffffll << 16)) >> n) |
  557 + ((x & (0xffffll << 16)) << (16 - n))) & (0xffffll << 16)) |
  558 + ((((x & (0xffffll << 32)) >> n) |
  559 + ((x & (0xffffll << 32)) << (16 - n))) & (0xffffll << 32)) |
  560 + ((((x & (0xffffll << 48)) >> n) |
  561 + ((x & (0xffffll << 48)) << (16 - n))) & (0xffffll << 48));
  562 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  563 + NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
  564 + NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
  565 + return x;
  566 +}
  567 +
  568 +uint64_t HELPER(iwmmxt_rorl)(CPUState *env, uint64_t x, uint32_t n)
  569 +{
  570 + x = ((x & (0xffffffffll << 0)) >> n) |
  571 + ((x >> n) & (0xffffffffll << 32)) |
  572 + ((x << (32 - n)) & (0xffffffffll << 0)) |
  573 + ((x & (0xffffffffll << 32)) << (32 - n));
  574 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  575 + NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
  576 + return x;
  577 +}
  578 +
  579 +uint64_t HELPER(iwmmxt_rorq)(CPUState *env, uint64_t x, uint32_t n)
  580 +{
  581 + x = (x >> n) | (x << (64 - n));
  582 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
  583 + return x;
  584 +}
  585 +
  586 +uint64_t HELPER(iwmmxt_shufh)(CPUState *env, uint64_t x, uint32_t n)
  587 +{
  588 + x = (((x >> ((n << 4) & 0x30)) & 0xffff) << 0) |
  589 + (((x >> ((n << 2) & 0x30)) & 0xffff) << 16) |
  590 + (((x >> ((n << 0) & 0x30)) & 0xffff) << 32) |
  591 + (((x >> ((n >> 2) & 0x30)) & 0xffff) << 48);
  592 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  593 + NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
  594 + NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
  595 + return x;
  596 +}
  597 +
  598 +/* TODO: Unsigned-Saturation */
  599 +uint64_t HELPER(iwmmxt_packuw)(CPUState *env, uint64_t a, uint64_t b)
  600 +{
  601 + a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
  602 + (((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
  603 + (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) |
  604 + (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56);
  605 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  606 + NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |
  607 + NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |
  608 + NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |
  609 + NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);
  610 + return a;
  611 +}
  612 +
  613 +uint64_t HELPER(iwmmxt_packul)(CPUState *env, uint64_t a, uint64_t b)
  614 +{
  615 + a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
  616 + (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
  617 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  618 + NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) |
  619 + NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3);
  620 + return a;
  621 +}
  622 +
  623 +uint64_t HELPER(iwmmxt_packuq)(CPUState *env, uint64_t a, uint64_t b)
  624 +{
  625 + a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
  626 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  627 + NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);
  628 + return a;
  629 +}
  630 +
  631 +/* TODO: Signed-Saturation */
  632 +uint64_t HELPER(iwmmxt_packsw)(CPUState *env, uint64_t a, uint64_t b)
  633 +{
  634 + a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
  635 + (((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
  636 + (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) |
  637 + (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56);
  638 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  639 + NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |
  640 + NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |
  641 + NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |
  642 + NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);
  643 + return a;
  644 +}
  645 +
  646 +uint64_t HELPER(iwmmxt_packsl)(CPUState *env, uint64_t a, uint64_t b)
  647 +{
  648 + a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
  649 + (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
  650 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  651 + NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) |
  652 + NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3);
  653 + return a;
  654 +}
  655 +
  656 +uint64_t HELPER(iwmmxt_packsq)(CPUState *env, uint64_t a, uint64_t b)
  657 +{
  658 + a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
  659 + env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
  660 + NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);
  661 + return a;
  662 +}
  663 +
  664 +uint64_t HELPER(iwmmxt_muladdsl)(uint64_t c, uint32_t a, uint32_t b)
  665 +{
  666 + return c + ((int32_t) EXTEND32(a) * (int32_t) EXTEND32(b));
  667 +}
  668 +
  669 +uint64_t HELPER(iwmmxt_muladdsw)(uint64_t c, uint32_t a, uint32_t b)
  670 +{
  671 + c += EXTEND32(EXTEND16S((a >> 0) & 0xffff) *
  672 + EXTEND16S((b >> 0) & 0xffff));
  673 + c += EXTEND32(EXTEND16S((a >> 16) & 0xffff) *
  674 + EXTEND16S((b >> 16) & 0xffff));
  675 + return c;
  676 +}
  677 +
  678 +uint64_t HELPER(iwmmxt_muladdswl)(uint64_t c, uint32_t a, uint32_t b)
  679 +{
  680 + return c + (EXTEND32(EXTEND16S(a & 0xffff) *
  681 + EXTEND16S(b & 0xffff)));
  682 +}
target-arm/neon_helper.c
  View file @e677137
  1 +/*
  2 + * ARM NEON vector operations.
  3 + *
  4 + * Copyright (c) 2007, 2008 CodeSourcery.
  5 + * Written by Paul Brook
  6 + *
  7 + * This code is licenced under the GNU GPL v2.
  8 + */
1 #include <stdlib.h> 9 #include <stdlib.h>
2 #include <stdio.h> 10 #include <stdio.h>
3 11
target-arm/op.c
  View file @e677137
@@ -20,17 +20,6 @@ @@ -20,17 +20,6 @@
20 */ 20 */
21 #include "exec.h" 21 #include "exec.h"
22 22
23 -/* memory access */  
24 -  
25 -#define MEMSUFFIX _raw  
26 -#include "op_mem.h"  
27 -  
28 -#if !defined(CONFIG_USER_ONLY)  
29 -#define MEMSUFFIX _user  
30 -#include "op_mem.h"  
31 -#define MEMSUFFIX _kernel  
32 -#include "op_mem.h"  
33 -#endif  
34 -  
35 -/* iwMMXt support */  
36 -#include "op_iwmmxt.c" 23 +void OPPROTO op_dummy(void)
  24 +{
  25 +}
target-arm/op_iwmmxt.c deleted 100644 → 0
  View file @ad69471
1 -/*  
2 - * iwMMXt micro operations for XScale.  
3 - *  
4 - * Copyright (c) 2007 OpenedHand, Ltd.  
5 - * Written by Andrzej Zaborowski <andrew@openedhand.com>  
6 - *  
7 - * This library is free software; you can redistribute it and/or  
8 - * modify it under the terms of the GNU Lesser General Public  
9 - * License as published by the Free Software Foundation; either  
10 - * version 2 of the License, or (at your option) any later version.  
11 - *  
12 - * This library is distributed in the hope that it will be useful,  
13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of  
14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
15 - * Lesser General Public License for more details.  
16 - *  
17 - * You should have received a copy of the GNU Lesser General Public  
18 - * License along with this library; if not, write to the Free Software  
19 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  
20 - */  
21 -  
22 -#define M1 env->iwmmxt.regs[PARAM1]  
23 -  
24 -/* iwMMXt macros extracted from GNU gdb. */  
25 -  
26 -/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */  
27 -#define SIMD8_SET( v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n)))  
28 -#define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n)))  
29 -#define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))  
30 -#define SIMD64_SET(v, n) ((v != 0) << (32 + (n)))  
31 -/* Flags to pass as "n" above. */  
32 -#define SIMD_NBIT -1  
33 -#define SIMD_ZBIT -2  
34 -#define SIMD_CBIT -3  
35 -#define SIMD_VBIT -4  
36 -/* Various status bit macros. */  
37 -#define NBIT8(x) ((x) & 0x80)  
38 -#define NBIT16(x) ((x) & 0x8000)  
39 -#define NBIT32(x) ((x) & 0x80000000)  
40 -#define NBIT64(x) ((x) & 0x8000000000000000ULL)  
41 -#define ZBIT8(x) (((x) & 0xff) == 0)  
42 -#define ZBIT16(x) (((x) & 0xffff) == 0)  
43 -#define ZBIT32(x) (((x) & 0xffffffff) == 0)  
44 -#define ZBIT64(x) (x == 0)  
45 -/* Sign extension macros. */  
46 -#define EXTEND8H(a) ((uint16_t) (int8_t) (a))  
47 -#define EXTEND8(a) ((uint32_t) (int8_t) (a))  
48 -#define EXTEND16(a) ((uint32_t) (int16_t) (a))  
49 -#define EXTEND16S(a) ((int32_t) (int16_t) (a))  
50 -#define EXTEND32(a) ((uint64_t) (int32_t) (a))  
51 -  
52 -void OPPROTO op_iwmmxt_movl_T0_T1_wRn(void)  
53 -{  
54 - T0 = M1 & ~(uint32_t) 0;  
55 - T1 = M1 >> 32;  
56 -}  
57 -  
58 -void OPPROTO op_iwmmxt_movl_wRn_T0_T1(void)  
59 -{  
60 - M1 = ((uint64_t) T1 << 32) | T0;  
61 -}  
62 -  
63 -void OPPROTO op_iwmmxt_movq_M0_wRn(void)  
64 -{  
65 - M0 = M1;  
66 -}  
67 -  
68 -void OPPROTO op_iwmmxt_orq_M0_wRn(void)  
69 -{  
70 - M0 |= M1;  
71 -}  
72 -  
73 -void OPPROTO op_iwmmxt_andq_M0_wRn(void)  
74 -{  
75 - M0 &= M1;  
76 -}  
77 -  
78 -void OPPROTO op_iwmmxt_xorq_M0_wRn(void)  
79 -{  
80 - M0 ^= M1;  
81 -}  
82 -  
83 -void OPPROTO op_iwmmxt_maddsq_M0_wRn(void)  
84 -{  
85 - M0 = ((  
86 - EXTEND16S((M0 >> 0) & 0xffff) * EXTEND16S((M1 >> 0) & 0xffff) +  
87 - EXTEND16S((M0 >> 16) & 0xffff) * EXTEND16S((M1 >> 16) & 0xffff)  
88 - ) & 0xffffffff) | ((uint64_t) (  
89 - EXTEND16S((M0 >> 32) & 0xffff) * EXTEND16S((M1 >> 32) & 0xffff) +  
90 - EXTEND16S((M0 >> 48) & 0xffff) * EXTEND16S((M1 >> 48) & 0xffff)  
91 - ) << 32);  
92 -}  
93 -  
94 -void OPPROTO op_iwmmxt_madduq_M0_wRn(void)  
95 -{  
96 - M0 = ((  
97 - ((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +  
98 - ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)  
99 - ) & 0xffffffff) | ((  
100 - ((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +  
101 - ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)  
102 - ) << 32);  
103 -}  
104 -  
105 -void OPPROTO op_iwmmxt_sadb_M0_wRn(void)  
106 -{  
107 -#define abs(x) (((x) >= 0) ? x : -x)  
108 -#define SADB(SHR) abs((int) ((M0 >> SHR) & 0xff) - (int) ((M1 >> SHR) & 0xff))  
109 - M0 =  
110 - SADB(0) + SADB(8) + SADB(16) + SADB(24) +  
111 - SADB(32) + SADB(40) + SADB(48) + SADB(56);  
112 -#undef SADB  
113 -}  
114 -  
115 -void OPPROTO op_iwmmxt_sadw_M0_wRn(void)  
116 -{  
117 -#define SADW(SHR) \  
118 - abs((int) ((M0 >> SHR) & 0xffff) - (int) ((M1 >> SHR) & 0xffff))  
119 - M0 = SADW(0) + SADW(16) + SADW(32) + SADW(48);  
120 -#undef SADW  
121 -}  
122 -  
123 -void OPPROTO op_iwmmxt_addl_M0_wRn(void)  
124 -{  
125 - M0 += env->iwmmxt.regs[PARAM1] & 0xffffffff;  
126 -}  
127 -  
128 -void OPPROTO op_iwmmxt_mulsw_M0_wRn(void)  
129 -{  
130 -#define MULS(SHR) ((uint64_t) ((( \  
131 - EXTEND16S((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff) \  
132 - ) >> PARAM2) & 0xffff) << SHR)  
133 - M0 = MULS(0) | MULS(16) | MULS(32) | MULS(48);  
134 -#undef MULS  
135 -}  
136 -  
137 -void OPPROTO op_iwmmxt_muluw_M0_wRn(void)  
138 -{  
139 -#define MULU(SHR) ((uint64_t) ((( \  
140 - ((M0 >> SHR) & 0xffff) * ((M1 >> SHR) & 0xffff) \  
141 - ) >> PARAM2) & 0xffff) << SHR)  
142 - M0 = MULU(0) | MULU(16) | MULU(32) | MULU(48);  
143 -#undef MULU  
144 -}  
145 -  
146 -void OPPROTO op_iwmmxt_macsw_M0_wRn(void)  
147 -{  
148 -#define MACS(SHR) ( \  
149 - EXTEND16((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff))  
150 - M0 = (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48));  
151 -#undef MACS  
152 -}  
153 -  
154 -void OPPROTO op_iwmmxt_macuw_M0_wRn(void)  
155 -{  
156 -#define MACU(SHR) ( \  
157 - (uint32_t) ((M0 >> SHR) & 0xffff) * \  
158 - (uint32_t) ((M1 >> SHR) & 0xffff))  
159 - M0 = MACU(0) + MACU(16) + MACU(32) + MACU(48);  
160 -#undef MACU  
161 -}  
162 -  
163 -void OPPROTO op_iwmmxt_addsq_M0_wRn(void)  
164 -{  
165 - M0 = (int64_t) M0 + (int64_t) M1;  
166 -}  
167 -  
168 -void OPPROTO op_iwmmxt_adduq_M0_wRn(void)  
169 -{  
170 - M0 += M1;  
171 -}  
172 -  
173 -void OPPROTO op_iwmmxt_movq_wRn_M0(void)  
174 -{  
175 - M1 = M0;  
176 -}  
177 -  
178 -void OPPROTO op_iwmmxt_movl_wCx_T0(void)  
179 -{  
180 - env->iwmmxt.cregs[PARAM1] = T0;  
181 -}  
182 -  
183 -void OPPROTO op_iwmmxt_movl_T0_wCx(void)  
184 -{  
185 - T0 = env->iwmmxt.cregs[PARAM1];  
186 -}  
187 -  
188 -void OPPROTO op_iwmmxt_movl_T1_wCx(void)  
189 -{  
190 - T1 = env->iwmmxt.cregs[PARAM1];  
191 -}  
192 -  
193 -void OPPROTO op_iwmmxt_set_mup(void)  
194 -{  
195 - env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 2;  
196 -}  
197 -  
198 -void OPPROTO op_iwmmxt_set_cup(void)  
199 -{  
200 - env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 1;  
201 -}  
202 -  
203 -void OPPROTO op_iwmmxt_setpsr_nz(void)  
204 -{  
205 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
206 - SIMD64_SET((M0 == 0), SIMD_ZBIT) |  
207 - SIMD64_SET((M0 & (1ULL << 63)), SIMD_NBIT);  
208 -}  
209 -  
210 -void OPPROTO op_iwmmxt_negq_M0(void)  
211 -{  
212 - M0 = ~M0;  
213 -}  
214 -  
215 -#define NZBIT8(x, i) \  
216 - SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \  
217 - SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)  
218 -#define NZBIT16(x, i) \  
219 - SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \  
220 - SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)  
221 -#define NZBIT32(x, i) \  
222 - SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \  
223 - SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)  
224 -#define NZBIT64(x) \  
225 - SIMD64_SET(NBIT64(x), SIMD_NBIT) | \  
226 - SIMD64_SET(ZBIT64(x), SIMD_ZBIT)  
227 -#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \  
228 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, b_M0_wRn))(void) \  
229 -{ \  
230 - M0 = \  
231 - (((M0 >> SH0) & 0xff) << 0) | (((M1 >> SH0) & 0xff) << 8) | \  
232 - (((M0 >> SH1) & 0xff) << 16) | (((M1 >> SH1) & 0xff) << 24) | \  
233 - (((M0 >> SH2) & 0xff) << 32) | (((M1 >> SH2) & 0xff) << 40) | \  
234 - (((M0 >> SH3) & 0xff) << 48) | (((M1 >> SH3) & 0xff) << 56); \  
235 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
236 - NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \  
237 - NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \  
238 - NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \  
239 - NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \  
240 -} \  
241 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, w_M0_wRn))(void) \  
242 -{ \  
243 - M0 = \  
244 - (((M0 >> SH0) & 0xffff) << 0) | \  
245 - (((M1 >> SH0) & 0xffff) << 16) | \  
246 - (((M0 >> SH2) & 0xffff) << 32) | \  
247 - (((M1 >> SH2) & 0xffff) << 48); \  
248 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
249 - NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 16, 1) | \  
250 - NZBIT8(M0 >> 32, 2) | NZBIT8(M0 >> 48, 3); \  
251 -} \  
252 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, l_M0_wRn))(void) \  
253 -{ \  
254 - M0 = \  
255 - (((M0 >> SH0) & 0xffffffff) << 0) | \  
256 - (((M1 >> SH0) & 0xffffffff) << 32); \  
257 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
258 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \  
259 -} \  
260 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, ub_M0))(void) \  
261 -{ \  
262 - M0 = \  
263 - (((M0 >> SH0) & 0xff) << 0) | \  
264 - (((M0 >> SH1) & 0xff) << 16) | \  
265 - (((M0 >> SH2) & 0xff) << 32) | \  
266 - (((M0 >> SH3) & 0xff) << 48); \  
267 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
268 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \  
269 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \  
270 -} \  
271 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, uw_M0))(void) \  
272 -{ \  
273 - M0 = \  
274 - (((M0 >> SH0) & 0xffff) << 0) | \  
275 - (((M0 >> SH2) & 0xffff) << 32); \  
276 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
277 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \  
278 -} \  
279 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, ul_M0))(void) \  
280 -{ \  
281 - M0 = (((M0 >> SH0) & 0xffffffff) << 0); \  
282 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \  
283 -} \  
284 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, sb_M0))(void) \  
285 -{ \  
286 - M0 = \  
287 - ((uint64_t) EXTEND8H((M0 >> SH0) & 0xff) << 0) | \  
288 - ((uint64_t) EXTEND8H((M0 >> SH1) & 0xff) << 16) | \  
289 - ((uint64_t) EXTEND8H((M0 >> SH2) & 0xff) << 32) | \  
290 - ((uint64_t) EXTEND8H((M0 >> SH3) & 0xff) << 48); \  
291 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
292 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \  
293 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \  
294 -} \  
295 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, sw_M0))(void) \  
296 -{ \  
297 - M0 = \  
298 - ((uint64_t) EXTEND16((M0 >> SH0) & 0xffff) << 0) | \  
299 - ((uint64_t) EXTEND16((M0 >> SH2) & 0xffff) << 32); \  
300 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
301 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \  
302 -} \  
303 -void OPPROTO glue(op_iwmmxt_unpack, glue(S, sl_M0))(void) \  
304 -{ \  
305 - M0 = EXTEND32((M0 >> SH0) & 0xffffffff); \  
306 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \  
307 -}  
308 -IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)  
309 -IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)  
310 -  
311 -#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \  
312 -void OPPROTO glue(op_iwmmxt_, glue(SUFF, b_M0_wRn))(void) \  
313 -{ \  
314 - M0 = \  
315 - CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \  
316 - CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) | \  
317 - CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) | \  
318 - CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff); \  
319 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
320 - NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \  
321 - NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \  
322 - NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \  
323 - NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \  
324 -} \  
325 -void OPPROTO glue(op_iwmmxt_, glue(SUFF, w_M0_wRn))(void) \  
326 -{ \  
327 - M0 = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \  
328 - CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \  
329 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
330 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \  
331 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \  
332 -} \  
333 -void OPPROTO glue(op_iwmmxt_, glue(SUFF, l_M0_wRn))(void) \  
334 -{ \  
335 - M0 = CMP(0, Tl, O, 0xffffffff) | \  
336 - CMP(32, Tl, O, 0xffffffff); \  
337 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \  
338 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \  
339 -}  
340 -#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \  
341 - (TYPE) ((M1 >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)  
342 -IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==)  
343 -IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >)  
344 -IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >)  
345 -#undef CMP  
346 -#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \  
347 - (TYPE) ((M1 >> SHR) & MASK)) ? M0 : M1) & ((uint64_t) MASK << SHR))  
348 -IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <)  
349 -IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <)  
350 -IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >)  
351 -IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >)  
352 -#undef CMP  
353 -#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \  
354 - OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)  
355 -IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -)  
356 -IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +)  
357 -#undef CMP  
358 -/* TODO Signed- and Unsigned-Saturation */  
359 -#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \  
360 - OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)  
361 -IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -)  
362 -IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +)  
363 -IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -)  
364 -IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)  
365 -#undef CMP  
366 -#undef IWMMXT_OP_CMP  
367 -  
368 -void OPPROTO op_iwmmxt_avgb_M0_wRn(void)  
369 -{  
370 -#define AVGB(SHR) ((( \  
371 - ((M0 >> SHR) & 0xff) + ((M1 >> SHR) & 0xff) + PARAM2) >> 1) << SHR)  
372 - M0 =  
373 - AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) |  
374 - AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56);  
375 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
376 - SIMD8_SET(ZBIT8((M0 >> 0) & 0xff), SIMD_ZBIT, 0) |  
377 - SIMD8_SET(ZBIT8((M0 >> 8) & 0xff), SIMD_ZBIT, 1) |  
378 - SIMD8_SET(ZBIT8((M0 >> 16) & 0xff), SIMD_ZBIT, 2) |  
379 - SIMD8_SET(ZBIT8((M0 >> 24) & 0xff), SIMD_ZBIT, 3) |  
380 - SIMD8_SET(ZBIT8((M0 >> 32) & 0xff), SIMD_ZBIT, 4) |  
381 - SIMD8_SET(ZBIT8((M0 >> 40) & 0xff), SIMD_ZBIT, 5) |  
382 - SIMD8_SET(ZBIT8((M0 >> 48) & 0xff), SIMD_ZBIT, 6) |  
383 - SIMD8_SET(ZBIT8((M0 >> 56) & 0xff), SIMD_ZBIT, 7);  
384 -#undef AVGB  
385 -}  
386 -  
387 -void OPPROTO op_iwmmxt_avgw_M0_wRn(void)  
388 -{  
389 -#define AVGW(SHR) ((( \  
390 - ((M0 >> SHR) & 0xffff) + ((M1 >> SHR) & 0xffff) + PARAM2) >> 1) << SHR)  
391 - M0 = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48);  
392 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
393 - SIMD16_SET(ZBIT16((M0 >> 0) & 0xffff), SIMD_ZBIT, 0) |  
394 - SIMD16_SET(ZBIT16((M0 >> 16) & 0xffff), SIMD_ZBIT, 1) |  
395 - SIMD16_SET(ZBIT16((M0 >> 32) & 0xffff), SIMD_ZBIT, 2) |  
396 - SIMD16_SET(ZBIT16((M0 >> 48) & 0xffff), SIMD_ZBIT, 3);  
397 -#undef AVGW  
398 -}  
399 -  
400 -void OPPROTO op_iwmmxt_msadb_M0_wRn(void)  
401 -{  
402 - M0 = ((((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +  
403 - ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)) & 0xffffffff) |  
404 - ((((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +  
405 - ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)) << 32);  
406 -}  
407 -  
408 -void OPPROTO op_iwmmxt_align_M0_T0_wRn(void)  
409 -{  
410 - M0 >>= T0 << 3;  
411 - M0 |= M1 << (64 - (T0 << 3));  
412 -}  
413 -  
414 -void OPPROTO op_iwmmxt_insr_M0_T0_T1(void)  
415 -{  
416 - M0 &= ~((uint64_t) T1 << PARAM1);  
417 - M0 |= (uint64_t) (T0 & T1) << PARAM1;  
418 -}  
419 -  
420 -void OPPROTO op_iwmmxt_extrsb_T0_M0(void)  
421 -{  
422 - T0 = EXTEND8((M0 >> PARAM1) & 0xff);  
423 -}  
424 -  
425 -void OPPROTO op_iwmmxt_extrsw_T0_M0(void)  
426 -{  
427 - T0 = EXTEND16((M0 >> PARAM1) & 0xffff);  
428 -}  
429 -  
430 -void OPPROTO op_iwmmxt_extru_T0_M0_T1(void)  
431 -{  
432 - T0 = (M0 >> PARAM1) & T1;  
433 -}  
434 -  
435 -void OPPROTO op_iwmmxt_bcstb_M0_T0(void)  
436 -{  
437 - T0 &= 0xff;  
438 - M0 =  
439 - ((uint64_t) T0 << 0) | ((uint64_t) T0 << 8) |  
440 - ((uint64_t) T0 << 16) | ((uint64_t) T0 << 24) |  
441 - ((uint64_t) T0 << 32) | ((uint64_t) T0 << 40) |  
442 - ((uint64_t) T0 << 48) | ((uint64_t) T0 << 56);  
443 -}  
444 -  
445 -void OPPROTO op_iwmmxt_bcstw_M0_T0(void)  
446 -{  
447 - T0 &= 0xffff;  
448 - M0 =  
449 - ((uint64_t) T0 << 0) | ((uint64_t) T0 << 16) |  
450 - ((uint64_t) T0 << 32) | ((uint64_t) T0 << 48);  
451 -}  
452 -  
453 -void OPPROTO op_iwmmxt_bcstl_M0_T0(void)  
454 -{  
455 - M0 = ((uint64_t) T0 << 0) | ((uint64_t) T0 << 32);  
456 -}  
457 -  
458 -void OPPROTO op_iwmmxt_addcb_M0(void)  
459 -{  
460 - M0 =  
461 - ((M0 >> 0) & 0xff) + ((M0 >> 8) & 0xff) +  
462 - ((M0 >> 16) & 0xff) + ((M0 >> 24) & 0xff) +  
463 - ((M0 >> 32) & 0xff) + ((M0 >> 40) & 0xff) +  
464 - ((M0 >> 48) & 0xff) + ((M0 >> 56) & 0xff);  
465 -}  
466 -  
467 -void OPPROTO op_iwmmxt_addcw_M0(void)  
468 -{  
469 - M0 =  
470 - ((M0 >> 0) & 0xffff) + ((M0 >> 16) & 0xffff) +  
471 - ((M0 >> 32) & 0xffff) + ((M0 >> 48) & 0xffff);  
472 -}  
473 -  
474 -void OPPROTO op_iwmmxt_addcl_M0(void)  
475 -{  
476 - M0 = (M0 & 0xffffffff) + (M0 >> 32);  
477 -}  
478 -  
479 -void OPPROTO op_iwmmxt_msbb_T0_M0(void)  
480 -{  
481 - T0 =  
482 - ((M0 >> 7) & 0x01) | ((M0 >> 14) & 0x02) |  
483 - ((M0 >> 21) & 0x04) | ((M0 >> 28) & 0x08) |  
484 - ((M0 >> 35) & 0x10) | ((M0 >> 42) & 0x20) |  
485 - ((M0 >> 49) & 0x40) | ((M0 >> 56) & 0x80);  
486 -}  
487 -  
488 -void OPPROTO op_iwmmxt_msbw_T0_M0(void)  
489 -{  
490 - T0 =  
491 - ((M0 >> 15) & 0x01) | ((M0 >> 30) & 0x02) |  
492 - ((M0 >> 45) & 0x04) | ((M0 >> 52) & 0x08);  
493 -}  
494 -  
495 -void OPPROTO op_iwmmxt_msbl_T0_M0(void)  
496 -{  
497 - T0 = ((M0 >> 31) & 0x01) | ((M0 >> 62) & 0x02);  
498 -}  
499 -  
500 -void OPPROTO op_iwmmxt_srlw_M0_T0(void)  
501 -{  
502 - M0 =  
503 - (((M0 & (0xffffll << 0)) >> T0) & (0xffffll << 0)) |  
504 - (((M0 & (0xffffll << 16)) >> T0) & (0xffffll << 16)) |  
505 - (((M0 & (0xffffll << 32)) >> T0) & (0xffffll << 32)) |  
506 - (((M0 & (0xffffll << 48)) >> T0) & (0xffffll << 48));  
507 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
508 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |  
509 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);  
510 -}  
511 -  
512 -void OPPROTO op_iwmmxt_srll_M0_T0(void)  
513 -{  
514 - M0 =  
515 - ((M0 & (0xffffffffll << 0)) >> T0) |  
516 - ((M0 >> T0) & (0xffffffffll << 32));  
517 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
518 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);  
519 -}  
520 -  
521 -void OPPROTO op_iwmmxt_srlq_M0_T0(void)  
522 -{  
523 - M0 >>= T0;  
524 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);  
525 -}  
526 -  
527 -void OPPROTO op_iwmmxt_sllw_M0_T0(void)  
528 -{  
529 - M0 =  
530 - (((M0 & (0xffffll << 0)) << T0) & (0xffffll << 0)) |  
531 - (((M0 & (0xffffll << 16)) << T0) & (0xffffll << 16)) |  
532 - (((M0 & (0xffffll << 32)) << T0) & (0xffffll << 32)) |  
533 - (((M0 & (0xffffll << 48)) << T0) & (0xffffll << 48));  
534 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
535 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |  
536 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);  
537 -}  
538 -  
539 -void OPPROTO op_iwmmxt_slll_M0_T0(void)  
540 -{  
541 - M0 =  
542 - ((M0 << T0) & (0xffffffffll << 0)) |  
543 - ((M0 & (0xffffffffll << 32)) << T0);  
544 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
545 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);  
546 -}  
547 -  
548 -void OPPROTO op_iwmmxt_sllq_M0_T0(void)  
549 -{  
550 - M0 <<= T0;  
551 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);  
552 -}  
553 -  
554 -void OPPROTO op_iwmmxt_sraw_M0_T0(void)  
555 -{  
556 - M0 =  
557 - ((uint64_t) ((EXTEND16(M0 >> 0) >> T0) & 0xffff) << 0) |  
558 - ((uint64_t) ((EXTEND16(M0 >> 16) >> T0) & 0xffff) << 16) |  
559 - ((uint64_t) ((EXTEND16(M0 >> 32) >> T0) & 0xffff) << 32) |  
560 - ((uint64_t) ((EXTEND16(M0 >> 48) >> T0) & 0xffff) << 48);  
561 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
562 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |  
563 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);  
564 -}  
565 -  
566 -void OPPROTO op_iwmmxt_sral_M0_T0(void)  
567 -{  
568 - M0 =  
569 - (((EXTEND32(M0 >> 0) >> T0) & 0xffffffff) << 0) |  
570 - (((EXTEND32(M0 >> 32) >> T0) & 0xffffffff) << 32);  
571 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
572 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);  
573 -}  
574 -  
575 -void OPPROTO op_iwmmxt_sraq_M0_T0(void)  
576 -{  
577 - M0 = (int64_t) M0 >> T0;  
578 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);  
579 -}  
580 -  
581 -void OPPROTO op_iwmmxt_rorw_M0_T0(void)  
582 -{  
583 - M0 =  
584 - ((((M0 & (0xffffll << 0)) >> T0) |  
585 - ((M0 & (0xffffll << 0)) << (16 - T0))) & (0xffffll << 0)) |  
586 - ((((M0 & (0xffffll << 16)) >> T0) |  
587 - ((M0 & (0xffffll << 16)) << (16 - T0))) & (0xffffll << 16)) |  
588 - ((((M0 & (0xffffll << 32)) >> T0) |  
589 - ((M0 & (0xffffll << 32)) << (16 - T0))) & (0xffffll << 32)) |  
590 - ((((M0 & (0xffffll << 48)) >> T0) |  
591 - ((M0 & (0xffffll << 48)) << (16 - T0))) & (0xffffll << 48));  
592 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
593 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |  
594 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);  
595 -}  
596 -  
597 -void OPPROTO op_iwmmxt_rorl_M0_T0(void)  
598 -{  
599 - M0 =  
600 - ((M0 & (0xffffffffll << 0)) >> T0) |  
601 - ((M0 >> T0) & (0xffffffffll << 32)) |  
602 - ((M0 << (32 - T0)) & (0xffffffffll << 0)) |  
603 - ((M0 & (0xffffffffll << 32)) << (32 - T0));  
604 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
605 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);  
606 -}  
607 -  
608 -void OPPROTO op_iwmmxt_rorq_M0_T0(void)  
609 -{  
610 - M0 = (M0 >> T0) | (M0 << (64 - T0));  
611 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);  
612 -}  
613 -  
614 -void OPPROTO op_iwmmxt_shufh_M0_T0(void)  
615 -{  
616 - M0 =  
617 - (((M0 >> ((T0 << 4) & 0x30)) & 0xffff) << 0) |  
618 - (((M0 >> ((T0 << 2) & 0x30)) & 0xffff) << 16) |  
619 - (((M0 >> ((T0 << 0) & 0x30)) & 0xffff) << 32) |  
620 - (((M0 >> ((T0 >> 2) & 0x30)) & 0xffff) << 48);  
621 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
622 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |  
623 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);  
624 -}  
625 -  
626 -/* TODO: Unsigned-Saturation */  
627 -void OPPROTO op_iwmmxt_packuw_M0_wRn(void)  
628 -{  
629 - M0 =  
630 - (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |  
631 - (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |  
632 - (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |  
633 - (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);  
634 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
635 - NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |  
636 - NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |  
637 - NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |  
638 - NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);  
639 -}  
640 -  
641 -void OPPROTO op_iwmmxt_packul_M0_wRn(void)  
642 -{  
643 - M0 =  
644 - (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |  
645 - (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);  
646 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
647 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |  
648 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);  
649 -}  
650 -  
651 -void OPPROTO op_iwmmxt_packuq_M0_wRn(void)  
652 -{  
653 - M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);  
654 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
655 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);  
656 -}  
657 -  
658 -/* TODO: Signed-Saturation */  
659 -void OPPROTO op_iwmmxt_packsw_M0_wRn(void)  
660 -{  
661 - M0 =  
662 - (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |  
663 - (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |  
664 - (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |  
665 - (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);  
666 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
667 - NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |  
668 - NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |  
669 - NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |  
670 - NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);  
671 -}  
672 -  
673 -void OPPROTO op_iwmmxt_packsl_M0_wRn(void)  
674 -{  
675 - M0 =  
676 - (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |  
677 - (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);  
678 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
679 - NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |  
680 - NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);  
681 -}  
682 -  
683 -void OPPROTO op_iwmmxt_packsq_M0_wRn(void)  
684 -{  
685 - M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);  
686 - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =  
687 - NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);  
688 -}  
689 -  
690 -void OPPROTO op_iwmmxt_muladdsl_M0_T0_T1(void)  
691 -{  
692 - M0 += (int32_t) EXTEND32(T0) * (int32_t) EXTEND32(T1);  
693 -}  
694 -  
695 -void OPPROTO op_iwmmxt_muladdsw_M0_T0_T1(void)  
696 -{  
697 - M0 += EXTEND32(EXTEND16S((T0 >> 0) & 0xffff) *  
698 - EXTEND16S((T1 >> 0) & 0xffff));  
699 - M0 += EXTEND32(EXTEND16S((T0 >> 16) & 0xffff) *  
700 - EXTEND16S((T1 >> 16) & 0xffff));  
701 -}  
702 -  
703 -void OPPROTO op_iwmmxt_muladdswl_M0_T0_T1(void)  
704 -{  
705 - M0 += EXTEND32(EXTEND16S(T0 & 0xffff) *  
706 - EXTEND16S(T1 & 0xffff));  
707 -}  
target-arm/op_mem.h deleted 100644 → 0
  View file @ad69471
1 -/* ARM memory operations. */  
2 -  
3 -/* iwMMXt load/store. Address is in T1 */  
4 -#define MMX_MEM_OP(name, ldname) \  
5 -void OPPROTO glue(op_iwmmxt_ld##name,MEMSUFFIX)(void) \  
6 -{ \  
7 - M0 = glue(ld##ldname,MEMSUFFIX)(T1); \  
8 - FORCE_RET(); \  
9 -} \  
10 -void OPPROTO glue(op_iwmmxt_st##name,MEMSUFFIX)(void) \  
11 -{ \  
12 - glue(st##name,MEMSUFFIX)(T1, M0); \  
13 - FORCE_RET(); \  
14 -}  
15 -  
16 -MMX_MEM_OP(b, ub)  
17 -MMX_MEM_OP(w, uw)  
18 -MMX_MEM_OP(l, l)  
19 -MMX_MEM_OP(q, q)  
20 -  
21 -#undef MMX_MEM_OP  
22 -  
23 -#undef MEMSUFFIX  
target-arm/translate.c
  View file @e677137
@@ -78,7 +78,7 @@ extern int loglevel; @@ -78,7 +78,7 @@ extern int loglevel;
78 78
79 static TCGv cpu_env; 79 static TCGv cpu_env;
80 /* We reuse the same 64-bit temporaries for efficiency. */ 80 /* We reuse the same 64-bit temporaries for efficiency. */
81 -static TCGv cpu_V0, cpu_V1; 81 +static TCGv cpu_V0, cpu_V1, cpu_M0;
82 82
83 /* FIXME: These should be removed. */ 83 /* FIXME: These should be removed. */
84 static TCGv cpu_T[2]; 84 static TCGv cpu_T[2];
@@ -456,6 +456,12 @@ static inline void tcg_gen_not_i32(TCGv t0, TCGv t1) @@ -456,6 +456,12 @@ static inline void tcg_gen_not_i32(TCGv t0, TCGv t1)
456 tcg_gen_xori_i32(t0, t1, ~0); 456 tcg_gen_xori_i32(t0, t1, ~0);
457 } 457 }
458 458
  459 +/* FIXME: Implement this natively. */
  460 +static inline void tcg_gen_neg_i64(TCGv dest, TCGv src)
  461 +{
  462 + tcg_gen_sub_i64(dest, tcg_const_i64(0), src);
  463 +}
  464 +
459 /* T0 &= ~T1. Clobbers T1. */ 465 /* T0 &= ~T1. Clobbers T1. */
460 /* FIXME: Implement bic natively. */ 466 /* FIXME: Implement bic natively. */
461 static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1) 467 static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1)
@@ -1234,6 +1240,238 @@ static inline void gen_mov_vreg_F0(int dp, int reg) @@ -1234,6 +1240,238 @@ static inline void gen_mov_vreg_F0(int dp, int reg)
1234 1240
1235 #define ARM_CP_RW_BIT (1 << 20) 1241 #define ARM_CP_RW_BIT (1 << 20)
1236 1242
  1243 +static inline void iwmmxt_load_reg(TCGv var, int reg)
  1244 +{
  1245 + tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
  1246 +}
  1247 +
  1248 +static inline void iwmmxt_store_reg(TCGv var, int reg)
  1249 +{
  1250 + tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
  1251 +}
  1252 +
  1253 +static inline void gen_op_iwmmxt_movl_wCx_T0(int reg)
  1254 +{
  1255 + tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
  1256 +}
  1257 +
  1258 +static inline void gen_op_iwmmxt_movl_T0_wCx(int reg)
  1259 +{
  1260 + tcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
  1261 +}
  1262 +
  1263 +static inline void gen_op_iwmmxt_movl_T1_wCx(int reg)
  1264 +{
  1265 + tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
  1266 +}
  1267 +
  1268 +static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
  1269 +{
  1270 + iwmmxt_store_reg(cpu_M0, rn);
  1271 +}
  1272 +
  1273 +static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
  1274 +{
  1275 + iwmmxt_load_reg(cpu_M0, rn);
  1276 +}
  1277 +
  1278 +static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
  1279 +{
  1280 + iwmmxt_load_reg(cpu_V1, rn);
  1281 + tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
  1282 +}
  1283 +
  1284 +static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
  1285 +{
  1286 + iwmmxt_load_reg(cpu_V1, rn);
  1287 + tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
  1288 +}
  1289 +
  1290 +static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
  1291 +{
  1292 + iwmmxt_load_reg(cpu_V1, rn);
  1293 + tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
  1294 +}
  1295 +
  1296 +#define IWMMXT_OP(name) \
  1297 +static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
  1298 +{ \
  1299 + iwmmxt_load_reg(cpu_V1, rn); \
  1300 + gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
  1301 +}
  1302 +
  1303 +#define IWMMXT_OP_ENV(name) \
  1304 +static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
  1305 +{ \
  1306 + iwmmxt_load_reg(cpu_V1, rn); \
  1307 + gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
  1308 +}
  1309 +
  1310 +#define IWMMXT_OP_ENV_SIZE(name) \
  1311 +IWMMXT_OP_ENV(name##b) \
  1312 +IWMMXT_OP_ENV(name##w) \
  1313 +IWMMXT_OP_ENV(name##l)
  1314 +
  1315 +#define IWMMXT_OP_ENV1(name) \
  1316 +static inline void gen_op_iwmmxt_##name##_M0(void) \
  1317 +{ \
  1318 + gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
  1319 +}
  1320 +
  1321 +IWMMXT_OP(maddsq)
  1322 +IWMMXT_OP(madduq)
  1323 +IWMMXT_OP(sadb)
  1324 +IWMMXT_OP(sadw)
  1325 +IWMMXT_OP(mulslw)
  1326 +IWMMXT_OP(mulshw)
  1327 +IWMMXT_OP(mululw)
  1328 +IWMMXT_OP(muluhw)
  1329 +IWMMXT_OP(macsw)
  1330 +IWMMXT_OP(macuw)
  1331 +
  1332 +IWMMXT_OP_ENV_SIZE(unpackl)
  1333 +IWMMXT_OP_ENV_SIZE(unpackh)
  1334 +
  1335 +IWMMXT_OP_ENV1(unpacklub)
  1336 +IWMMXT_OP_ENV1(unpackluw)
  1337 +IWMMXT_OP_ENV1(unpacklul)
  1338 +IWMMXT_OP_ENV1(unpackhub)
  1339 +IWMMXT_OP_ENV1(unpackhuw)
  1340 +IWMMXT_OP_ENV1(unpackhul)
  1341 +IWMMXT_OP_ENV1(unpacklsb)
  1342 +IWMMXT_OP_ENV1(unpacklsw)
  1343 +IWMMXT_OP_ENV1(unpacklsl)
  1344 +IWMMXT_OP_ENV1(unpackhsb)
  1345 +IWMMXT_OP_ENV1(unpackhsw)
  1346 +IWMMXT_OP_ENV1(unpackhsl)
  1347 +
  1348 +IWMMXT_OP_ENV_SIZE(cmpeq)
  1349 +IWMMXT_OP_ENV_SIZE(cmpgtu)
  1350 +IWMMXT_OP_ENV_SIZE(cmpgts)
  1351 +
  1352 +IWMMXT_OP_ENV_SIZE(mins)
  1353 +IWMMXT_OP_ENV_SIZE(minu)
  1354 +IWMMXT_OP_ENV_SIZE(maxs)
  1355 +IWMMXT_OP_ENV_SIZE(maxu)
  1356 +
  1357 +IWMMXT_OP_ENV_SIZE(subn)
  1358 +IWMMXT_OP_ENV_SIZE(addn)
  1359 +IWMMXT_OP_ENV_SIZE(subu)
  1360 +IWMMXT_OP_ENV_SIZE(addu)
  1361 +IWMMXT_OP_ENV_SIZE(subs)
  1362 +IWMMXT_OP_ENV_SIZE(adds)
  1363 +
  1364 +IWMMXT_OP_ENV(avgb0)
  1365 +IWMMXT_OP_ENV(avgb1)
  1366 +IWMMXT_OP_ENV(avgw0)
  1367 +IWMMXT_OP_ENV(avgw1)
  1368 +
  1369 +IWMMXT_OP(msadb)
  1370 +
  1371 +IWMMXT_OP_ENV(packuw)
  1372 +IWMMXT_OP_ENV(packul)
  1373 +IWMMXT_OP_ENV(packuq)
  1374 +IWMMXT_OP_ENV(packsw)
  1375 +IWMMXT_OP_ENV(packsl)
  1376 +IWMMXT_OP_ENV(packsq)
  1377 +
  1378 +static inline void gen_op_iwmmxt_muladdsl_M0_T0_T1(void)
  1379 +{
  1380 + gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
  1381 +}
  1382 +
  1383 +static inline void gen_op_iwmmxt_muladdsw_M0_T0_T1(void)
  1384 +{
  1385 + gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
  1386 +}
  1387 +
  1388 +static inline void gen_op_iwmmxt_muladdswl_M0_T0_T1(void)
  1389 +{
  1390 + gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
  1391 +}
  1392 +
  1393 +static inline void gen_op_iwmmxt_align_M0_T0_wRn(int rn)
  1394 +{
  1395 + iwmmxt_load_reg(cpu_V1, rn);
  1396 + gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, cpu_T[0]);
  1397 +}
  1398 +
  1399 +static inline void gen_op_iwmmxt_insr_M0_T0_T1(int shift)
  1400 +{
  1401 + TCGv tmp = tcg_const_i32(shift);
  1402 + gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1], tmp);
  1403 +}
  1404 +
  1405 +static inline void gen_op_iwmmxt_extrsb_T0_M0(int shift)
  1406 +{
  1407 + tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
  1408 + tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
  1409 + tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
  1410 +}
  1411 +
  1412 +static inline void gen_op_iwmmxt_extrsw_T0_M0(int shift)
  1413 +{
  1414 + tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
  1415 + tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
  1416 + tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
  1417 +}
  1418 +
  1419 +static inline void gen_op_iwmmxt_extru_T0_M0(int shift, uint32_t mask)
  1420 +{
  1421 + tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
  1422 + tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
  1423 + if (mask != ~0u)
  1424 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask);
  1425 +}
  1426 +
  1427 +static void gen_op_iwmmxt_set_mup(void)
  1428 +{
  1429 + TCGv tmp;
  1430 + tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
  1431 + tcg_gen_ori_i32(tmp, tmp, 2);
  1432 + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
  1433 +}
  1434 +
  1435 +static void gen_op_iwmmxt_set_cup(void)
  1436 +{
  1437 + TCGv tmp;
  1438 + tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
  1439 + tcg_gen_ori_i32(tmp, tmp, 1);
  1440 + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
  1441 +}
  1442 +
  1443 +static void gen_op_iwmmxt_setpsr_nz(void)
  1444 +{
  1445 + TCGv tmp = new_tmp();
  1446 + gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
  1447 + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
  1448 +}
  1449 +
  1450 +static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
  1451 +{
  1452 + iwmmxt_load_reg(cpu_V1, rn);
  1453 + tcg_gen_andi_i64(cpu_V1, cpu_V1, 0xffffffffu);
  1454 + tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
  1455 +}
  1456 +
  1457 +
  1458 +static void gen_iwmmxt_movl_T0_T1_wRn(int rn)
  1459 +{
  1460 + iwmmxt_load_reg(cpu_V0, rn);
  1461 + tcg_gen_trunc_i64_i32(cpu_T[0], cpu_V0);
  1462 + tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
  1463 + tcg_gen_trunc_i64_i32(cpu_T[1], cpu_V0);
  1464 +}
  1465 +
  1466 +static void gen_iwmmxt_movl_wRn_T0_T1(int rn)
  1467 +{
  1468 + tcg_gen_extu_i32_i64(cpu_V0, cpu_T[0]);
  1469 + tcg_gen_extu_i32_i64(cpu_V1, cpu_T[0]);
  1470 + tcg_gen_shli_i64(cpu_V1, cpu_V1, 32);
  1471 + tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
  1472 + iwmmxt_store_reg(cpu_V0, rn);
  1473 +}
  1474 +
1237 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn) 1475 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn)
1238 { 1476 {
1239 int rd; 1477 int rd;
@@ -1275,7 +1513,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask) @@ -1275,7 +1513,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask)
1275 else 1513 else
1276 gen_op_iwmmxt_movl_T0_wCx(rd); 1514 gen_op_iwmmxt_movl_T0_wCx(rd);
1277 else 1515 else
1278 - gen_op_iwmmxt_movl_T0_T1_wRn(rd); 1516 + gen_iwmmxt_movl_T0_T1_wRn(rd);
1279 1517
1280 gen_op_movl_T1_im(mask); 1518 gen_op_movl_T1_im(mask);
1281 gen_op_andl_T0_T1(); 1519 gen_op_andl_T0_T1();
@@ -1296,13 +1534,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1296,13 +1534,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1296 rdlo = (insn >> 12) & 0xf; 1534 rdlo = (insn >> 12) & 0xf;
1297 rdhi = (insn >> 16) & 0xf; 1535 rdhi = (insn >> 16) & 0xf;
1298 if (insn & ARM_CP_RW_BIT) { /* TMRRC */ 1536 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1299 - gen_op_iwmmxt_movl_T0_T1_wRn(wrd); 1537 + gen_iwmmxt_movl_T0_T1_wRn(wrd);
1300 gen_movl_reg_T0(s, rdlo); 1538 gen_movl_reg_T0(s, rdlo);
1301 gen_movl_reg_T1(s, rdhi); 1539 gen_movl_reg_T1(s, rdhi);
1302 } else { /* TMCRR */ 1540 } else { /* TMCRR */
1303 gen_movl_T0_reg(s, rdlo); 1541 gen_movl_T0_reg(s, rdlo);
1304 gen_movl_T1_reg(s, rdhi); 1542 gen_movl_T1_reg(s, rdhi);
1305 - gen_op_iwmmxt_movl_wRn_T0_T1(wrd); 1543 + gen_iwmmxt_movl_wRn_T0_T1(wrd);
1306 gen_op_iwmmxt_set_mup(); 1544 gen_op_iwmmxt_set_mup();
1307 } 1545 }
1308 return 0; 1546 return 0;
@@ -1318,16 +1556,25 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1318,16 +1556,25 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1318 dead_tmp(tmp); 1556 dead_tmp(tmp);
1319 gen_op_iwmmxt_movl_wCx_T0(wrd); 1557 gen_op_iwmmxt_movl_wCx_T0(wrd);
1320 } else { 1558 } else {
1321 - if (insn & (1 << 8))  
1322 - if (insn & (1 << 22)) /* WLDRD */  
1323 - gen_ldst(iwmmxt_ldq, s);  
1324 - else /* WLDRW wRd */  
1325 - gen_ldst(iwmmxt_ldl, s);  
1326 - else  
1327 - if (insn & (1 << 22)) /* WLDRH */  
1328 - gen_ldst(iwmmxt_ldw, s);  
1329 - else /* WLDRB */  
1330 - gen_ldst(iwmmxt_ldb, s); 1559 + i = 1;
  1560 + if (insn & (1 << 8)) {
  1561 + if (insn & (1 << 22)) { /* WLDRD */
  1562 + tcg_gen_qemu_ld64(cpu_M0, cpu_T[1], IS_USER(s));
  1563 + i = 0;
  1564 + } else { /* WLDRW wRd */
  1565 + tmp = gen_ld32(cpu_T[1], IS_USER(s));
  1566 + }
  1567 + } else {
  1568 + if (insn & (1 << 22)) { /* WLDRH */
  1569 + tmp = gen_ld16u(cpu_T[1], IS_USER(s));
  1570 + } else { /* WLDRB */
  1571 + tmp = gen_ld8u(cpu_T[1], IS_USER(s));
  1572 + }
  1573 + }
  1574 + if (i) {
  1575 + tcg_gen_extu_i32_i64(cpu_M0, tmp);
  1576 + dead_tmp(tmp);
  1577 + }
1331 gen_op_iwmmxt_movq_wRn_M0(wrd); 1578 gen_op_iwmmxt_movq_wRn_M0(wrd);
1332 } 1579 }
1333 } else { 1580 } else {
@@ -1338,16 +1585,24 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1338,16 +1585,24 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1338 gen_st32(tmp, cpu_T[1], IS_USER(s)); 1585 gen_st32(tmp, cpu_T[1], IS_USER(s));
1339 } else { 1586 } else {
1340 gen_op_iwmmxt_movq_M0_wRn(wrd); 1587 gen_op_iwmmxt_movq_M0_wRn(wrd);
1341 - if (insn & (1 << 8))  
1342 - if (insn & (1 << 22)) /* WSTRD */  
1343 - gen_ldst(iwmmxt_stq, s);  
1344 - else /* WSTRW wRd */  
1345 - gen_ldst(iwmmxt_stl, s);  
1346 - else  
1347 - if (insn & (1 << 22)) /* WSTRH */  
1348 - gen_ldst(iwmmxt_ldw, s);  
1349 - else /* WSTRB */  
1350 - gen_ldst(iwmmxt_stb, s); 1588 + tmp = new_tmp();
  1589 + if (insn & (1 << 8)) {
  1590 + if (insn & (1 << 22)) { /* WSTRD */
  1591 + dead_tmp(tmp);
  1592 + tcg_gen_qemu_st64(cpu_M0, cpu_T[1], IS_USER(s));
  1593 + } else { /* WSTRW wRd */
  1594 + tcg_gen_trunc_i64_i32(tmp, cpu_M0);
  1595 + gen_st32(tmp, cpu_T[1], IS_USER(s));
  1596 + }
  1597 + } else {
  1598 + if (insn & (1 << 22)) { /* WSTRH */
  1599 + tcg_gen_trunc_i64_i32(tmp, cpu_M0);
  1600 + gen_st16(tmp, cpu_T[1], IS_USER(s));
  1601 + } else { /* WSTRB */
  1602 + tcg_gen_trunc_i64_i32(tmp, cpu_M0);
  1603 + gen_st8(tmp, cpu_T[1], IS_USER(s));
  1604 + }
  1605 + }
1351 } 1606 }
1352 } 1607 }
1353 return 0; 1608 return 0;
@@ -1422,7 +1677,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1422,7 +1677,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1422 rd0 = (insn >> 0) & 0xf; 1677 rd0 = (insn >> 0) & 0xf;
1423 rd1 = (insn >> 16) & 0xf; 1678 rd1 = (insn >> 16) & 0xf;
1424 gen_op_iwmmxt_movq_M0_wRn(rd0); 1679 gen_op_iwmmxt_movq_M0_wRn(rd0);
1425 - gen_op_iwmmxt_negq_M0(); 1680 + tcg_gen_neg_i64(cpu_M0, cpu_M0);
1426 gen_op_iwmmxt_andq_M0_wRn(rd1); 1681 gen_op_iwmmxt_andq_M0_wRn(rd1);
1427 gen_op_iwmmxt_setpsr_nz(); 1682 gen_op_iwmmxt_setpsr_nz();
1428 gen_op_iwmmxt_movq_wRn_M0(wrd); 1683 gen_op_iwmmxt_movq_wRn_M0(wrd);
@@ -1515,10 +1770,17 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1515,10 +1770,17 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1515 rd0 = (insn >> 16) & 0xf; 1770 rd0 = (insn >> 16) & 0xf;
1516 rd1 = (insn >> 0) & 0xf; 1771 rd1 = (insn >> 0) & 0xf;
1517 gen_op_iwmmxt_movq_M0_wRn(rd0); 1772 gen_op_iwmmxt_movq_M0_wRn(rd0);
1518 - if (insn & (1 << 21))  
1519 - gen_op_iwmmxt_mulsw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0);  
1520 - else  
1521 - gen_op_iwmmxt_muluw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0); 1773 + if (insn & (1 << 21)) {
  1774 + if (insn & (1 << 20))
  1775 + gen_op_iwmmxt_mulshw_M0_wRn(rd1);
  1776 + else
  1777 + gen_op_iwmmxt_mulslw_M0_wRn(rd1);
  1778 + } else {
  1779 + if (insn & (1 << 20))
  1780 + gen_op_iwmmxt_muluhw_M0_wRn(rd1);
  1781 + else
  1782 + gen_op_iwmmxt_mululw_M0_wRn(rd1);
  1783 + }
1522 gen_op_iwmmxt_movq_wRn_M0(wrd); 1784 gen_op_iwmmxt_movq_wRn_M0(wrd);
1523 gen_op_iwmmxt_set_mup(); 1785 gen_op_iwmmxt_set_mup();
1524 break; 1786 break;
@@ -1532,10 +1794,8 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1532,10 +1794,8 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1532 else 1794 else
1533 gen_op_iwmmxt_macuw_M0_wRn(rd1); 1795 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1534 if (!(insn & (1 << 20))) { 1796 if (!(insn & (1 << 20))) {
1535 - if (insn & (1 << 21))  
1536 - gen_op_iwmmxt_addsq_M0_wRn(wrd);  
1537 - else  
1538 - gen_op_iwmmxt_adduq_M0_wRn(wrd); 1797 + iwmmxt_load_reg(cpu_V1, wrd);
  1798 + tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1539 } 1799 }
1540 gen_op_iwmmxt_movq_wRn_M0(wrd); 1800 gen_op_iwmmxt_movq_wRn_M0(wrd);
1541 gen_op_iwmmxt_set_mup(); 1801 gen_op_iwmmxt_set_mup();
@@ -1567,10 +1827,17 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1567,10 +1827,17 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1567 rd0 = (insn >> 16) & 0xf; 1827 rd0 = (insn >> 16) & 0xf;
1568 rd1 = (insn >> 0) & 0xf; 1828 rd1 = (insn >> 0) & 0xf;
1569 gen_op_iwmmxt_movq_M0_wRn(rd0); 1829 gen_op_iwmmxt_movq_M0_wRn(rd0);
1570 - if (insn & (1 << 22))  
1571 - gen_op_iwmmxt_avgw_M0_wRn(rd1, (insn >> 20) & 1);  
1572 - else  
1573 - gen_op_iwmmxt_avgb_M0_wRn(rd1, (insn >> 20) & 1); 1830 + if (insn & (1 << 22)) {
  1831 + if (insn & (1 << 20))
  1832 + gen_op_iwmmxt_avgw1_M0_wRn(rd1);
  1833 + else
  1834 + gen_op_iwmmxt_avgw0_M0_wRn(rd1);
  1835 + } else {
  1836 + if (insn & (1 << 20))
  1837 + gen_op_iwmmxt_avgb1_M0_wRn(rd1);
  1838 + else
  1839 + gen_op_iwmmxt_avgb0_M0_wRn(rd1);
  1840 + }
1574 gen_op_iwmmxt_movq_wRn_M0(wrd); 1841 gen_op_iwmmxt_movq_wRn_M0(wrd);
1575 gen_op_iwmmxt_set_mup(); 1842 gen_op_iwmmxt_set_mup();
1576 gen_op_iwmmxt_set_cup(); 1843 gen_op_iwmmxt_set_cup();
@@ -1622,21 +1889,18 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1622,21 +1889,18 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1622 if (insn & 8) 1889 if (insn & 8)
1623 gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3); 1890 gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3);
1624 else { 1891 else {
1625 - gen_op_movl_T1_im(0xff);  
1626 - gen_op_iwmmxt_extru_T0_M0_T1((insn & 7) << 3); 1892 + gen_op_iwmmxt_extru_T0_M0((insn & 7) << 3, 0xff);
1627 } 1893 }
1628 break; 1894 break;
1629 case 1: 1895 case 1:
1630 if (insn & 8) 1896 if (insn & 8)
1631 gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4); 1897 gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4);
1632 else { 1898 else {
1633 - gen_op_movl_T1_im(0xffff);  
1634 - gen_op_iwmmxt_extru_T0_M0_T1((insn & 3) << 4); 1899 + gen_op_iwmmxt_extru_T0_M0((insn & 3) << 4, 0xffff);
1635 } 1900 }
1636 break; 1901 break;
1637 case 2: 1902 case 2:
1638 - gen_op_movl_T1_im(0xffffffff);  
1639 - gen_op_iwmmxt_extru_T0_M0_T1((insn & 1) << 5); 1903 + gen_op_iwmmxt_extru_T0_M0((insn & 1) << 5, ~0u);
1640 break; 1904 break;
1641 case 3: 1905 case 3:
1642 return 1; 1906 return 1;
@@ -1669,13 +1933,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1669,13 +1933,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1669 gen_movl_T0_reg(s, rd); 1933 gen_movl_T0_reg(s, rd);
1670 switch ((insn >> 6) & 3) { 1934 switch ((insn >> 6) & 3) {
1671 case 0: 1935 case 0:
1672 - gen_op_iwmmxt_bcstb_M0_T0(); 1936 + gen_helper_iwmmxt_bcstb(cpu_M0, cpu_T[0]);
1673 break; 1937 break;
1674 case 1: 1938 case 1:
1675 - gen_op_iwmmxt_bcstw_M0_T0(); 1939 + gen_helper_iwmmxt_bcstw(cpu_M0, cpu_T[0]);
1676 break; 1940 break;
1677 case 2: 1941 case 2:
1678 - gen_op_iwmmxt_bcstl_M0_T0(); 1942 + gen_helper_iwmmxt_bcstl(cpu_M0, cpu_T[0]);
1679 break; 1943 break;
1680 case 3: 1944 case 3:
1681 return 1; 1945 return 1;
@@ -1715,13 +1979,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1715,13 +1979,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1715 gen_op_iwmmxt_movq_M0_wRn(rd0); 1979 gen_op_iwmmxt_movq_M0_wRn(rd0);
1716 switch ((insn >> 22) & 3) { 1980 switch ((insn >> 22) & 3) {
1717 case 0: 1981 case 0:
1718 - gen_op_iwmmxt_addcb_M0(); 1982 + gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1719 break; 1983 break;
1720 case 1: 1984 case 1:
1721 - gen_op_iwmmxt_addcw_M0(); 1985 + gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1722 break; 1986 break;
1723 case 2: 1987 case 2:
1724 - gen_op_iwmmxt_addcl_M0(); 1988 + gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1725 break; 1989 break;
1726 case 3: 1990 case 3:
1727 return 1; 1991 return 1;
@@ -1763,13 +2027,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1763,13 +2027,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1763 gen_op_iwmmxt_movq_M0_wRn(rd0); 2027 gen_op_iwmmxt_movq_M0_wRn(rd0);
1764 switch ((insn >> 22) & 3) { 2028 switch ((insn >> 22) & 3) {
1765 case 0: 2029 case 0:
1766 - gen_op_iwmmxt_msbb_T0_M0(); 2030 + gen_helper_iwmmxt_msbb(cpu_T[0], cpu_M0);
1767 break; 2031 break;
1768 case 1: 2032 case 1:
1769 - gen_op_iwmmxt_msbw_T0_M0(); 2033 + gen_helper_iwmmxt_msbw(cpu_T[0], cpu_M0);
1770 break; 2034 break;
1771 case 2: 2035 case 2:
1772 - gen_op_iwmmxt_msbl_T0_M0(); 2036 + gen_helper_iwmmxt_msbl(cpu_T[0], cpu_M0);
1773 break; 2037 break;
1774 case 3: 2038 case 3:
1775 return 1; 2039 return 1;
@@ -1881,13 +2145,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1881,13 +2145,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1881 case 0: 2145 case 0:
1882 return 1; 2146 return 1;
1883 case 1: 2147 case 1:
1884 - gen_op_iwmmxt_srlw_M0_T0(); 2148 + gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1885 break; 2149 break;
1886 case 2: 2150 case 2:
1887 - gen_op_iwmmxt_srll_M0_T0(); 2151 + gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1888 break; 2152 break;
1889 case 3: 2153 case 3:
1890 - gen_op_iwmmxt_srlq_M0_T0(); 2154 + gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1891 break; 2155 break;
1892 } 2156 }
1893 gen_op_iwmmxt_movq_wRn_M0(wrd); 2157 gen_op_iwmmxt_movq_wRn_M0(wrd);
@@ -1905,13 +2169,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1905,13 +2169,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1905 case 0: 2169 case 0:
1906 return 1; 2170 return 1;
1907 case 1: 2171 case 1:
1908 - gen_op_iwmmxt_sraw_M0_T0(); 2172 + gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1909 break; 2173 break;
1910 case 2: 2174 case 2:
1911 - gen_op_iwmmxt_sral_M0_T0(); 2175 + gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1912 break; 2176 break;
1913 case 3: 2177 case 3:
1914 - gen_op_iwmmxt_sraq_M0_T0(); 2178 + gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1915 break; 2179 break;
1916 } 2180 }
1917 gen_op_iwmmxt_movq_wRn_M0(wrd); 2181 gen_op_iwmmxt_movq_wRn_M0(wrd);
@@ -1929,13 +2193,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1929,13 +2193,13 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1929 case 0: 2193 case 0:
1930 return 1; 2194 return 1;
1931 case 1: 2195 case 1:
1932 - gen_op_iwmmxt_sllw_M0_T0(); 2196 + gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1933 break; 2197 break;
1934 case 2: 2198 case 2:
1935 - gen_op_iwmmxt_slll_M0_T0(); 2199 + gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1936 break; 2200 break;
1937 case 3: 2201 case 3:
1938 - gen_op_iwmmxt_sllq_M0_T0(); 2202 + gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1939 break; 2203 break;
1940 } 2204 }
1941 gen_op_iwmmxt_movq_wRn_M0(wrd); 2205 gen_op_iwmmxt_movq_wRn_M0(wrd);
@@ -1953,17 +2217,17 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -1953,17 +2217,17 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1953 case 1: 2217 case 1:
1954 if (gen_iwmmxt_shift(insn, 0xf)) 2218 if (gen_iwmmxt_shift(insn, 0xf))
1955 return 1; 2219 return 1;
1956 - gen_op_iwmmxt_rorw_M0_T0(); 2220 + gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1957 break; 2221 break;
1958 case 2: 2222 case 2:
1959 if (gen_iwmmxt_shift(insn, 0x1f)) 2223 if (gen_iwmmxt_shift(insn, 0x1f))
1960 return 1; 2224 return 1;
1961 - gen_op_iwmmxt_rorl_M0_T0(); 2225 + gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1962 break; 2226 break;
1963 case 3: 2227 case 3:
1964 if (gen_iwmmxt_shift(insn, 0x3f)) 2228 if (gen_iwmmxt_shift(insn, 0x3f))
1965 return 1; 2229 return 1;
1966 - gen_op_iwmmxt_rorq_M0_T0(); 2230 + gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
1967 break; 2231 break;
1968 } 2232 }
1969 gen_op_iwmmxt_movq_wRn_M0(wrd); 2233 gen_op_iwmmxt_movq_wRn_M0(wrd);
@@ -2094,7 +2358,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -2094,7 +2358,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
2094 rd0 = (insn >> 16) & 0xf; 2358 rd0 = (insn >> 16) & 0xf;
2095 gen_op_iwmmxt_movq_M0_wRn(rd0); 2359 gen_op_iwmmxt_movq_M0_wRn(rd0);
2096 gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f)); 2360 gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f));
2097 - gen_op_iwmmxt_shufh_M0_T0(); 2361 + gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2098 gen_op_iwmmxt_movq_wRn_M0(wrd); 2362 gen_op_iwmmxt_movq_wRn_M0(wrd);
2099 gen_op_iwmmxt_set_mup(); 2363 gen_op_iwmmxt_set_mup();
2100 gen_op_iwmmxt_set_cup(); 2364 gen_op_iwmmxt_set_cup();
@@ -2279,7 +2543,7 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -2279,7 +2543,7 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2279 return 1; 2543 return 1;
2280 2544
2281 if (insn & ARM_CP_RW_BIT) { /* MRA */ 2545 if (insn & ARM_CP_RW_BIT) { /* MRA */
2282 - gen_op_iwmmxt_movl_T0_T1_wRn(acc); 2546 + gen_iwmmxt_movl_T0_T1_wRn(acc);
2283 gen_movl_reg_T0(s, rdlo); 2547 gen_movl_reg_T0(s, rdlo);
2284 gen_op_movl_T0_im((1 << (40 - 32)) - 1); 2548 gen_op_movl_T0_im((1 << (40 - 32)) - 1);
2285 gen_op_andl_T0_T1(); 2549 gen_op_andl_T0_T1();
@@ -2287,7 +2551,7 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) @@ -2287,7 +2551,7 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2287 } else { /* MAR */ 2551 } else { /* MAR */
2288 gen_movl_T0_reg(s, rdlo); 2552 gen_movl_T0_reg(s, rdlo);
2289 gen_movl_T1_reg(s, rdhi); 2553 gen_movl_T1_reg(s, rdhi);
2290 - gen_op_iwmmxt_movl_wRn_T0_T1(acc); 2554 + gen_iwmmxt_movl_wRn_T0_T1(acc);
2291 } 2555 }
2292 return 0; 2556 return 0;
2293 } 2557 }
@@ -8322,6 +8586,8 @@ static inline int gen_intermediate_code_internal(CPUState *env, @@ -8322,6 +8586,8 @@ static inline int gen_intermediate_code_internal(CPUState *env,
8322 cpu_F1d = tcg_temp_new(TCG_TYPE_I64); 8586 cpu_F1d = tcg_temp_new(TCG_TYPE_I64);
8323 cpu_V0 = cpu_F0d; 8587 cpu_V0 = cpu_F0d;
8324 cpu_V1 = cpu_F1d; 8588 cpu_V1 = cpu_F1d;
  8589 + /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
  8590 + cpu_M0 = tcg_temp_new(TCG_TYPE_I64);
8325 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; 8591 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
8326 lj = -1; 8592 lj = -1;
8327 /* Reset the conditional execution bits immediately. This avoids 8593 /* Reset the conditional execution bits immediately. This avoids