Commit e5e38121576e57ea4f1f4acae01f58f0386ff0ba
1 parent
e1cb9502
Add TurboSPARC mask ID register (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3932 c046a42c-6fe2-441c-8c8c-71466251a162
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11 additions
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1 deletions
hw/iommu.c
| @@ -34,7 +34,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0) | @@ -34,7 +34,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0) | ||
| 34 | #define DPRINTF(fmt, args...) | 34 | #define DPRINTF(fmt, args...) |
| 35 | #endif | 35 | #endif |
| 36 | 36 | ||
| 37 | -#define IOMMU_NREGS (3*4096/4) | 37 | +#define IOMMU_NREGS (4*4096/4) |
| 38 | #define IOMMU_CTRL (0x0000 >> 2) | 38 | #define IOMMU_CTRL (0x0000 >> 2) |
| 39 | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ | 39 | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
| 40 | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ | 40 | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
| @@ -95,6 +95,12 @@ do { printf("IOMMU: " fmt , ##args); } while (0) | @@ -95,6 +95,12 @@ do { printf("IOMMU: " fmt , ##args); } while (0) | ||
| 95 | #define IOMMU_ARBEN_MASK 0x001f0000 | 95 | #define IOMMU_ARBEN_MASK 0x001f0000 |
| 96 | #define IOMMU_MID 0x00000008 | 96 | #define IOMMU_MID 0x00000008 |
| 97 | 97 | ||
| 98 | +#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ | ||
| 99 | +#define IOMMU_MASK_ID_MASK 0x00ffffff | ||
| 100 | + | ||
| 101 | +#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ | ||
| 102 | +#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ | ||
| 103 | + | ||
| 98 | /* The format of an iopte in the page tables */ | 104 | /* The format of an iopte in the page tables */ |
| 99 | #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ | 105 | #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
| 100 | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or | 106 | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
| @@ -206,6 +212,9 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, | @@ -206,6 +212,9 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, | ||
| 206 | // addresses, fault cause and address stored to MMU/IOMMU | 212 | // addresses, fault cause and address stored to MMU/IOMMU |
| 207 | s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; | 213 | s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
| 208 | break; | 214 | break; |
| 215 | + case IOMMU_MASK_ID: | ||
| 216 | + s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; | ||
| 217 | + break; | ||
| 209 | default: | 218 | default: |
| 210 | s->regs[saddr] = val; | 219 | s->regs[saddr] = val; |
| 211 | break; | 220 | break; |
| @@ -337,6 +346,7 @@ static void iommu_reset(void *opaque) | @@ -337,6 +346,7 @@ static void iommu_reset(void *opaque) | ||
| 337 | s->regs[IOMMU_CTRL] = s->version; | 346 | s->regs[IOMMU_CTRL] = s->version; |
| 338 | s->regs[IOMMU_ARBEN] = IOMMU_MID; | 347 | s->regs[IOMMU_ARBEN] = IOMMU_MID; |
| 339 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; | 348 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
| 349 | + s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; | ||
| 340 | qemu_irq_lower(s->irq); | 350 | qemu_irq_lower(s->irq); |
| 341 | } | 351 | } |
| 342 | 352 |