gwj / at91sam9263 · Commits

Commit e571cb477b2ed6000dfa0fdafe8cab6c0aa1bb15

Authored by aurel32
1 parent c8b3532d

target-ppc: Change core powerpc gdbstub bits to be XML-aware 

Define GDB_CORE_XML and hack things similarly to ARM so that despite the
FP registers coming in between the GPRs and some status registers,
everything works out OK no matter which kind of GDB we're communicating
with.

It matters whether we're built to target 64-bit or 32-bit cores.  I
think there are still problems if we are debugging 32-bit programs on a
built-for-64-bit QEMU (QEMU will always send 64-bit registers), but I
don't know if there's a good way around that at the time being.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6421 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 22 additions and 1 deletions
gdbstub.c
  View file @e571cb4
@@ -620,7 +620,17 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i) @@ -620,7 +620,17 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)
620 620
621 #elif defined (TARGET_PPC) 621 #elif defined (TARGET_PPC)
622 622
  623 +/* Old gdb always expects FP registers. Newer (xml-aware) gdb only
  624 + expects whatever the target description contains. Due to a
  625 + historical mishap the FP registers appear in between core integer
  626 + regs and PC, MSR, CR, and so forth. We hack round this by giving the
  627 + FP regs zero size when talking to a newer gdb. */
623 #define NUM_CORE_REGS 71 628 #define NUM_CORE_REGS 71
  629 +#if defined (TARGET_PPC64)
  630 +#define GDB_CORE_XML "power64-core.xml"
  631 +#else
  632 +#define GDB_CORE_XML "power-core.xml"
  633 +#endif
624 634
625 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) 635 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
626 { 636 {
@@ -629,6 +639,8 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) @@ -629,6 +639,8 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
629 GET_REGL(env->gpr[n]); 639 GET_REGL(env->gpr[n]);
630 } else if (n < 64) { 640 } else if (n < 64) {
631 /* fprs */ 641 /* fprs */
  642 + if (gdb_has_xml)
  643 + return 0;
632 stfq_p(mem_buf, env->fpr[n-32]); 644 stfq_p(mem_buf, env->fpr[n-32]);
633 return 8; 645 return 8;
634 } else { 646 } else {
@@ -646,7 +658,12 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) @@ -646,7 +658,12 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
646 case 67: GET_REGL(env->lr); 658 case 67: GET_REGL(env->lr);
647 case 68: GET_REGL(env->ctr); 659 case 68: GET_REGL(env->ctr);
648 case 69: GET_REGL(env->xer); 660 case 69: GET_REGL(env->xer);
649 - case 70: GET_REG32(0); /* fpscr */ 661 + case 70:
  662 + {
  663 + if (gdb_has_xml)
  664 + return 0;
  665 + GET_REG32(0); /* fpscr */
  666 + }
650 } 667 }
651 } 668 }
652 return 0; 669 return 0;
@@ -660,6 +677,8 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) @@ -660,6 +677,8 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
660 return sizeof(target_ulong); 677 return sizeof(target_ulong);
661 } else if (n < 64) { 678 } else if (n < 64) {
662 /* fprs */ 679 /* fprs */
  680 + if (gdb_has_xml)
  681 + return 0;
663 env->fpr[n-32] = ldfq_p(mem_buf); 682 env->fpr[n-32] = ldfq_p(mem_buf);
664 return 8; 683 return 8;
665 } else { 684 } else {
@@ -689,6 +708,8 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) @@ -689,6 +708,8 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
689 return sizeof(target_ulong); 708 return sizeof(target_ulong);
690 case 70: 709 case 70:
691 /* fpscr */ 710 /* fpscr */
  711 + if (gdb_has_xml)
  712 + return 0;
692 return 4; 713 return 4;
693 } 714 }
694 } 715 }