gwj / at91sam9263 · Commits

Commit e55fd9340e66b7b8361b64f01ce20b3d575a2194

Authored by aurel32
1 parent 02f4f6c2

[ppc] Convert op_move_{T1,T2}_T0 to TCG 

Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with
tcg_gen_mov_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5137 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 19 additions and 31 deletions
target-ppc/op.c
  View file @e55fd93
... ... @@ -179,18 +179,6 @@ void OPPROTO op_set_T2 (void)
179 179 }
180 180 #endif
181 181  
182   -void OPPROTO op_move_T1_T0 (void)
183   -{
184   - T1 = T0;
185   - RETURN();
186   -}
187   -
188   -void OPPROTO op_move_T2_T0 (void)
189   -{
190   - T2 = T0;
191   - RETURN();
192   -}
193   -
194 182 void OPPROTO op_moven_T2_T0 (void)
195 183 {
196 184 T2 = ~T0;
... ...
target-ppc/translate.c
  View file @e55fd93
... ... @@ -795,7 +795,7 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
795 795 /* add add. addo addo. */
796 796 static always_inline void gen_op_addo (void)
797 797 {
798   - gen_op_move_T2_T0();
  798 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
799 799 gen_op_add();
800 800 gen_op_check_addo();
801 801 }
... ... @@ -803,7 +803,7 @@ static always_inline void gen_op_addo (void)
803 803 #define gen_op_add_64 gen_op_add
804 804 static always_inline void gen_op_addo_64 (void)
805 805 {
806   - gen_op_move_T2_T0();
  806 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
807 807 gen_op_add();
808 808 gen_op_check_addo_64();
809 809 }
... ... @@ -812,13 +812,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
812 812 /* addc addc. addco addco. */
813 813 static always_inline void gen_op_addc (void)
814 814 {
815   - gen_op_move_T2_T0();
  815 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
816 816 gen_op_add();
817 817 gen_op_check_addc();
818 818 }
819 819 static always_inline void gen_op_addco (void)
820 820 {
821   - gen_op_move_T2_T0();
  821 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
822 822 gen_op_add();
823 823 gen_op_check_addc();
824 824 gen_op_check_addo();
... ... @@ -826,13 +826,13 @@ static always_inline void gen_op_addco (void)
826 826 #if defined(TARGET_PPC64)
827 827 static always_inline void gen_op_addc_64 (void)
828 828 {
829   - gen_op_move_T2_T0();
  829 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
830 830 gen_op_add();
831 831 gen_op_check_addc_64();
832 832 }
833 833 static always_inline void gen_op_addco_64 (void)
834 834 {
835   - gen_op_move_T2_T0();
  835 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
836 836 gen_op_add();
837 837 gen_op_check_addc_64();
838 838 gen_op_check_addo_64();
... ... @@ -842,14 +842,14 @@ GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
842 842 /* adde adde. addeo addeo. */
843 843 static always_inline void gen_op_addeo (void)
844 844 {
845   - gen_op_move_T2_T0();
  845 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
846 846 gen_op_adde();
847 847 gen_op_check_addo();
848 848 }
849 849 #if defined(TARGET_PPC64)
850 850 static always_inline void gen_op_addeo_64 (void)
851 851 {
852   - gen_op_move_T2_T0();
  852 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
853 853 gen_op_adde_64();
854 854 gen_op_check_addo_64();
855 855 }
... ... @@ -858,13 +858,13 @@ GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
858 858 /* addme addme. addmeo addmeo. */
859 859 static always_inline void gen_op_addme (void)
860 860 {
861   - gen_op_move_T1_T0();
  861 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
862 862 gen_op_add_me();
863 863 }
864 864 #if defined(TARGET_PPC64)
865 865 static always_inline void gen_op_addme_64 (void)
866 866 {
867   - gen_op_move_T1_T0();
  867 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
868 868 gen_op_add_me_64();
869 869 }
870 870 #endif
... ... @@ -872,13 +872,13 @@ GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
872 872 /* addze addze. addzeo addzeo. */
873 873 static always_inline void gen_op_addze (void)
874 874 {
875   - gen_op_move_T2_T0();
  875 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
876 876 gen_op_add_ze();
877 877 gen_op_check_addc();
878 878 }
879 879 static always_inline void gen_op_addzeo (void)
880 880 {
881   - gen_op_move_T2_T0();
  881 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
882 882 gen_op_add_ze();
883 883 gen_op_check_addc();
884 884 gen_op_check_addo();
... ... @@ -886,13 +886,13 @@ static always_inline void gen_op_addzeo (void)
886 886 #if defined(TARGET_PPC64)
887 887 static always_inline void gen_op_addze_64 (void)
888 888 {
889   - gen_op_move_T2_T0();
  889 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
890 890 gen_op_add_ze();
891 891 gen_op_check_addc_64();
892 892 }
893 893 static always_inline void gen_op_addzeo_64 (void)
894 894 {
895   - gen_op_move_T2_T0();
  895 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
896 896 gen_op_add_ze();
897 897 gen_op_check_addc_64();
898 898 gen_op_check_addo_64();
... ... @@ -999,7 +999,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
999 999  
1000 1000 gen_op_load_gpr_T0(rA(ctx->opcode));
1001 1001 if (likely(simm != 0)) {
1002   - gen_op_move_T2_T0();
  1002 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1003 1003 gen_op_addi(simm);
1004 1004 #if defined(TARGET_PPC64)
1005 1005 if (ctx->sf_mode)
... ... @@ -1019,7 +1019,7 @@ GEN_HANDLER2(addic_, &quot;addic.&quot;, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1019 1019  
1020 1020 gen_op_load_gpr_T0(rA(ctx->opcode));
1021 1021 if (likely(simm != 0)) {
1022   - gen_op_move_T2_T0();
  1022 + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1023 1023 gen_op_addi(simm);
1024 1024 #if defined(TARGET_PPC64)
1025 1025 if (ctx->sf_mode)
... ... @@ -1661,7 +1661,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1661 1661 int mb, me;
1662 1662 gen_op_load_gpr_T0(rS(ctx->opcode));
1663 1663 if (SH(ctx->opcode) != 0) {
1664   - gen_op_move_T1_T0();
  1664 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1665 1665 mb = 32 - SH(ctx->opcode);
1666 1666 me = 31;
1667 1667 #if defined(TARGET_PPC64)
... ... @@ -1691,7 +1691,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
1691 1691 gen_op_load_gpr_T0(rS(ctx->opcode));
1692 1692 sh = SH(ctx->opcode) + (n << 5);
1693 1693 if (sh != 0) {
1694   - gen_op_move_T1_T0();
  1694 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1695 1695 mb = 64 - SH(ctx->opcode);
1696 1696 me = 63;
1697 1697 mask = MASK(mb, me);
... ... @@ -4647,7 +4647,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4647 4647 if (opc2 & 0x04) {
4648 4648 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4649 4649 gen_op_load_gpr_T2(rt);
4650   - gen_op_move_T1_T0();
  4650 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
4651 4651 gen_op_405_add_T0_T2();
4652 4652 }
4653 4653 if (opc3 & 0x10) {
... ...