gwj / at91sam9263 · Commits

Commit e37e863f5e492cf60db21233f4008aafd6c5f610

Authored by bellard
1 parent fdabc366

correct split between helper.c and op_helper.c - cosmetics 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1505 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 233 additions and 242 deletions
target-mips/cpu.h
  View file @e37e863
... ... @@ -240,174 +240,6 @@ enum {
240 240 EXCP_FLUSH = 0x109,
241 241 };
242 242  
243   -/* MIPS opcodes */
244   -#define EXT_SPECIAL 0x100
245   -#define EXT_SPECIAL2 0x200
246   -#define EXT_REGIMM 0x300
247   -#define EXT_CP0 0x400
248   -#define EXT_CP1 0x500
249   -#define EXT_CP2 0x600
250   -#define EXT_CP3 0x700
251   -
252   -enum {
253   - /* indirect opcode tables */
254   - OPC_SPECIAL = 0x00,
255   - OPC_BREGIMM = 0x01,
256   - OPC_CP0 = 0x10,
257   - OPC_CP1 = 0x11,
258   - OPC_CP2 = 0x12,
259   - OPC_CP3 = 0x13,
260   - OPC_SPECIAL2 = 0x1C,
261   - /* arithmetic with immediate */
262   - OPC_ADDI = 0x08,
263   - OPC_ADDIU = 0x09,
264   - OPC_SLTI = 0x0A,
265   - OPC_SLTIU = 0x0B,
266   - OPC_ANDI = 0x0C,
267   - OPC_ORI = 0x0D,
268   - OPC_XORI = 0x0E,
269   - OPC_LUI = 0x0F,
270   - /* Jump and branches */
271   - OPC_J = 0x02,
272   - OPC_JAL = 0x03,
273   - OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
274   - OPC_BEQL = 0x14,
275   - OPC_BNE = 0x05,
276   - OPC_BNEL = 0x15,
277   - OPC_BLEZ = 0x06,
278   - OPC_BLEZL = 0x16,
279   - OPC_BGTZ = 0x07,
280   - OPC_BGTZL = 0x17,
281   - OPC_JALX = 0x1D, /* MIPS 16 only */
282   - /* Load and stores */
283   - OPC_LB = 0x20,
284   - OPC_LH = 0x21,
285   - OPC_LWL = 0x22,
286   - OPC_LW = 0x23,
287   - OPC_LBU = 0x24,
288   - OPC_LHU = 0x25,
289   - OPC_LWR = 0x26,
290   - OPC_SB = 0x28,
291   - OPC_SH = 0x29,
292   - OPC_SWL = 0x2A,
293   - OPC_SW = 0x2B,
294   - OPC_SWR = 0x2E,
295   - OPC_LL = 0x30,
296   - OPC_SC = 0x38,
297   - /* Floating point load/store */
298   - OPC_LWC1 = 0x31,
299   - OPC_LWC2 = 0x32,
300   - OPC_LDC1 = 0x35,
301   - OPC_LDC2 = 0x36,
302   - OPC_SWC1 = 0x39,
303   - OPC_SWC2 = 0x3A,
304   - OPC_SDC1 = 0x3D,
305   - OPC_SDC2 = 0x3E,
306   - /* Cache and prefetch */
307   - OPC_CACHE = 0x2F,
308   - OPC_PREF = 0x33,
309   -};
310   -
311   -/* MIPS special opcodes */
312   -enum {
313   - /* Shifts */
314   - OPC_SLL = 0x00 | EXT_SPECIAL,
315   - /* NOP is SLL r0, r0, 0 */
316   - /* SSNOP is SLL r0, r0, 1 */
317   - OPC_SRL = 0x02 | EXT_SPECIAL,
318   - OPC_SRA = 0x03 | EXT_SPECIAL,
319   - OPC_SLLV = 0x04 | EXT_SPECIAL,
320   - OPC_SRLV = 0x06 | EXT_SPECIAL,
321   - OPC_SRAV = 0x07 | EXT_SPECIAL,
322   - /* Multiplication / division */
323   - OPC_MULT = 0x18 | EXT_SPECIAL,
324   - OPC_MULTU = 0x19 | EXT_SPECIAL,
325   - OPC_DIV = 0x1A | EXT_SPECIAL,
326   - OPC_DIVU = 0x1B | EXT_SPECIAL,
327   - /* 2 registers arithmetic / logic */
328   - OPC_ADD = 0x20 | EXT_SPECIAL,
329   - OPC_ADDU = 0x21 | EXT_SPECIAL,
330   - OPC_SUB = 0x22 | EXT_SPECIAL,
331   - OPC_SUBU = 0x23 | EXT_SPECIAL,
332   - OPC_AND = 0x24 | EXT_SPECIAL,
333   - OPC_OR = 0x25 | EXT_SPECIAL,
334   - OPC_XOR = 0x26 | EXT_SPECIAL,
335   - OPC_NOR = 0x27 | EXT_SPECIAL,
336   - OPC_SLT = 0x2A | EXT_SPECIAL,
337   - OPC_SLTU = 0x2B | EXT_SPECIAL,
338   - /* Jumps */
339   - OPC_JR = 0x08 | EXT_SPECIAL,
340   - OPC_JALR = 0x09 | EXT_SPECIAL,
341   - /* Traps */
342   - OPC_TGE = 0x30 | EXT_SPECIAL,
343   - OPC_TGEU = 0x31 | EXT_SPECIAL,
344   - OPC_TLT = 0x32 | EXT_SPECIAL,
345   - OPC_TLTU = 0x33 | EXT_SPECIAL,
346   - OPC_TEQ = 0x34 | EXT_SPECIAL,
347   - OPC_TNE = 0x36 | EXT_SPECIAL,
348   - /* HI / LO registers load & stores */
349   - OPC_MFHI = 0x10 | EXT_SPECIAL,
350   - OPC_MTHI = 0x11 | EXT_SPECIAL,
351   - OPC_MFLO = 0x12 | EXT_SPECIAL,
352   - OPC_MTLO = 0x13 | EXT_SPECIAL,
353   - /* Conditional moves */
354   - OPC_MOVZ = 0x0A | EXT_SPECIAL,
355   - OPC_MOVN = 0x0B | EXT_SPECIAL,
356   -
357   - OPC_MOVCI = 0x01 | EXT_SPECIAL,
358   -
359   - /* Special */
360   - OPC_PMON = 0x05 | EXT_SPECIAL,
361   - OPC_SYSCALL = 0x0C | EXT_SPECIAL,
362   - OPC_BREAK = 0x0D | EXT_SPECIAL,
363   - OPC_SYNC = 0x0F | EXT_SPECIAL,
364   -};
365   -
366   -enum {
367   - /* Mutiply & xxx operations */
368   - OPC_MADD = 0x00 | EXT_SPECIAL2,
369   - OPC_MADDU = 0x01 | EXT_SPECIAL2,
370   - OPC_MUL = 0x02 | EXT_SPECIAL2,
371   - OPC_MSUB = 0x04 | EXT_SPECIAL2,
372   - OPC_MSUBU = 0x05 | EXT_SPECIAL2,
373   - /* Misc */
374   - OPC_CLZ = 0x20 | EXT_SPECIAL2,
375   - OPC_CLO = 0x21 | EXT_SPECIAL2,
376   - /* Special */
377   - OPC_SDBBP = 0x3F | EXT_SPECIAL2,
378   -};
379   -
380   -/* Branch REGIMM */
381   -enum {
382   - OPC_BLTZ = 0x00 | EXT_REGIMM,
383   - OPC_BLTZL = 0x02 | EXT_REGIMM,
384   - OPC_BGEZ = 0x01 | EXT_REGIMM,
385   - OPC_BGEZL = 0x03 | EXT_REGIMM,
386   - OPC_BLTZAL = 0x10 | EXT_REGIMM,
387   - OPC_BLTZALL = 0x12 | EXT_REGIMM,
388   - OPC_BGEZAL = 0x11 | EXT_REGIMM,
389   - OPC_BGEZALL = 0x13 | EXT_REGIMM,
390   - OPC_TGEI = 0x08 | EXT_REGIMM,
391   - OPC_TGEIU = 0x09 | EXT_REGIMM,
392   - OPC_TLTI = 0x0A | EXT_REGIMM,
393   - OPC_TLTIU = 0x0B | EXT_REGIMM,
394   - OPC_TEQI = 0x0C | EXT_REGIMM,
395   - OPC_TNEI = 0x0E | EXT_REGIMM,
396   -};
397   -
398   -enum {
399   - /* Coprocessor 0 (MMU) */
400   - OPC_MFC0 = 0x00 | EXT_CP0,
401   - OPC_MTC0 = 0x04 | EXT_CP0,
402   - OPC_TLBR = 0x01 | EXT_CP0,
403   - OPC_TLBWI = 0x02 | EXT_CP0,
404   - OPC_TLBWR = 0x06 | EXT_CP0,
405   - OPC_TLBP = 0x08 | EXT_CP0,
406   - OPC_ERET = 0x18 | EXT_CP0,
407   - OPC_DERET = 0x1F | EXT_CP0,
408   - OPC_WAIT = 0x20 | EXT_CP0,
409   -};
410   -
411 243 int cpu_mips_exec(CPUMIPSState *s);
412 244 CPUMIPSState *cpu_mips_init(void);
413 245 uint32_t cpu_mips_get_clock (void);
... ...
target-mips/exec.h
  View file @e37e863
... ... @@ -19,27 +19,15 @@ typedef uint32_t host_uint_t;
19 19 register host_uint_t T0 asm(AREG1);
20 20 register host_uint_t T1 asm(AREG2);
21 21 register host_uint_t T2 asm(AREG3);
22   -register host_int_t Ts0 asm(AREG1);
23   -register host_int_t Ts1 asm(AREG2);
24   -register host_int_t Ts2 asm(AREG3);
25   -
26   -#define PARAM(n) ((uint32_t)PARAM##n)
27   -#define SPARAM(n) ((int32_t)PARAM##n)
28 22  
29 23 #if defined (USE_HOST_FLOAT_REGS)
30 24 register double FT0 asm(FREG0);
31 25 register double FT1 asm(FREG1);
32 26 register double FT2 asm(FREG2);
33   -register float FTS0 asm(FREG0);
34   -register float FTS1 asm(FREG1);
35   -register float FTS2 asm(FREG2);
36 27 #else
37 28 #define FT0 (env->ft0.d)
38 29 #define FT1 (env->ft1.d)
39 30 #define FT2 (env->ft2.d)
40   -#define FTS0 (env->ft0.f)
41   -#define FTS1 (env->ft1.f)
42   -#define FTS2 (env->ft2.f)
43 31 #endif
44 32  
45 33 #if defined (DEBUG_OP)
... ...
target-mips/helper.c
  View file @e37e863
... ... @@ -17,7 +17,16 @@
17 17 * License along with this library; if not, write to the Free Software
18 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 */
20   -#include "exec.h"
  20 +#include <stdarg.h>
  21 +#include <stdlib.h>
  22 +#include <stdio.h>
  23 +#include <string.h>
  24 +#include <inttypes.h>
  25 +#include <signal.h>
  26 +#include <assert.h>
  27 +
  28 +#include "cpu.h"
  29 +#include "exec-all.h"
21 30  
22 31 /* MIPS32 4K MMU emulation */
23 32 #ifdef MIPS_USES_R4K_TLB
... ... @@ -142,57 +151,10 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
142 151 return -1;
143 152 return phys_addr;
144 153 }
145   -#endif
146   -
147   -#if !defined(CONFIG_USER_ONLY)
148   -
149   -#define MMUSUFFIX _mmu
150   -#define GETPC() (__builtin_return_address(0))
151   -
152   -#define SHIFT 0
153   -#include "softmmu_template.h"
154   -
155   -#define SHIFT 1
156   -#include "softmmu_template.h"
157   -
158   -#define SHIFT 2
159   -#include "softmmu_template.h"
160   -
161   -#define SHIFT 3
162   -#include "softmmu_template.h"
163   -
164   -void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
165   -{
166   - TranslationBlock *tb;
167   - CPUState *saved_env;
168   - unsigned long pc;
169   - int ret;
170   -
171   - /* XXX: hack to restore env in all cases, even if not called from
172   - generated code */
173   - saved_env = env;
174   - env = cpu_single_env;
175   - ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
176   - if (ret) {
177   - if (retaddr) {
178   - /* now we have a real cpu fault */
179   - pc = (unsigned long)retaddr;
180   - tb = tb_find_pc(pc);
181   - if (tb) {
182   - /* the PC is inside the translated code. It means that we have
183   - a virtual CPU fault */
184   - cpu_restore_state(tb, env, pc, NULL);
185   - }
186   - }
187   - do_raise_exception_err(env->exception_index, env->error_code);
188   - }
189   - env = saved_env;
190   -}
191 154  
192 155 void cpu_mips_init_mmu (CPUState *env)
193 156 {
194 157 }
195   -
196 158 #endif /* !defined(CONFIG_USER_ONLY) */
197 159  
198 160 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
... ...
target-mips/op_helper.c
  View file @e37e863
... ... @@ -29,7 +29,6 @@ void cpu_loop_exit(void)
29 29 longjmp(env->jmp_env, 1);
30 30 }
31 31  
32   -__attribute__ (( regparm(2) ))
33 32 void do_raise_exception_err (uint32_t exception, int error_code)
34 33 {
35 34 #if 1
... ... @@ -42,7 +41,6 @@ void do_raise_exception_err (uint32_t exception, int error_code)
42 41 cpu_loop_exit();
43 42 }
44 43  
45   -__attribute__ (( regparm(1) ))
46 44 void do_raise_exception (uint32_t exception)
47 45 {
48 46 do_raise_exception_err(exception, 0);
... ... @@ -117,7 +115,6 @@ void do_msubu (void)
117 115 #endif
118 116  
119 117 /* CP0 helpers */
120   -__attribute__ (( regparm(2) ))
121 118 void do_mfc0 (int reg, int sel)
122 119 {
123 120 const unsigned char *rn;
... ... @@ -267,12 +264,10 @@ void do_mfc0 (int reg, int sel)
267 264 return;
268 265 }
269 266  
270   -__attribute__ (( regparm(2) ))
271 267 void do_mtc0 (int reg, int sel)
272 268 {
273 269 const unsigned char *rn;
274 270 uint32_t val, old, mask;
275   - int i, raise;
276 271  
277 272 if (sel != 0 && reg != 16 && reg != 28) {
278 273 val = -1;
... ... @@ -379,11 +374,14 @@ void do_mtc0 (int reg, int sel)
379 374 old = env->CP0_Cause;
380 375 env->CP0_Cause = val;
381 376 #if 0
382   - /* Check if we ever asserted a software IRQ */
383   - for (i = 0; i < 2; i++) {
384   - mask = 0x100 << i;
385   - if ((val & mask) & !(old & mask))
386   - mips_set_irq(i);
  377 + {
  378 + int i;
  379 + /* Check if we ever asserted a software IRQ */
  380 + for (i = 0; i < 2; i++) {
  381 + mask = 0x100 << i;
  382 + if ((val & mask) & !(old & mask))
  383 + mips_set_irq(i);
  384 + }
387 385 }
388 386 #endif
389 387 rn = "Cause";
... ... @@ -486,7 +484,6 @@ void do_mtc0 (int reg, int sel)
486 484  
487 485 /* TLB management */
488 486 #if defined(MIPS_USES_R4K_TLB)
489   -__attribute__ (( regparm(1) ))
490 487 static void invalidate_tb (int idx)
491 488 {
492 489 tlb_t *tlb;
... ... @@ -505,7 +502,6 @@ static void invalidate_tb (int idx)
505 502 }
506 503 }
507 504  
508   -__attribute__ (( regparm(1) ))
509 505 static void fill_tb (int idx)
510 506 {
511 507 tlb_t *tlb;
... ... @@ -584,7 +580,6 @@ void do_tlbr (void)
584 580 }
585 581 #endif
586 582  
587   -__attribute__ (( regparm(1) ))
588 583 void op_dump_ldst (const unsigned char *func)
589 584 {
590 585 if (loglevel)
... ... @@ -608,7 +603,6 @@ void debug_eret (void)
608 603 }
609 604 }
610 605  
611   -__attribute__ (( regparm(1) ))
612 606 void do_pmon (int function)
613 607 {
614 608 function /= 2;
... ... @@ -634,3 +628,50 @@ void do_pmon (int function)
634 628 break;
635 629 }
636 630 }
  631 +
  632 +#if !defined(CONFIG_USER_ONLY)
  633 +
  634 +#define MMUSUFFIX _mmu
  635 +#define GETPC() (__builtin_return_address(0))
  636 +
  637 +#define SHIFT 0
  638 +#include "softmmu_template.h"
  639 +
  640 +#define SHIFT 1
  641 +#include "softmmu_template.h"
  642 +
  643 +#define SHIFT 2
  644 +#include "softmmu_template.h"
  645 +
  646 +#define SHIFT 3
  647 +#include "softmmu_template.h"
  648 +
  649 +void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
  650 +{
  651 + TranslationBlock *tb;
  652 + CPUState *saved_env;
  653 + unsigned long pc;
  654 + int ret;
  655 +
  656 + /* XXX: hack to restore env in all cases, even if not called from
  657 + generated code */
  658 + saved_env = env;
  659 + env = cpu_single_env;
  660 + ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
  661 + if (ret) {
  662 + if (retaddr) {
  663 + /* now we have a real cpu fault */
  664 + pc = (unsigned long)retaddr;
  665 + tb = tb_find_pc(pc);
  666 + if (tb) {
  667 + /* the PC is inside the translated code. It means that we have
  668 + a virtual CPU fault */
  669 + cpu_restore_state(tb, env, pc, NULL);
  670 + }
  671 + }
  672 + do_raise_exception_err(env->exception_index, env->error_code);
  673 + }
  674 + env = saved_env;
  675 +}
  676 +
  677 +#endif
... ...
target-mips/translate.c
  View file @e37e863
... ... @@ -43,6 +43,174 @@ static uint32_t *gen_opparam_ptr;
43 43  
44 44 #include "gen-op.h"
45 45  
  46 +/* MIPS opcodes */
  47 +#define EXT_SPECIAL 0x100
  48 +#define EXT_SPECIAL2 0x200
  49 +#define EXT_REGIMM 0x300
  50 +#define EXT_CP0 0x400
  51 +#define EXT_CP1 0x500
  52 +#define EXT_CP2 0x600
  53 +#define EXT_CP3 0x700
  54 +
  55 +enum {
  56 + /* indirect opcode tables */
  57 + OPC_SPECIAL = 0x00,
  58 + OPC_BREGIMM = 0x01,
  59 + OPC_CP0 = 0x10,
  60 + OPC_CP1 = 0x11,
  61 + OPC_CP2 = 0x12,
  62 + OPC_CP3 = 0x13,
  63 + OPC_SPECIAL2 = 0x1C,
  64 + /* arithmetic with immediate */
  65 + OPC_ADDI = 0x08,
  66 + OPC_ADDIU = 0x09,
  67 + OPC_SLTI = 0x0A,
  68 + OPC_SLTIU = 0x0B,
  69 + OPC_ANDI = 0x0C,
  70 + OPC_ORI = 0x0D,
  71 + OPC_XORI = 0x0E,
  72 + OPC_LUI = 0x0F,
  73 + /* Jump and branches */
  74 + OPC_J = 0x02,
  75 + OPC_JAL = 0x03,
  76 + OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
  77 + OPC_BEQL = 0x14,
  78 + OPC_BNE = 0x05,
  79 + OPC_BNEL = 0x15,
  80 + OPC_BLEZ = 0x06,
  81 + OPC_BLEZL = 0x16,
  82 + OPC_BGTZ = 0x07,
  83 + OPC_BGTZL = 0x17,
  84 + OPC_JALX = 0x1D, /* MIPS 16 only */
  85 + /* Load and stores */
  86 + OPC_LB = 0x20,
  87 + OPC_LH = 0x21,
  88 + OPC_LWL = 0x22,
  89 + OPC_LW = 0x23,
  90 + OPC_LBU = 0x24,
  91 + OPC_LHU = 0x25,
  92 + OPC_LWR = 0x26,
  93 + OPC_SB = 0x28,
  94 + OPC_SH = 0x29,
  95 + OPC_SWL = 0x2A,
  96 + OPC_SW = 0x2B,
  97 + OPC_SWR = 0x2E,
  98 + OPC_LL = 0x30,
  99 + OPC_SC = 0x38,
  100 + /* Floating point load/store */
  101 + OPC_LWC1 = 0x31,
  102 + OPC_LWC2 = 0x32,
  103 + OPC_LDC1 = 0x35,
  104 + OPC_LDC2 = 0x36,
  105 + OPC_SWC1 = 0x39,
  106 + OPC_SWC2 = 0x3A,
  107 + OPC_SDC1 = 0x3D,
  108 + OPC_SDC2 = 0x3E,
  109 + /* Cache and prefetch */
  110 + OPC_CACHE = 0x2F,
  111 + OPC_PREF = 0x33,
  112 +};
  113 +
  114 +/* MIPS special opcodes */
  115 +enum {
  116 + /* Shifts */
  117 + OPC_SLL = 0x00 | EXT_SPECIAL,
  118 + /* NOP is SLL r0, r0, 0 */
  119 + /* SSNOP is SLL r0, r0, 1 */
  120 + OPC_SRL = 0x02 | EXT_SPECIAL,
  121 + OPC_SRA = 0x03 | EXT_SPECIAL,
  122 + OPC_SLLV = 0x04 | EXT_SPECIAL,
  123 + OPC_SRLV = 0x06 | EXT_SPECIAL,
  124 + OPC_SRAV = 0x07 | EXT_SPECIAL,
  125 + /* Multiplication / division */
  126 + OPC_MULT = 0x18 | EXT_SPECIAL,
  127 + OPC_MULTU = 0x19 | EXT_SPECIAL,
  128 + OPC_DIV = 0x1A | EXT_SPECIAL,
  129 + OPC_DIVU = 0x1B | EXT_SPECIAL,
  130 + /* 2 registers arithmetic / logic */
  131 + OPC_ADD = 0x20 | EXT_SPECIAL,
  132 + OPC_ADDU = 0x21 | EXT_SPECIAL,
  133 + OPC_SUB = 0x22 | EXT_SPECIAL,
  134 + OPC_SUBU = 0x23 | EXT_SPECIAL,
  135 + OPC_AND = 0x24 | EXT_SPECIAL,
  136 + OPC_OR = 0x25 | EXT_SPECIAL,
  137 + OPC_XOR = 0x26 | EXT_SPECIAL,
  138 + OPC_NOR = 0x27 | EXT_SPECIAL,
  139 + OPC_SLT = 0x2A | EXT_SPECIAL,
  140 + OPC_SLTU = 0x2B | EXT_SPECIAL,
  141 + /* Jumps */
  142 + OPC_JR = 0x08 | EXT_SPECIAL,
  143 + OPC_JALR = 0x09 | EXT_SPECIAL,
  144 + /* Traps */
  145 + OPC_TGE = 0x30 | EXT_SPECIAL,
  146 + OPC_TGEU = 0x31 | EXT_SPECIAL,
  147 + OPC_TLT = 0x32 | EXT_SPECIAL,
  148 + OPC_TLTU = 0x33 | EXT_SPECIAL,
  149 + OPC_TEQ = 0x34 | EXT_SPECIAL,
  150 + OPC_TNE = 0x36 | EXT_SPECIAL,
  151 + /* HI / LO registers load & stores */
  152 + OPC_MFHI = 0x10 | EXT_SPECIAL,
  153 + OPC_MTHI = 0x11 | EXT_SPECIAL,
  154 + OPC_MFLO = 0x12 | EXT_SPECIAL,
  155 + OPC_MTLO = 0x13 | EXT_SPECIAL,
  156 + /* Conditional moves */
  157 + OPC_MOVZ = 0x0A | EXT_SPECIAL,
  158 + OPC_MOVN = 0x0B | EXT_SPECIAL,
  159 +
  160 + OPC_MOVCI = 0x01 | EXT_SPECIAL,
  161 +
  162 + /* Special */
  163 + OPC_PMON = 0x05 | EXT_SPECIAL,
  164 + OPC_SYSCALL = 0x0C | EXT_SPECIAL,
  165 + OPC_BREAK = 0x0D | EXT_SPECIAL,
  166 + OPC_SYNC = 0x0F | EXT_SPECIAL,
  167 +};
  168 +
  169 +enum {
  170 + /* Mutiply & xxx operations */
  171 + OPC_MADD = 0x00 | EXT_SPECIAL2,
  172 + OPC_MADDU = 0x01 | EXT_SPECIAL2,
  173 + OPC_MUL = 0x02 | EXT_SPECIAL2,
  174 + OPC_MSUB = 0x04 | EXT_SPECIAL2,
  175 + OPC_MSUBU = 0x05 | EXT_SPECIAL2,
  176 + /* Misc */
  177 + OPC_CLZ = 0x20 | EXT_SPECIAL2,
  178 + OPC_CLO = 0x21 | EXT_SPECIAL2,
  179 + /* Special */
  180 + OPC_SDBBP = 0x3F | EXT_SPECIAL2,
  181 +};
  182 +
  183 +/* Branch REGIMM */
  184 +enum {
  185 + OPC_BLTZ = 0x00 | EXT_REGIMM,
  186 + OPC_BLTZL = 0x02 | EXT_REGIMM,
  187 + OPC_BGEZ = 0x01 | EXT_REGIMM,
  188 + OPC_BGEZL = 0x03 | EXT_REGIMM,
  189 + OPC_BLTZAL = 0x10 | EXT_REGIMM,
  190 + OPC_BLTZALL = 0x12 | EXT_REGIMM,
  191 + OPC_BGEZAL = 0x11 | EXT_REGIMM,
  192 + OPC_BGEZALL = 0x13 | EXT_REGIMM,
  193 + OPC_TGEI = 0x08 | EXT_REGIMM,
  194 + OPC_TGEIU = 0x09 | EXT_REGIMM,
  195 + OPC_TLTI = 0x0A | EXT_REGIMM,
  196 + OPC_TLTIU = 0x0B | EXT_REGIMM,
  197 + OPC_TEQI = 0x0C | EXT_REGIMM,
  198 + OPC_TNEI = 0x0E | EXT_REGIMM,
  199 +};
  200 +
  201 +enum {
  202 + /* Coprocessor 0 (MMU) */
  203 + OPC_MFC0 = 0x00 | EXT_CP0,
  204 + OPC_MTC0 = 0x04 | EXT_CP0,
  205 + OPC_TLBR = 0x01 | EXT_CP0,
  206 + OPC_TLBWI = 0x02 | EXT_CP0,
  207 + OPC_TLBWR = 0x06 | EXT_CP0,
  208 + OPC_TLBP = 0x08 | EXT_CP0,
  209 + OPC_ERET = 0x18 | EXT_CP0,
  210 + OPC_DERET = 0x1F | EXT_CP0,
  211 + OPC_WAIT = 0x20 | EXT_CP0,
  212 +};
  213 +
46 214 const unsigned char *regnames[] =
47 215 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
48 216 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
... ...