gwj / at91sam9263 · Commits

Commit e36f36e15fbd0fca6074461a256a9c9ab4ea0afa

Authored by bellard
1 parent 7b17d41e

mmio support for vga registers - line offset fix - (aka XFree86 4.3.0 fixes) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@894 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 108 additions and 129 deletions
hw/cirrus_vga.c
  View file @e36f36e
... ... @@ -25,6 +25,8 @@
25 25 #include "vl.h"
26 26 #include "vga_int.h"
27 27  
  28 +//#define DEBUG_CIRRUS
  29 +
28 30 /***************************************
29 31 *
30 32 * definitions
... ... @@ -204,7 +206,7 @@ typedef void (*cirrus_bitblt_handler_t) (void *opaque);
204 206  
205 207 typedef struct CirrusVGAState {
206 208 /* XXX: we use the anonymous struct/union gcc 3.x extension */
207   - struct VGAState;
  209 + __extension__ struct VGAState;
208 210  
209 211 int cirrus_linear_io_addr;
210 212 int cirrus_mmio_io_addr;
... ... @@ -1036,7 +1038,7 @@ static void cirrus_get_offsets(VGAState *s1,
1036 1038 uint32_t line_offset;
1037 1039  
1038 1040 line_offset = s->cr[0x13]
1039   - | ((s->cr[0x1b] & 0x10) << 8);
  1041 + | ((s->cr[0x1b] & 0x10) << 4);
1040 1042 line_offset <<= 3;
1041 1043 *pline_offset = line_offset;
1042 1044  
... ... @@ -1821,31 +1823,6 @@ static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1821 1823  
1822 1824 /***************************************
1823 1825 *
1824   - * memory-mapped I/O (vga)
1825   - *
1826   - ***************************************/
1827   -
1828   -static uint8_t cirrus_mmio_vga_read(CirrusVGAState * s, unsigned address)
1829   -{
1830   -#ifdef DEBUG_CIRRUS
1831   - printf("cirrus: mmio vga read (unimplemented) - address 0x%04x\n",
1832   - address);
1833   -#endif
1834   - return 0xff;
1835   -}
1836   -
1837   -static void cirrus_mmio_vga_write(CirrusVGAState * s, unsigned address,
1838   - uint8_t value)
1839   -{
1840   -#ifdef DEBUG_CIRRUS
1841   - printf
1842   - ("cirrus: mmio vga write (unimplemented) - address 0x%04x, value 0x%02x\n",
1843   - address, value);
1844   -#endif
1845   -}
1846   -
1847   -/***************************************
1848   - *
1849 1826 * write mode 4/5
1850 1827 *
1851 1828 * assume TARGET_PAGE_SIZE >= 16
... ... @@ -2221,108 +2198,6 @@ static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2221 2198 cirrus_linear_writel,
2222 2199 };
2223 2200  
2224   -/***************************************
2225   - *
2226   - * memory-mapped I/O access
2227   - *
2228   - ***************************************/
2229   -
2230   -static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2231   -{
2232   - CirrusVGAState *s = (CirrusVGAState *) opaque;
2233   -
2234   - addr &= CIRRUS_PNPMMIO_SIZE - 1;
2235   - /* ??? Does CLGD5430 have memory-mapped VGA registers ??? */
2236   - return (addr >= 0x100) ?
2237   - cirrus_mmio_blt_read(s, addr - 0x100) :
2238   - cirrus_mmio_vga_read(s, addr);
2239   -}
2240   -
2241   -static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2242   -{
2243   - uint32_t v;
2244   -#ifdef TARGET_WORDS_BIGENDIAN
2245   - v = cirrus_mmio_readb(opaque, addr) << 8;
2246   - v |= cirrus_mmio_readb(opaque, addr + 1);
2247   -#else
2248   - v = cirrus_mmio_readb(opaque, addr);
2249   - v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2250   -#endif
2251   - return v;
2252   -}
2253   -
2254   -static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2255   -{
2256   - uint32_t v;
2257   -#ifdef TARGET_WORDS_BIGENDIAN
2258   - v = cirrus_mmio_readb(opaque, addr) << 24;
2259   - v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2260   - v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2261   - v |= cirrus_mmio_readb(opaque, addr + 3);
2262   -#else
2263   - v = cirrus_mmio_readb(opaque, addr);
2264   - v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2265   - v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2266   - v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2267   -#endif
2268   - return v;
2269   -}
2270   -
2271   -static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2272   - uint32_t val)
2273   -{
2274   - CirrusVGAState *s = (CirrusVGAState *) opaque;
2275   -
2276   - addr &= CIRRUS_PNPMMIO_SIZE - 1;
2277   - /* ??? Does CLGD5430 have memory-mapped VGA registers ??? */
2278   - if (addr >= 0x100) {
2279   - cirrus_mmio_blt_write(s, addr - 0x100, val);
2280   - } else {
2281   - cirrus_mmio_vga_write(s, addr, val);
2282   - }
2283   -}
2284   -
2285   -static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2286   - uint32_t val)
2287   -{
2288   -#ifdef TARGET_WORDS_BIGENDIAN
2289   - cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2290   - cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2291   -#else
2292   - cirrus_mmio_writeb(opaque, addr, val & 0xff);
2293   - cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2294   -#endif
2295   -}
2296   -
2297   -static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2298   - uint32_t val)
2299   -{
2300   -#ifdef TARGET_WORDS_BIGENDIAN
2301   - cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2302   - cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2303   - cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2304   - cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2305   -#else
2306   - cirrus_mmio_writeb(opaque, addr, val & 0xff);
2307   - cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2308   - cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2309   - cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2310   -#endif
2311   -}
2312   -
2313   -
2314   -static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
2315   - cirrus_mmio_readb,
2316   - cirrus_mmio_readw,
2317   - cirrus_mmio_readl,
2318   -};
2319   -
2320   -static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
2321   - cirrus_mmio_writeb,
2322   - cirrus_mmio_writew,
2323   - cirrus_mmio_writel,
2324   -};
2325   -
2326 2201 /* I/O ports */
2327 2202  
2328 2203 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
... ... @@ -2570,6 +2445,110 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2570 2445  
2571 2446 /***************************************
2572 2447 *
  2448 + * memory-mapped I/O access
  2449 + *
  2450 + ***************************************/
  2451 +
  2452 +static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
  2453 +{
  2454 + CirrusVGAState *s = (CirrusVGAState *) opaque;
  2455 +
  2456 + addr &= CIRRUS_PNPMMIO_SIZE - 1;
  2457 +
  2458 + if (addr >= 0x100) {
  2459 + return cirrus_mmio_blt_read(s, addr - 0x100);
  2460 + } else {
  2461 + return vga_ioport_read(s, addr + 0x3c0);
  2462 + }
  2463 +}
  2464 +
  2465 +static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
  2466 +{
  2467 + uint32_t v;
  2468 +#ifdef TARGET_WORDS_BIGENDIAN
  2469 + v = cirrus_mmio_readb(opaque, addr) << 8;
  2470 + v |= cirrus_mmio_readb(opaque, addr + 1);
  2471 +#else
  2472 + v = cirrus_mmio_readb(opaque, addr);
  2473 + v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
  2474 +#endif
  2475 + return v;
  2476 +}
  2477 +
  2478 +static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
  2479 +{
  2480 + uint32_t v;
  2481 +#ifdef TARGET_WORDS_BIGENDIAN
  2482 + v = cirrus_mmio_readb(opaque, addr) << 24;
  2483 + v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
  2484 + v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
  2485 + v |= cirrus_mmio_readb(opaque, addr + 3);
  2486 +#else
  2487 + v = cirrus_mmio_readb(opaque, addr);
  2488 + v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
  2489 + v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
  2490 + v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
  2491 +#endif
  2492 + return v;
  2493 +}
  2494 +
  2495 +static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
  2496 + uint32_t val)
  2497 +{
  2498 + CirrusVGAState *s = (CirrusVGAState *) opaque;
  2499 +
  2500 + addr &= CIRRUS_PNPMMIO_SIZE - 1;
  2501 +
  2502 + if (addr >= 0x100) {
  2503 + cirrus_mmio_blt_write(s, addr - 0x100, val);
  2504 + } else {
  2505 + vga_ioport_write(s, addr + 0x3c0, val);
  2506 + }
  2507 +}
  2508 +
  2509 +static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
  2510 + uint32_t val)
  2511 +{
  2512 +#ifdef TARGET_WORDS_BIGENDIAN
  2513 + cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
  2514 + cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
  2515 +#else
  2516 + cirrus_mmio_writeb(opaque, addr, val & 0xff);
  2517 + cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
  2518 +#endif
  2519 +}
  2520 +
  2521 +static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
  2522 + uint32_t val)
  2523 +{
  2524 +#ifdef TARGET_WORDS_BIGENDIAN
  2525 + cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
  2526 + cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
  2527 + cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
  2528 + cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
  2529 +#else
  2530 + cirrus_mmio_writeb(opaque, addr, val & 0xff);
  2531 + cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
  2532 + cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
  2533 + cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
  2534 +#endif
  2535 +}
  2536 +
  2537 +
  2538 +static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
  2539 + cirrus_mmio_readb,
  2540 + cirrus_mmio_readw,
  2541 + cirrus_mmio_readl,
  2542 +};
  2543 +
  2544 +static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
  2545 + cirrus_mmio_writeb,
  2546 + cirrus_mmio_writew,
  2547 + cirrus_mmio_writel,
  2548 +};
  2549 +
  2550 +/***************************************
  2551 + *
2573 2552 * initialize
2574 2553 *
2575 2554 ***************************************/
... ...