Commit e32cba29beb079165ddcd01a45242a8ac010319c
1 parent
7fc06735
Sparc32: convert Sun4c interrupt controller to qdev
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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3 changed files
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57 additions
and
20 deletions
hw/sun4c_intctl.c
| ... | ... | @@ -21,9 +21,12 @@ |
| 21 | 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | 22 | * THE SOFTWARE. |
| 23 | 23 | */ |
| 24 | + | |
| 24 | 25 | #include "hw.h" |
| 25 | 26 | #include "sun4m.h" |
| 26 | 27 | #include "monitor.h" |
| 28 | +#include "sysbus.h" | |
| 29 | + | |
| 27 | 30 | //#define DEBUG_IRQ_COUNT |
| 28 | 31 | //#define DEBUG_IRQ |
| 29 | 32 | |
| ... | ... | @@ -42,10 +45,11 @@ |
| 42 | 45 | #define MAX_PILS 16 |
| 43 | 46 | |
| 44 | 47 | typedef struct Sun4c_INTCTLState { |
| 48 | + SysBusDevice busdev; | |
| 45 | 49 | #ifdef DEBUG_IRQ_COUNT |
| 46 | 50 | uint64_t irq_count; |
| 47 | 51 | #endif |
| 48 | - qemu_irq *cpu_irqs; | |
| 52 | + qemu_irq cpu_irqs[MAX_PILS]; | |
| 49 | 53 | const uint32_t *intbit_to_level; |
| 50 | 54 | uint32_t pil_out; |
| 51 | 55 | uint8_t reg; |
| ... | ... | @@ -194,25 +198,54 @@ static void sun4c_intctl_reset(void *opaque) |
| 194 | 198 | s->pending = 0; |
| 195 | 199 | } |
| 196 | 200 | |
| 197 | -void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, | |
| 198 | - qemu_irq *parent_irq) | |
| 201 | +DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq) | |
| 199 | 202 | { |
| 200 | - int sun4c_intctl_io_memory; | |
| 201 | - Sun4c_INTCTLState *s; | |
| 203 | + DeviceState *dev; | |
| 204 | + SysBusDevice *s; | |
| 205 | + unsigned int i; | |
| 202 | 206 | |
| 203 | - s = qemu_mallocz(sizeof(Sun4c_INTCTLState)); | |
| 207 | + dev = qdev_create(NULL, "sun4c_intctl"); | |
| 208 | + qdev_init(dev); | |
| 204 | 209 | |
| 205 | - sun4c_intctl_io_memory = cpu_register_io_memory(sun4c_intctl_mem_read, | |
| 206 | - sun4c_intctl_mem_write, s); | |
| 207 | - cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory); | |
| 208 | - s->cpu_irqs = parent_irq; | |
| 210 | + s = sysbus_from_qdev(dev); | |
| 209 | 211 | |
| 210 | - register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save, | |
| 211 | - sun4c_intctl_load, s); | |
| 212 | + for (i = 0; i < MAX_PILS; i++) { | |
| 213 | + sysbus_connect_irq(s, i, parent_irq[i]); | |
| 214 | + } | |
| 215 | + sysbus_mmio_map(s, 0, addr); | |
| 212 | 216 | |
| 213 | - qemu_register_reset(sun4c_intctl_reset, s); | |
| 214 | - *irq = qemu_allocate_irqs(sun4c_set_irq, s, 8); | |
| 217 | + return dev; | |
| 218 | +} | |
| 219 | + | |
| 220 | +static void sun4c_intctl_init1(SysBusDevice *dev) | |
| 221 | +{ | |
| 222 | + Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev); | |
| 223 | + int io_memory; | |
| 224 | + unsigned int i; | |
| 215 | 225 | |
| 226 | + io_memory = cpu_register_io_memory(sun4c_intctl_mem_read, | |
| 227 | + sun4c_intctl_mem_write, s); | |
| 228 | + sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); | |
| 229 | + qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8); | |
| 230 | + | |
| 231 | + for (i = 0; i < MAX_PILS; i++) { | |
| 232 | + sysbus_init_irq(dev, &s->cpu_irqs[i]); | |
| 233 | + } | |
| 234 | + register_savevm("sun4c_intctl", -1, 1, sun4c_intctl_save, | |
| 235 | + sun4c_intctl_load, s); | |
| 236 | + qemu_register_reset(sun4c_intctl_reset, s); | |
| 216 | 237 | sun4c_intctl_reset(s); |
| 217 | - return s; | |
| 218 | 238 | } |
| 239 | + | |
| 240 | +static SysBusDeviceInfo sun4c_intctl_info = { | |
| 241 | + .init = sun4c_intctl_init1, | |
| 242 | + .qdev.name = "sun4c_intctl", | |
| 243 | + .qdev.size = sizeof(Sun4c_INTCTLState), | |
| 244 | +}; | |
| 245 | + | |
| 246 | +static void sun4c_intctl_register_devices(void) | |
| 247 | +{ | |
| 248 | + sysbus_register_withprop(&sun4c_intctl_info); | |
| 249 | +} | |
| 250 | + | |
| 251 | +device_init(sun4c_intctl_register_devices) | ... | ... |
hw/sun4m.c
| ... | ... | @@ -1502,13 +1502,15 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
| 1502 | 1502 | { |
| 1503 | 1503 | CPUState *env; |
| 1504 | 1504 | void *iommu, *espdma, *ledma, *nvram; |
| 1505 | - qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq; | |
| 1505 | + qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq; | |
| 1506 | 1506 | qemu_irq *esp_reset, *le_reset; |
| 1507 | 1507 | qemu_irq fdc_tc; |
| 1508 | 1508 | unsigned long kernel_size; |
| 1509 | 1509 | BlockDriverState *fd[MAX_FD]; |
| 1510 | 1510 | int drive_index; |
| 1511 | 1511 | void *fw_cfg; |
| 1512 | + DeviceState *dev; | |
| 1513 | + unsigned int i; | |
| 1512 | 1514 | |
| 1513 | 1515 | /* init CPU */ |
| 1514 | 1516 | if (!cpu_model) |
| ... | ... | @@ -1521,8 +1523,11 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
| 1521 | 1523 | |
| 1522 | 1524 | prom_init(hwdef->slavio_base, bios_name); |
| 1523 | 1525 | |
| 1524 | - slavio_intctl = sun4c_intctl_init(hwdef->intctl_base, | |
| 1525 | - &slavio_irq, cpu_irqs); | |
| 1526 | + dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); | |
| 1527 | + | |
| 1528 | + for (i = 0; i < 8; i++) { | |
| 1529 | + slavio_irq[i] = qdev_get_gpio_in(dev, i); | |
| 1530 | + } | |
| 1526 | 1531 | |
| 1527 | 1532 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
| 1528 | 1533 | slavio_irq[hwdef->me_irq]); | ... | ... |
hw/sun4m.h
| ... | ... | @@ -39,8 +39,7 @@ void slavio_irq_info(Monitor *mon, void *opaque); |
| 39 | 39 | DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq); |
| 40 | 40 | |
| 41 | 41 | /* sun4c_intctl.c */ |
| 42 | -void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, | |
| 43 | - qemu_irq *parent_irq); | |
| 42 | +DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq); | |
| 44 | 43 | void sun4c_pic_info(Monitor *mon, void *opaque); |
| 45 | 44 | void sun4c_irq_info(Monitor *mon, void *opaque); |
| 46 | 45 | ... | ... |