Commit e30b46789326eaa7fb1f870f0c7d964263851216
1 parent
75d0187a
MicroSparc I didn't have fsmuld op
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4618 c046a42c-6fe2-441c-8c8c-71466251a162
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3 changed files
with
19 additions
and
9 deletions
target-sparc/cpu.h
| ... | ... | @@ -284,17 +284,18 @@ typedef struct CPUSPARCState { |
| 284 | 284 | #define CPU_FEATURE_FMUL (1 << 7) |
| 285 | 285 | #define CPU_FEATURE_VIS1 (1 << 8) |
| 286 | 286 | #define CPU_FEATURE_VIS2 (1 << 9) |
| 287 | +#define CPU_FEATURE_FSMULD (1 << 10) | |
| 287 | 288 | #ifndef TARGET_SPARC64 |
| 288 | 289 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ |
| 289 | 290 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
| 290 | 291 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
| 291 | - CPU_FEATURE_FMUL) | |
| 292 | + CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) | |
| 292 | 293 | #else |
| 293 | 294 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ |
| 294 | 295 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
| 295 | 296 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
| 296 | 297 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ |
| 297 | - CPU_FEATURE_VIS2) | |
| 298 | + CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) | |
| 298 | 299 | #endif |
| 299 | 300 | |
| 300 | 301 | #if defined(TARGET_SPARC64) | ... | ... |
target-sparc/helper.c
| ... | ... | @@ -1098,7 +1098,7 @@ static const sparc_def_t sparc_defs[] = { |
| 1098 | 1098 | .mmu_cxr_mask = 0x0000003f, |
| 1099 | 1099 | .mmu_sfsr_mask = 0xffffffff, |
| 1100 | 1100 | .mmu_trcr_mask = 0xffffffff, |
| 1101 | - .features = CPU_FEATURE_FLOAT, | |
| 1101 | + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, | |
| 1102 | 1102 | }, |
| 1103 | 1103 | { |
| 1104 | 1104 | .name = "Fujitsu MB86904", |
| ... | ... | @@ -1134,7 +1134,8 @@ static const sparc_def_t sparc_defs[] = { |
| 1134 | 1134 | .mmu_cxr_mask = 0x0000003f, |
| 1135 | 1135 | .mmu_sfsr_mask = 0xffffffff, |
| 1136 | 1136 | .mmu_trcr_mask = 0xffffffff, |
| 1137 | - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, | |
| 1137 | + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | | |
| 1138 | + CPU_FEATURE_FSMULD, | |
| 1138 | 1139 | }, |
| 1139 | 1140 | { |
| 1140 | 1141 | .name = "Cypress CY7C601", |
| ... | ... | @@ -1146,7 +1147,8 @@ static const sparc_def_t sparc_defs[] = { |
| 1146 | 1147 | .mmu_cxr_mask = 0x0000003f, |
| 1147 | 1148 | .mmu_sfsr_mask = 0xffffffff, |
| 1148 | 1149 | .mmu_trcr_mask = 0xffffffff, |
| 1149 | - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, | |
| 1150 | + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | | |
| 1151 | + CPU_FEATURE_FSMULD, | |
| 1150 | 1152 | }, |
| 1151 | 1153 | { |
| 1152 | 1154 | .name = "Cypress CY7C611", |
| ... | ... | @@ -1158,7 +1160,8 @@ static const sparc_def_t sparc_defs[] = { |
| 1158 | 1160 | .mmu_cxr_mask = 0x0000003f, |
| 1159 | 1161 | .mmu_sfsr_mask = 0xffffffff, |
| 1160 | 1162 | .mmu_trcr_mask = 0xffffffff, |
| 1161 | - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, | |
| 1163 | + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | | |
| 1164 | + CPU_FEATURE_FSMULD, | |
| 1162 | 1165 | }, |
| 1163 | 1166 | { |
| 1164 | 1167 | .name = "TI SuperSparc II", |
| ... | ... | @@ -1182,7 +1185,9 @@ static const sparc_def_t sparc_defs[] = { |
| 1182 | 1185 | .mmu_cxr_mask = 0x0000003f, |
| 1183 | 1186 | .mmu_sfsr_mask = 0x00016fff, |
| 1184 | 1187 | .mmu_trcr_mask = 0x0000003f, |
| 1185 | - .features = CPU_DEFAULT_FEATURES, | |
| 1188 | + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | | |
| 1189 | + CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | | |
| 1190 | + CPU_FEATURE_FMUL, | |
| 1186 | 1191 | }, |
| 1187 | 1192 | { |
| 1188 | 1193 | .name = "TI MicroSparc II", |
| ... | ... | @@ -1266,7 +1271,8 @@ static const sparc_def_t sparc_defs[] = { |
| 1266 | 1271 | .mmu_cxr_mask = 0x0000003f, |
| 1267 | 1272 | .mmu_sfsr_mask = 0xffffffff, |
| 1268 | 1273 | .mmu_trcr_mask = 0xffffffff, |
| 1269 | - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT, | |
| 1274 | + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | | |
| 1275 | + CPU_FEATURE_FSMULD, | |
| 1270 | 1276 | }, |
| 1271 | 1277 | { |
| 1272 | 1278 | .name = "Matsushita MN10501", |
| ... | ... | @@ -1278,7 +1284,8 @@ static const sparc_def_t sparc_defs[] = { |
| 1278 | 1284 | .mmu_cxr_mask = 0x0000003f, |
| 1279 | 1285 | .mmu_sfsr_mask = 0xffffffff, |
| 1280 | 1286 | .mmu_trcr_mask = 0xffffffff, |
| 1281 | - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT, | |
| 1287 | + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | | |
| 1288 | + CPU_FEATURE_FSMULD, | |
| 1282 | 1289 | }, |
| 1283 | 1290 | { |
| 1284 | 1291 | .name = "Weitek W8601", |
| ... | ... | @@ -1330,6 +1337,7 @@ static const char * const feature_name[] = { |
| 1330 | 1337 | "fmul", |
| 1331 | 1338 | "vis1", |
| 1332 | 1339 | "vis2", |
| 1340 | + "fsmuld", | |
| 1333 | 1341 | }; |
| 1334 | 1342 | |
| 1335 | 1343 | static void print_features(FILE *f, | ... | ... |
target-sparc/translate.c
| ... | ... | @@ -2511,6 +2511,7 @@ static void disas_sparc_insn(DisasContext * dc) |
| 2511 | 2511 | gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2512 | 2512 | break; |
| 2513 | 2513 | case 0x69: |
| 2514 | + CHECK_FPU_FEATURE(dc, FSMULD); | |
| 2514 | 2515 | gen_op_load_fpr_FT0(rs1); |
| 2515 | 2516 | gen_op_load_fpr_FT1(rs2); |
| 2516 | 2517 | gen_clear_float_exceptions(); | ... | ... |