Commit e214b9bb55b20480c4f7a6f4db2d929332cf8c19
1 parent
e8996ee0
Switch MIPS movf/movt to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4545 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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22 additions
and
23 deletions
target-mips/op.c
| @@ -460,21 +460,6 @@ void op_dmultu (void) | @@ -460,21 +460,6 @@ void op_dmultu (void) | ||
| 460 | } | 460 | } |
| 461 | #endif | 461 | #endif |
| 462 | 462 | ||
| 463 | -/* Conditional moves */ | ||
| 464 | -void op_movf (void) | ||
| 465 | -{ | ||
| 466 | - if (!(env->fpu->fcr31 & PARAM1)) | ||
| 467 | - T0 = T1; | ||
| 468 | - FORCE_RET(); | ||
| 469 | -} | ||
| 470 | - | ||
| 471 | -void op_movt (void) | ||
| 472 | -{ | ||
| 473 | - if (env->fpu->fcr31 & PARAM1) | ||
| 474 | - T0 = T1; | ||
| 475 | - FORCE_RET(); | ||
| 476 | -} | ||
| 477 | - | ||
| 478 | /* CP0 functions */ | 463 | /* CP0 functions */ |
| 479 | void op_mfc0_index (void) | 464 | void op_mfc0_index (void) |
| 480 | { | 465 | { |
target-mips/translate.c
| @@ -5450,19 +5450,33 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) | @@ -5450,19 +5450,33 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) | ||
| 5450 | 5450 | ||
| 5451 | static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) | 5451 | static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) |
| 5452 | { | 5452 | { |
| 5453 | + TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR); | ||
| 5454 | + TCGv r_tmp = new_tmp(); | ||
| 5455 | + TCGv t0 = tcg_temp_new(TCG_TYPE_TL); | ||
| 5456 | + TCGv t1 = tcg_temp_new(TCG_TYPE_TL); | ||
| 5457 | + int l1 = gen_new_label(); | ||
| 5453 | uint32_t ccbit; | 5458 | uint32_t ccbit; |
| 5459 | + TCGCond cond; | ||
| 5454 | 5460 | ||
| 5455 | - gen_load_gpr(cpu_T[0], rd); | ||
| 5456 | - gen_load_gpr(cpu_T[1], rs); | ||
| 5457 | - if (cc) { | 5461 | + if (cc) |
| 5458 | ccbit = 1 << (24 + cc); | 5462 | ccbit = 1 << (24 + cc); |
| 5459 | - } else | 5463 | + else |
| 5460 | ccbit = 1 << 23; | 5464 | ccbit = 1 << 23; |
| 5461 | - if (!tf) | ||
| 5462 | - gen_op_movf(ccbit); | 5465 | + if (tf) |
| 5466 | + cond = TCG_COND_NE; | ||
| 5463 | else | 5467 | else |
| 5464 | - gen_op_movt(ccbit); | ||
| 5465 | - gen_store_gpr(cpu_T[0], rd); | 5468 | + cond = TCG_COND_EQ; |
| 5469 | + | ||
| 5470 | + gen_load_gpr(t0, rd); | ||
| 5471 | + gen_load_gpr(t1, rs); | ||
| 5472 | + tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu)); | ||
| 5473 | + tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31)); | ||
| 5474 | + tcg_gen_andi_i32(r_tmp, r_tmp, ccbit); | ||
| 5475 | + tcg_gen_brcond_i32(cond, r_tmp, tcg_const_i32(0), l1); | ||
| 5476 | + tcg_gen_mov_tl(t0, t1); | ||
| 5477 | + gen_set_label(l1); | ||
| 5478 | + dead_tmp(r_tmp); | ||
| 5479 | + gen_store_gpr(t0, rd); | ||
| 5466 | } | 5480 | } |
| 5467 | 5481 | ||
| 5468 | #define GEN_MOVCF(fmt) \ | 5482 | #define GEN_MOVCF(fmt) \ |