gwj / at91sam9263 · Commits

Commit e1f3808e03f73e7a7fa966afbed2455dd052202e

Authored by pbrook
1 parent 3979144c

Convert m68k target to TCG. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4565 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 11 changed files with 1574 additions and 2352 deletions
configure
  View file @e1f3808
... ... @@ -1237,10 +1237,8 @@ case "$target_cpu" in
1237 1237 ;;
1238 1238 m68k)
1239 1239 echo "TARGET_ARCH=m68k" >> $config_mak
1240   - echo "CONFIG_DYNGEN_OP=yes" >> $config_mak
1241 1240 echo "#define TARGET_ARCH \"m68k\"" >> $config_h
1242 1241 echo "#define TARGET_M68K 1" >> $config_h
1243   - echo "#define CONFIG_DYNGEN_OP 1" >> $config_h
1244 1242 bflt="yes"
1245 1243 ;;
1246 1244 mips|mipsel)
... ...
target-m68k/cpu.h
  View file @e1f3808
... ... @@ -108,7 +108,7 @@ typedef struct CPUM68KState {
108 108 int exception_index;
109 109 int interrupt_request;
110 110 int user_mode_only;
111   - int halted;
  111 + uint32_t halted;
112 112  
113 113 int pending_vector;
114 114 int pending_level;
... ... @@ -120,6 +120,7 @@ typedef struct CPUM68KState {
120 120 uint32_t features;
121 121 } CPUM68KState;
122 122  
  123 +void m68k_tcg_init(void);
123 124 CPUM68KState *cpu_m68k_init(const char *cpu_model);
124 125 int cpu_m68k_exec(CPUM68KState *s);
125 126 void cpu_m68k_close(CPUM68KState *s);
... ... @@ -141,9 +142,7 @@ enum {
141 142 CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
142 143 CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
143 144 CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
144   - CC_OP_SHL, /* CC_DEST = source, CC_SRC = shift */
145   - CC_OP_SHR, /* CC_DEST = source, CC_SRC = shift */
146   - CC_OP_SAR, /* CC_DEST = source, CC_SRC = shift */
  145 + CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
147 146 };
148 147  
149 148 #define CCF_C 0x01
... ...
target-m68k/exec.h
  View file @e1f3808
... ... @@ -45,8 +45,6 @@ int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
45 45 #endif
46 46  
47 47 void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op);
48   -float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1);
49   -void helper_movec(CPUM68KState *env, int reg, uint32_t val);
50 48  
51 49 void cpu_loop_exit(void);
52 50  
... ...
target-m68k/helper.c
  View file @e1f3808
... ... @@ -27,6 +27,10 @@
27 27 #include "exec-all.h"
28 28 #include "qemu-common.h"
29 29  
  30 +#include "helpers.h"
  31 +
  32 +#define SIGNBIT (1u << 31)
  33 +
30 34 enum m68k_cpuid {
31 35 M68K_CPUID_M5206,
32 36 M68K_CPUID_M5208,
... ... @@ -121,11 +125,16 @@ void cpu_reset(CPUM68KState *env)
121 125 CPUM68KState *cpu_m68k_init(const char *cpu_model)
122 126 {
123 127 CPUM68KState *env;
  128 + static int inited;
124 129  
125 130 env = malloc(sizeof(CPUM68KState));
126 131 if (!env)
127 132 return NULL;
128 133 cpu_exec_init(env);
  134 + if (!inited) {
  135 + inited = 1;
  136 + m68k_tcg_init();
  137 + }
129 138  
130 139 env->cpu_model_str = cpu_model;
131 140  
... ... @@ -211,34 +220,9 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
211 220 if (HIGHBIT & (tmp ^ dest) & (tmp ^ src))
212 221 flags |= CCF_V;
213 222 break;
214   - case CC_OP_SHL:
215   - if (src >= 32) {
216   - SET_NZ(0);
217   - } else {
218   - tmp = dest << src;
219   - SET_NZ(tmp);
220   - }
221   - if (src && src <= 32 && (dest & (1 << (32 - src))))
222   - flags |= CCF_C;
223   - break;
224   - case CC_OP_SHR:
225   - if (src >= 32) {
226   - SET_NZ(0);
227   - } else {
228   - tmp = dest >> src;
229   - SET_NZ(tmp);
230   - }
231   - if (src && src <= 32 && ((dest >> (src - 1)) & 1))
232   - flags |= CCF_C;
233   - break;
234   - case CC_OP_SAR:
235   - if (src >= 32) {
236   - SET_NZ(-1);
237   - } else {
238   - tmp = (int32_t)dest >> src;
239   - SET_NZ(tmp);
240   - }
241   - if (src && src <= 32 && (((int32_t)dest >> (src - 1)) & 1))
  223 + case CC_OP_SHIFT:
  224 + SET_NZ(dest);
  225 + if (src)
242 226 flags |= CCF_C;
243 227 break;
244 228 default:
... ... @@ -248,25 +232,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
248 232 env->cc_dest = flags;
249 233 }
250 234  
251   -float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1)
252   -{
253   - /* ??? This may incorrectly raise exceptions. */
254   - /* ??? Should flush denormals to zero. */
255   - float64 res;
256   - res = float64_sub(src0, src1, &env->fp_status);
257   - if (float64_is_nan(res)) {
258   - /* +/-inf compares equal against itself, but sub returns nan. */
259   - if (!float64_is_nan(src0)
260   - && !float64_is_nan(src1)) {
261   - res = float64_zero;
262   - if (float64_lt_quiet(src0, res, &env->fp_status))
263   - res = float64_chs(res);
264   - }
265   - }
266   - return res;
267   -}
268   -
269   -void helper_movec(CPUM68KState *env, int reg, uint32_t val)
  235 +void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
270 236 {
271 237 switch (reg) {
272 238 case 0x02: /* CACR */
... ... @@ -286,7 +252,7 @@ void helper_movec(CPUM68KState *env, int reg, uint32_t val)
286 252 }
287 253 }
288 254  
289   -void m68k_set_macsr(CPUM68KState *env, uint32_t val)
  255 +void HELPER(set_macsr)(CPUM68KState *env, uint32_t val)
290 256 {
291 257 uint32_t acc;
292 258 int8_t exthigh;
... ... @@ -376,3 +342,541 @@ void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector)
376 342 }
377 343  
378 344 #endif
  345 +
  346 +uint32_t HELPER(bitrev)(uint32_t x)
  347 +{
  348 + x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau);
  349 + x = ((x >> 2) & 0x33333333u) | ((x << 2) & 0xccccccccu);
  350 + x = ((x >> 4) & 0x0f0f0f0fu) | ((x << 4) & 0xf0f0f0f0u);
  351 + return bswap32(x);
  352 +}
  353 +
  354 +uint32_t HELPER(ff1)(uint32_t x)
  355 +{
  356 + int n;
  357 + for (n = 32; x; n--)
  358 + x >>= 1;
  359 + return n;
  360 +}
  361 +
  362 +uint32_t HELPER(sats)(uint32_t val, uint32_t ccr)
  363 +{
  364 + /* The result has the opposite sign to the original value. */
  365 + if (ccr & CCF_V)
  366 + val = (((int32_t)val) >> 31) ^ SIGNBIT;
  367 + return val;
  368 +}
  369 +
  370 +uint32_t HELPER(subx_cc)(CPUState *env, uint32_t op1, uint32_t op2)
  371 +{
  372 + uint32_t res;
  373 + uint32_t old_flags;
  374 +
  375 + old_flags = env->cc_dest;
  376 + if (env->cc_x) {
  377 + env->cc_x = (op1 <= op2);
  378 + env->cc_op = CC_OP_SUBX;
  379 + res = op1 - (op2 + 1);
  380 + } else {
  381 + env->cc_x = (op1 < op2);
  382 + env->cc_op = CC_OP_SUB;
  383 + res = op1 - op2;
  384 + }
  385 + env->cc_dest = res;
  386 + env->cc_src = op2;
  387 + cpu_m68k_flush_flags(env, env->cc_op);
  388 + /* !Z is sticky. */
  389 + env->cc_dest &= (old_flags | ~CCF_Z);
  390 + return res;
  391 +}
  392 +
  393 +uint32_t HELPER(addx_cc)(CPUState *env, uint32_t op1, uint32_t op2)
  394 +{
  395 + uint32_t res;
  396 + uint32_t old_flags;
  397 +
  398 + old_flags = env->cc_dest;
  399 + if (env->cc_x) {
  400 + res = op1 + op2 + 1;
  401 + env->cc_x = (res <= op2);
  402 + env->cc_op = CC_OP_ADDX;
  403 + } else {
  404 + res = op1 + op2;
  405 + env->cc_x = (res < op2);
  406 + env->cc_op = CC_OP_ADD;
  407 + }
  408 + env->cc_dest = res;
  409 + env->cc_src = op2;
  410 + cpu_m68k_flush_flags(env, env->cc_op);
  411 + /* !Z is sticky. */
  412 + env->cc_dest &= (old_flags | ~CCF_Z);
  413 + return res;
  414 +}
  415 +
  416 +uint32_t HELPER(xflag_lt)(uint32_t a, uint32_t b)
  417 +{
  418 + return a < b;
  419 +}
  420 +
  421 +uint32_t HELPER(btest)(uint32_t x)
  422 +{
  423 + return x != 0;
  424 +}
  425 +
  426 +void HELPER(set_sr)(CPUState *env, uint32_t val)
  427 +{
  428 + env->sr = val & 0xffff;
  429 + m68k_switch_sp(env);
  430 +}
  431 +
  432 +uint32_t HELPER(shl_cc)(CPUState *env, uint32_t val, uint32_t shift)
  433 +{
  434 + uint32_t result;
  435 + uint32_t cf;
  436 +
  437 + shift &= 63;
  438 + if (shift == 0) {
  439 + result = val;
  440 + cf = env->cc_src & CCF_C;
  441 + } else if (shift < 32) {
  442 + result = val << shift;
  443 + cf = (val >> (32 - shift)) & 1;
  444 + } else if (shift == 32) {
  445 + result = 0;
  446 + cf = val & 1;
  447 + } else /* shift > 32 */ {
  448 + result = 0;
  449 + cf = 0;
  450 + }
  451 + env->cc_src = cf;
  452 + env->cc_x = (cf != 0);
  453 + env->cc_dest = result;
  454 + return result;
  455 +}
  456 +
  457 +uint32_t HELPER(shr_cc)(CPUState *env, uint32_t val, uint32_t shift)
  458 +{
  459 + uint32_t result;
  460 + uint32_t cf;
  461 +
  462 + shift &= 63;
  463 + if (shift == 0) {
  464 + result = val;
  465 + cf = env->cc_src & CCF_C;
  466 + } else if (shift < 32) {
  467 + result = val >> shift;
  468 + cf = (val >> (shift - 1)) & 1;
  469 + } else if (shift == 32) {
  470 + result = 0;
  471 + cf = val >> 31;
  472 + } else /* shift > 32 */ {
  473 + result = 0;
  474 + cf = 0;
  475 + }
  476 + env->cc_src = cf;
  477 + env->cc_x = (cf != 0);
  478 + env->cc_dest = result;
  479 + return result;
  480 +}
  481 +
  482 +uint32_t HELPER(sar_cc)(CPUState *env, uint32_t val, uint32_t shift)
  483 +{
  484 + uint32_t result;
  485 + uint32_t cf;
  486 +
  487 + shift &= 63;
  488 + if (shift == 0) {
  489 + result = val;
  490 + cf = (env->cc_src & CCF_C) != 0;
  491 + } else if (shift < 32) {
  492 + result = (int32_t)val >> shift;
  493 + cf = (val >> (shift - 1)) & 1;
  494 + } else /* shift >= 32 */ {
  495 + result = (int32_t)val >> 31;
  496 + cf = val >> 31;
  497 + }
  498 + env->cc_src = cf;
  499 + env->cc_x = cf;
  500 + env->cc_dest = result;
  501 + return result;
  502 +}
  503 +
  504 +/* FPU helpers. */
  505 +uint32_t HELPER(f64_to_i32)(CPUState *env, float64 val)
  506 +{
  507 + return float64_to_int32(val, &env->fp_status);
  508 +}
  509 +
  510 +float32 HELPER(f64_to_f32)(CPUState *env, float64 val)
  511 +{
  512 + return float64_to_float32(val, &env->fp_status);
  513 +}
  514 +
  515 +float64 HELPER(i32_to_f64)(CPUState *env, uint32_t val)
  516 +{
  517 + return int32_to_float64(val, &env->fp_status);
  518 +}
  519 +
  520 +float64 HELPER(f32_to_f64)(CPUState *env, float32 val)
  521 +{
  522 + return float32_to_float64(val, &env->fp_status);
  523 +}
  524 +
  525 +float64 HELPER(iround_f64)(CPUState *env, float64 val)
  526 +{
  527 + return float64_round_to_int(val, &env->fp_status);
  528 +}
  529 +
  530 +float64 HELPER(itrunc_f64)(CPUState *env, float64 val)
  531 +{
  532 + return float64_trunc_to_int(val, &env->fp_status);
  533 +}
  534 +
  535 +float64 HELPER(sqrt_f64)(CPUState *env, float64 val)
  536 +{
  537 + return float64_sqrt(val, &env->fp_status);
  538 +}
  539 +
  540 +float64 HELPER(abs_f64)(float64 val)
  541 +{
  542 + return float64_abs(val);
  543 +}
  544 +
  545 +float64 HELPER(chs_f64)(float64 val)
  546 +{
  547 + return float64_chs(val);
  548 +}
  549 +
  550 +float64 HELPER(add_f64)(CPUState *env, float64 a, float64 b)
  551 +{
  552 + return float64_add(a, b, &env->fp_status);
  553 +}
  554 +
  555 +float64 HELPER(sub_f64)(CPUState *env, float64 a, float64 b)
  556 +{
  557 + return float64_sub(a, b, &env->fp_status);
  558 +}
  559 +
  560 +float64 HELPER(mul_f64)(CPUState *env, float64 a, float64 b)
  561 +{
  562 + return float64_mul(a, b, &env->fp_status);
  563 +}
  564 +
  565 +float64 HELPER(div_f64)(CPUState *env, float64 a, float64 b)
  566 +{
  567 + return float64_div(a, b, &env->fp_status);
  568 +}
  569 +
  570 +float64 HELPER(sub_cmp_f64)(CPUState *env, float64 a, float64 b)
  571 +{
  572 + /* ??? This may incorrectly raise exceptions. */
  573 + /* ??? Should flush denormals to zero. */
  574 + float64 res;
  575 + res = float64_sub(a, b, &env->fp_status);
  576 + if (float64_is_nan(res)) {
  577 + /* +/-inf compares equal against itself, but sub returns nan. */
  578 + if (!float64_is_nan(a)
  579 + && !float64_is_nan(b)) {
  580 + res = float64_zero;
  581 + if (float64_lt_quiet(a, res, &env->fp_status))
  582 + res = float64_chs(res);
  583 + }
  584 + }
  585 + return res;
  586 +}
  587 +
  588 +uint32_t HELPER(compare_f64)(CPUState *env, float64 val)
  589 +{
  590 + return float64_compare_quiet(val, float64_zero, &env->fp_status);
  591 +}
  592 +
  593 +/* MAC unit. */
  594 +/* FIXME: The MAC unit implementation is a bit of a mess. Some helpers
  595 + take values, others take register numbers and manipulate the contents
  596 + in-place. */
  597 +void HELPER(mac_move)(CPUState *env, uint32_t dest, uint32_t src)
  598 +{
  599 + uint32_t mask;
  600 + env->macc[dest] = env->macc[src];
  601 + mask = MACSR_PAV0 << dest;
  602 + if (env->macsr & (MACSR_PAV0 << src))
  603 + env->macsr |= mask;
  604 + else
  605 + env->macsr &= ~mask;
  606 +}
  607 +
  608 +uint64_t HELPER(macmuls)(CPUState *env, uint32_t op1, uint32_t op2)
  609 +{
  610 + int64_t product;
  611 + int64_t res;
  612 +
  613 + product = (uint64_t)op1 * op2;
  614 + res = (product << 24) >> 24;
  615 + if (res != product) {
  616 + env->macsr |= MACSR_V;
  617 + if (env->macsr & MACSR_OMC) {
  618 + /* Make sure the accumulate operation overflows. */
  619 + if (product < 0)
  620 + res = ~(1ll << 50);
  621 + else
  622 + res = 1ll << 50;
  623 + }
  624 + }
  625 + return res;
  626 +}
  627 +
  628 +uint64_t HELPER(macmulu)(CPUState *env, uint32_t op1, uint32_t op2)
  629 +{
  630 + uint64_t product;
  631 +
  632 + product = (uint64_t)op1 * op2;
  633 + if (product & (0xffffffull << 40)) {
  634 + env->macsr |= MACSR_V;
  635 + if (env->macsr & MACSR_OMC) {
  636 + /* Make sure the accumulate operation overflows. */
  637 + product = 1ll << 50;
  638 + } else {
  639 + product &= ((1ull << 40) - 1);
  640 + }
  641 + }
  642 + return product;
  643 +}
  644 +
  645 +uint64_t HELPER(macmulf)(CPUState *env, uint32_t op1, uint32_t op2)
  646 +{
  647 + uint64_t product;
  648 + uint32_t remainder;
  649 +
  650 + product = (uint64_t)op1 * op2;
  651 + if (env->macsr & MACSR_RT) {
  652 + remainder = product & 0xffffff;
  653 + product >>= 24;
  654 + if (remainder > 0x800000)
  655 + product++;
  656 + else if (remainder == 0x800000)
  657 + product += (product & 1);
  658 + } else {
  659 + product >>= 24;
  660 + }
  661 + return product;
  662 +}
  663 +
  664 +void HELPER(macsats)(CPUState *env, uint32_t acc)
  665 +{
  666 + int64_t tmp;
  667 + int64_t result;
  668 + tmp = env->macc[acc];
  669 + result = ((tmp << 16) >> 16);
  670 + if (result != tmp) {
  671 + env->macsr |= MACSR_V;
  672 + }
  673 + if (env->macsr & MACSR_V) {
  674 + env->macsr |= MACSR_PAV0 << acc;
  675 + if (env->macsr & MACSR_OMC) {
  676 + /* The result is saturated to 32 bits, despite overflow occuring
  677 + at 48 bits. Seems weird, but that's what the hardware docs
  678 + say. */
  679 + result = (result >> 63) ^ 0x7fffffff;
  680 + }
  681 + }
  682 + env->macc[acc] = result;
  683 +}
  684 +
  685 +void HELPER(macsatu)(CPUState *env, uint32_t acc)
  686 +{
  687 + uint64_t val;
  688 +
  689 + val = env->macc[acc];
  690 + if (val & (0xffffull << 48)) {
  691 + env->macsr |= MACSR_V;
  692 + }
  693 + if (env->macsr & MACSR_V) {
  694 + env->macsr |= MACSR_PAV0 << acc;
  695 + if (env->macsr & MACSR_OMC) {
  696 + if (val > (1ull << 53))
  697 + val = 0;
  698 + else
  699 + val = (1ull << 48) - 1;
  700 + } else {
  701 + val &= ((1ull << 48) - 1);
  702 + }
  703 + }
  704 + env->macc[acc] = val;
  705 +}
  706 +
  707 +void HELPER(macsatf)(CPUState *env, uint32_t acc)
  708 +{
  709 + int64_t sum;
  710 + int64_t result;
  711 +
  712 + sum = env->macc[acc];
  713 + result = (sum << 16) >> 16;
  714 + if (result != sum) {
  715 + env->macsr |= MACSR_V;
  716 + }
  717 + if (env->macsr & MACSR_V) {
  718 + env->macsr |= MACSR_PAV0 << acc;
  719 + if (env->macsr & MACSR_OMC) {
  720 + result = (result >> 63) ^ 0x7fffffffffffll;
  721 + }
  722 + }
  723 + env->macc[acc] = result;
  724 +}
  725 +
  726 +void HELPER(mac_set_flags)(CPUState *env, uint32_t acc)
  727 +{
  728 + uint64_t val;
  729 + val = env->macc[acc];
  730 + if (val == 0)
  731 + env->macsr |= MACSR_Z;
  732 + else if (val & (1ull << 47));
  733 + env->macsr |= MACSR_N;
  734 + if (env->macsr & (MACSR_PAV0 << acc)) {
  735 + env->macsr |= MACSR_V;
  736 + }
  737 + if (env->macsr & MACSR_FI) {
  738 + val = ((int64_t)val) >> 40;
  739 + if (val != 0 && val != -1)
  740 + env->macsr |= MACSR_EV;
  741 + } else if (env->macsr & MACSR_SU) {
  742 + val = ((int64_t)val) >> 32;
  743 + if (val != 0 && val != -1)
  744 + env->macsr |= MACSR_EV;
  745 + } else {
  746 + if ((val >> 32) != 0)
  747 + env->macsr |= MACSR_EV;
  748 + }
  749 +}
  750 +
  751 +void HELPER(flush_flags)(CPUState *env, uint32_t cc_op)
  752 +{
  753 + cpu_m68k_flush_flags(env, cc_op);
  754 +}
  755 +
  756 +uint32_t HELPER(get_macf)(CPUState *env, uint64_t val)
  757 +{
  758 + int rem;
  759 + uint32_t result;
  760 +
  761 + if (env->macsr & MACSR_SU) {
  762 + /* 16-bit rounding. */
  763 + rem = val & 0xffffff;
  764 + val = (val >> 24) & 0xffffu;
  765 + if (rem > 0x800000)
  766 + val++;
  767 + else if (rem == 0x800000)
  768 + val += (val & 1);
  769 + } else if (env->macsr & MACSR_RT) {
  770 + /* 32-bit rounding. */
  771 + rem = val & 0xff;
  772 + val >>= 8;
  773 + if (rem > 0x80)
  774 + val++;
  775 + else if (rem == 0x80)
  776 + val += (val & 1);
  777 + } else {
  778 + /* No rounding. */
  779 + val >>= 8;
  780 + }
  781 + if (env->macsr & MACSR_OMC) {
  782 + /* Saturate. */
  783 + if (env->macsr & MACSR_SU) {
  784 + if (val != (uint16_t) val) {
  785 + result = ((val >> 63) ^ 0x7fff) & 0xffff;
  786 + } else {
  787 + result = val & 0xffff;
  788 + }
  789 + } else {
  790 + if (val != (uint32_t)val) {
  791 + result = ((uint32_t)(val >> 63) & 0x7fffffff);
  792 + } else {
  793 + result = (uint32_t)val;
  794 + }
  795 + }
  796 + } else {
  797 + /* No saturation. */
  798 + if (env->macsr & MACSR_SU) {
  799 + result = val & 0xffff;
  800 + } else {
  801 + result = (uint32_t)val;
  802 + }
  803 + }
  804 + return result;
  805 +}
  806 +
  807 +uint32_t HELPER(get_macs)(uint64_t val)
  808 +{
  809 + if (val == (int32_t)val) {
  810 + return (int32_t)val;
  811 + } else {
  812 + return (val >> 61) ^ ~SIGNBIT;
  813 + }
  814 +}
  815 +
  816 +uint32_t HELPER(get_macu)(uint64_t val)
  817 +{
  818 + if ((val >> 32) == 0) {
  819 + return (uint32_t)val;
  820 + } else {
  821 + return 0xffffffffu;
  822 + }
  823 +}
  824 +
  825 +uint32_t HELPER(get_mac_extf)(CPUState *env, uint32_t acc)
  826 +{
  827 + uint32_t val;
  828 + val = env->macc[acc] & 0x00ff;
  829 + val = (env->macc[acc] >> 32) & 0xff00;
  830 + val |= (env->macc[acc + 1] << 16) & 0x00ff0000;
  831 + val |= (env->macc[acc + 1] >> 16) & 0xff000000;
  832 + return val;
  833 +}
  834 +
  835 +uint32_t HELPER(get_mac_exti)(CPUState *env, uint32_t acc)
  836 +{
  837 + uint32_t val;
  838 + val = (env->macc[acc] >> 32) & 0xffff;
  839 + val |= (env->macc[acc + 1] >> 16) & 0xffff0000;
  840 + return val;
  841 +}
  842 +
  843 +void HELPER(set_mac_extf)(CPUState *env, uint32_t val, uint32_t acc)
  844 +{
  845 + int64_t res;
  846 + int32_t tmp;
  847 + res = env->macc[acc] & 0xffffffff00ull;
  848 + tmp = (int16_t)(val & 0xff00);
  849 + res |= ((int64_t)tmp) << 32;
  850 + res |= val & 0xff;
  851 + env->macc[acc] = res;
  852 + res = env->macc[acc + 1] & 0xffffffff00ull;
  853 + tmp = (val & 0xff000000);
  854 + res |= ((int64_t)tmp) << 16;
  855 + res |= (val >> 16) & 0xff;
  856 + env->macc[acc + 1] = res;
  857 +}
  858 +
  859 +void HELPER(set_mac_exts)(CPUState *env, uint32_t val, uint32_t acc)
  860 +{
  861 + int64_t res;
  862 + int32_t tmp;
  863 + res = (uint32_t)env->macc[acc];
  864 + tmp = (int16_t)val;
  865 + res |= ((int64_t)tmp) << 32;
  866 + env->macc[acc] = res;
  867 + res = (uint32_t)env->macc[acc + 1];
  868 + tmp = val & 0xffff0000;
  869 + res |= (int64_t)tmp << 16;
  870 + env->macc[acc + 1] = res;
  871 +}
  872 +
  873 +void HELPER(set_mac_extu)(CPUState *env, uint32_t val, uint32_t acc)
  874 +{
  875 + uint64_t res;
  876 + res = (uint32_t)env->macc[acc];
  877 + res |= ((uint64_t)(val & 0xffff)) << 32;
  878 + env->macc[acc] = res;
  879 + res = (uint32_t)env->macc[acc + 1];
  880 + res |= (uint64_t)(val & 0xffff0000) << 16;
  881 + env->macc[acc + 1] = res;
  882 +}
... ...
target-m68k/helpers.h 0 → 100644
  View file @e1f3808
  1 +#ifndef DEF_HELPER
  2 +#define DEF_HELPER(name, ret, args) ret glue(helper_,name) args;
  3 +#endif
  4 +
  5 +#ifdef GEN_HELPER
  6 +#define DEF_HELPER_0_0(name, ret, args) \
  7 +DEF_HELPER(name, ret, args) \
  8 +static inline void gen_helper_##name(void) \
  9 +{ \
  10 + tcg_gen_helper_0_0(helper_##name); \
  11 +}
  12 +#define DEF_HELPER_0_1(name, ret, args) \
  13 +DEF_HELPER(name, ret, args) \
  14 +static inline void gen_helper_##name(TCGv arg1) \
  15 +{ \
  16 + tcg_gen_helper_0_1(helper_##name, arg1); \
  17 +}
  18 +#define DEF_HELPER_0_2(name, ret, args) \
  19 +DEF_HELPER(name, ret, args) \
  20 +static inline void gen_helper_##name(TCGv arg1, TCGv arg2) \
  21 +{ \
  22 + tcg_gen_helper_0_2(helper_##name, arg1, arg2); \
  23 +}
  24 +#define DEF_HELPER_0_3(name, ret, args) \
  25 +DEF_HELPER(name, ret, args) \
  26 +static inline void gen_helper_##name( \
  27 + TCGv arg1, TCGv arg2, TCGv arg3) \
  28 +{ \
  29 + tcg_gen_helper_0_3(helper_##name, arg1, arg2, arg3); \
  30 +}
  31 +#define DEF_HELPER_1_0(name, ret, args) \
  32 +DEF_HELPER(name, ret, args) \
  33 +static inline void gen_helper_##name(TCGv ret) \
  34 +{ \
  35 + tcg_gen_helper_1_0(helper_##name, ret); \
  36 +}
  37 +#define DEF_HELPER_1_1(name, ret, args) \
  38 +DEF_HELPER(name, ret, args) \
  39 +static inline void gen_helper_##name(TCGv ret, TCGv arg1) \
  40 +{ \
  41 + tcg_gen_helper_1_1(helper_##name, ret, arg1); \
  42 +}
  43 +#define DEF_HELPER_1_2(name, ret, args) \
  44 +DEF_HELPER(name, ret, args) \
  45 +static inline void gen_helper_##name(TCGv ret, TCGv arg1, TCGv arg2) \
  46 +{ \
  47 + tcg_gen_helper_1_2(helper_##name, ret, arg1, arg2); \
  48 +}
  49 +#define DEF_HELPER_1_3(name, ret, args) \
  50 +DEF_HELPER(name, ret, args) \
  51 +static inline void gen_helper_##name(TCGv ret, \
  52 + TCGv arg1, TCGv arg2, TCGv arg3) \
  53 +{ \
  54 + tcg_gen_helper_1_3(helper_##name, ret, arg1, arg2, arg3); \
  55 +}
  56 +#define DEF_HELPER_1_4(name, ret, args) \
  57 +DEF_HELPER(name, ret, args) \
  58 +static inline void gen_helper_##name(TCGv ret, \
  59 + TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4) \
  60 +{ \
  61 + tcg_gen_helper_1_4(helper_##name, ret, arg1, arg2, arg3, arg4); \
  62 +}
  63 +#else /* !GEN_HELPER */
  64 +#define DEF_HELPER_0_0 DEF_HELPER
  65 +#define DEF_HELPER_0_1 DEF_HELPER
  66 +#define DEF_HELPER_0_2 DEF_HELPER
  67 +#define DEF_HELPER_0_3 DEF_HELPER
  68 +#define DEF_HELPER_1_0 DEF_HELPER
  69 +#define DEF_HELPER_1_1 DEF_HELPER
  70 +#define DEF_HELPER_1_2 DEF_HELPER
  71 +#define DEF_HELPER_1_3 DEF_HELPER
  72 +#define DEF_HELPER_1_4 DEF_HELPER
  73 +#define HELPER(x) glue(helper_,x)
  74 +#endif
  75 +
  76 +DEF_HELPER_1_1(bitrev, uint32_t, (uint32_t))
  77 +DEF_HELPER_1_1(ff1, uint32_t, (uint32_t))
  78 +DEF_HELPER_1_2(sats, uint32_t, (uint32_t, uint32_t))
  79 +DEF_HELPER_0_2(divu, void, (CPUState *, uint32_t))
  80 +DEF_HELPER_0_2(divs, void, (CPUState *, uint32_t))
  81 +DEF_HELPER_1_3(addx_cc, uint32_t, (CPUState *, uint32_t, uint32_t))
  82 +DEF_HELPER_1_3(subx_cc, uint32_t, (CPUState *, uint32_t, uint32_t))
  83 +DEF_HELPER_1_3(shl_cc, uint32_t, (CPUState *, uint32_t, uint32_t))
  84 +DEF_HELPER_1_3(shr_cc, uint32_t, (CPUState *, uint32_t, uint32_t))
  85 +DEF_HELPER_1_3(sar_cc, uint32_t, (CPUState *, uint32_t, uint32_t))
  86 +DEF_HELPER_1_2(xflag_lt, uint32_t, (uint32_t, uint32_t))
  87 +DEF_HELPER_0_2(set_sr, void, (CPUState *, uint32_t))
  88 +DEF_HELPER_0_3(movec, void, (CPUState *, uint32_t, uint32_t))
  89 +
  90 +DEF_HELPER_1_2(f64_to_i32, float32, (CPUState *, float64))
  91 +DEF_HELPER_1_2(f64_to_f32, float32, (CPUState *, float64))
  92 +DEF_HELPER_1_2(i32_to_f64, float64, (CPUState *, uint32_t))
  93 +DEF_HELPER_1_2(f32_to_f64, float64, (CPUState *, float32))
  94 +DEF_HELPER_1_2(iround_f64, float64, (CPUState *, float64))
  95 +DEF_HELPER_1_2(itrunc_f64, float64, (CPUState *, float64))
  96 +DEF_HELPER_1_2(sqrt_f64, float64, (CPUState *, float64))
  97 +DEF_HELPER_1_1(abs_f64, float64, (float64))
  98 +DEF_HELPER_1_1(chs_f64, float64, (float64))
  99 +DEF_HELPER_1_3(add_f64, float64, (CPUState *, float64, float64))
  100 +DEF_HELPER_1_3(sub_f64, float64, (CPUState *, float64, float64))
  101 +DEF_HELPER_1_3(mul_f64, float64, (CPUState *, float64, float64))
  102 +DEF_HELPER_1_3(div_f64, float64, (CPUState *, float64, float64))
  103 +DEF_HELPER_1_3(sub_cmp_f64, float64, (CPUState *, float64, float64))
  104 +DEF_HELPER_1_2(compare_f64, uint32_t, (CPUState *, float64))
  105 +
  106 +DEF_HELPER_0_3(mac_move, void, (CPUState *, uint32_t, uint32_t))
  107 +DEF_HELPER_1_3(macmulf, uint64_t, (CPUState *, uint32_t, uint32_t))
  108 +DEF_HELPER_1_3(macmuls, uint64_t, (CPUState *, uint32_t, uint32_t))
  109 +DEF_HELPER_1_3(macmulu, uint64_t, (CPUState *, uint32_t, uint32_t))
  110 +DEF_HELPER_0_2(macsats, void, (CPUState *, uint32_t))
  111 +DEF_HELPER_0_2(macsatu, void, (CPUState *, uint32_t))
  112 +DEF_HELPER_0_2(macsatf, void, (CPUState *, uint32_t))
  113 +DEF_HELPER_0_2(mac_set_flags, void, (CPUState *, uint32_t))
  114 +DEF_HELPER_0_2(set_macsr, void, (CPUState *, uint32_t))
  115 +DEF_HELPER_1_2(get_macf, uint32_t, (CPUState *, uint64_t))
  116 +DEF_HELPER_1_1(get_macs, uint32_t, (uint64_t))
  117 +DEF_HELPER_1_1(get_macu, uint32_t, (uint64_t))
  118 +DEF_HELPER_1_2(get_mac_extf, uint32_t, (CPUState *, uint32_t))
  119 +DEF_HELPER_1_2(get_mac_exti, uint32_t, (CPUState *, uint32_t))
  120 +DEF_HELPER_0_3(set_mac_extf, void, (CPUState *, uint32_t, uint32_t))
  121 +DEF_HELPER_0_3(set_mac_exts, void, (CPUState *, uint32_t, uint32_t))
  122 +DEF_HELPER_0_3(set_mac_extu, void, (CPUState *, uint32_t, uint32_t))
  123 +
  124 +DEF_HELPER_0_2(flush_flags, void, (CPUState *, uint32_t))
  125 +DEF_HELPER_0_1(raise_exception, void, (uint32_t))
  126 +
  127 +#undef DEF_HELPER
  128 +#undef DEF_HELPER_0_0
  129 +#undef DEF_HELPER_0_1
  130 +#undef DEF_HELPER_0_2
  131 +#undef DEF_HELPER_0_3
  132 +#undef DEF_HELPER_1_0
  133 +#undef DEF_HELPER_1_1
  134 +#undef DEF_HELPER_1_2
  135 +#undef DEF_HELPER_1_3
  136 +#undef DEF_HELPER_1_4
  137 +#undef GEN_HELPER
  138 +#undef DEF_HELPER
... ...
target-m68k/op-hacks.h deleted 100644 → 0
  View file @3979144
1   -/* Various hacks to make code written for a dynamic code generator work
2   - with regular QEMU. */
3   -
4   -static int free_qreg;
5   -
6   -#define QMODE_I32 1
7   -#define QMODE_F32 1
8   -#define QMODE_F64 2
9   -
10   -static inline int gen_new_qreg(int mode)
11   -{
12   - int qreg;
13   -
14   - qreg = free_qreg;
15   - free_qreg += mode;
16   - if (free_qreg > MAX_QREGS) {
17   - fprintf(stderr, "qreg overflow\n");
18   - abort();
19   - }
20   - return qreg + TARGET_NUM_QREGS;
21   -}
22   -
23   -static inline int gen_im32(uint32_t i)
24   -{
25   - int qreg = gen_new_qreg(QMODE_I32);
26   - gen_op_mov32_im(qreg, i);
27   - return qreg;
28   -}
29   -
30   -static inline void gen_op_ldf32_raw(int dest, int addr)
31   -{
32   - gen_op_ld32_raw(dest, addr);
33   -}
34   -
35   -static inline void gen_op_stf32_raw(int addr, int dest)
36   -{
37   - gen_op_st32_raw(addr, dest);
38   -}
39   -
40   -#if !defined(CONFIG_USER_ONLY)
41   -static inline void gen_op_ldf32_user(int dest, int addr)
42   -{
43   - gen_op_ld32_user(dest, addr);
44   -}
45   -
46   -static inline void gen_op_stf32_user(int addr, int dest)
47   -{
48   - gen_op_st32_user(addr, dest);
49   -}
50   -
51   -static inline void gen_op_ldf32_kernel(int dest, int addr)
52   -{
53   - gen_op_ld32_kernel(dest, addr);
54   -}
55   -
56   -static inline void gen_op_stf32_kernel(int addr, int dest)
57   -{
58   - gen_op_st32_kernel(addr, dest);
59   -}
60   -#endif
61   -
62   -static inline void gen_op_pack_32_f32(int dest, int src)
63   -{
64   - gen_op_mov32(dest, src);
65   -}
66   -
67   -static inline void gen_op_pack_f32_32(int dest, int src)
68   -{
69   - gen_op_mov32(dest, src);
70   -}
71   -
72   -static inline void gen_op_flags_set(void)
73   -{
74   - /* Dummy op. */
75   -}
76   -
77   -static inline void gen_op_shl_im_cc(int val, int shift)
78   -{
79   - gen_op_shl_cc(val, gen_im32(shift));
80   -}
81   -
82   -static inline void gen_op_shr_im_cc(int val, int shift)
83   -{
84   - gen_op_shr_cc(val, gen_im32(shift));
85   -}
86   -
87   -static inline void gen_op_sar_im_cc(int val, int shift)
88   -{
89   - gen_op_sar_cc(val, gen_im32(shift));
90   -}
91   -
92   -#ifdef USE_DIRECT_JUMP
93   -#define TBPARAM(x)
94   -#else
95   -#define TBPARAM(x) (long)(x)
96   -#endif
97   -
98   -static inline void gen_op_goto_tb(int dummy, int n, long tb)
99   -{
100   - if (n == 0) {
101   - gen_op_goto_tb0(TBPARAM(tb));
102   - } else {
103   - gen_op_goto_tb1(TBPARAM(tb));
104   - }
105   -}
106   -
107   -static inline void gen_op_jmp_z32(int val, int label)
108   -{
109   - gen_op_set_T0_z32(val);
110   - gen_op_jmp_T0(label);
111   -}
112   -
113   -static inline void gen_op_jmp_nz32(int val, int label)
114   -{
115   - gen_op_set_T0_nz32(val);
116   - gen_op_jmp_T0(label);
117   -}
118   -
119   -static inline void gen_op_jmp_s32(int val, int label)
120   -{
121   - gen_op_set_T0_s32(val);
122   - gen_op_jmp_T0(label);
123   -}
124   -
125   -static inline void gen_op_jmp_ns32(int val, int label)
126   -{
127   - gen_op_set_T0_ns32(val);
128   - gen_op_jmp_T0(label);
129   -}
130   -
target-m68k/op.c deleted 100644 → 0
  View file @3979144
1   -/*
2   - * m68k micro operations
3   - *
4   - * Copyright (c) 2006-2007 CodeSourcery
5   - * Written by Paul Brook
6   - *
7   - * This library is free software; you can redistribute it and/or
8   - * modify it under the terms of the GNU Lesser General Public
9   - * License as published by the Free Software Foundation; either
10   - * version 2 of the License, or (at your option) any later version.
11   - *
12   - * This library is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15   - * General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU Lesser General Public
18   - * License along with this library; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20   - */
21   -
22   -#include "exec.h"
23   -#include "m68k-qreg.h"
24   -
25   -#ifndef offsetof
26   -#define offsetof(type, field) ((size_t) &((type *)0)->field)
27   -#endif
28   -
29   -static long qreg_offsets[] = {
30   -#define DEFO32(name, offset) offsetof(CPUState, offset),
31   -#define DEFR(name, reg, mode) -1,
32   -#define DEFF64(name, offset) offsetof(CPUState, offset),
33   - 0,
34   -#include "qregs.def"
35   -};
36   -
37   -#define CPU_FP_STATUS env->fp_status
38   -
39   -#define RAISE_EXCEPTION(n) do { \
40   - env->exception_index = n; \
41   - cpu_loop_exit(); \
42   - } while(0)
43   -
44   -#define get_op helper_get_op
45   -#define set_op helper_set_op
46   -#define get_opf64 helper_get_opf64
47   -#define set_opf64 helper_set_opf64
48   -uint32_t
49   -get_op(int qreg)
50   -{
51   - if (qreg >= TARGET_NUM_QREGS) {
52   - return env->qregs[qreg - TARGET_NUM_QREGS];
53   - } else if (qreg == QREG_T0) {
54   - return T0;
55   - } else {
56   - return *(uint32_t *)(((long)env) + qreg_offsets[qreg]);
57   - }
58   -}
59   -
60   -void set_op(int qreg, uint32_t val)
61   -{
62   - if (qreg >= TARGET_NUM_QREGS) {
63   - env->qregs[qreg - TARGET_NUM_QREGS] = val;
64   - } else if (qreg == QREG_T0) {
65   - T0 = val;
66   - } else {
67   - *(uint32_t *)(((long)env) + qreg_offsets[qreg]) = val;
68   - }
69   -}
70   -
71   -float64 get_opf64(int qreg)
72   -{
73   - if (qreg < TARGET_NUM_QREGS) {
74   - return *(float64 *)(((long)env) + qreg_offsets[qreg]);
75   - } else {
76   - return *(float64 *)&env->qregs[qreg - TARGET_NUM_QREGS];
77   - }
78   -}
79   -
80   -void set_opf64(int qreg, float64 val)
81   -{
82   - if (qreg < TARGET_NUM_QREGS) {
83   - *(float64 *)(((long)env) + qreg_offsets[qreg]) = val;
84   - } else {
85   - *(float64 *)&env->qregs[qreg - TARGET_NUM_QREGS] = val;
86   - }
87   -}
88   -
89   -#define OP(name) void OPPROTO glue(op_,name) (void)
90   -
91   -OP(mov32)
92   -{
93   - set_op(PARAM1, get_op(PARAM2));
94   - FORCE_RET();
95   -}
96   -
97   -OP(mov32_im)
98   -{
99   - set_op(PARAM1, PARAM2);
100   - FORCE_RET();
101   -}
102   -
103   -OP(movf64)
104   -{
105   - set_opf64(PARAM1, get_opf64(PARAM2));
106   - FORCE_RET();
107   -}
108   -
109   -OP(zerof64)
110   -{
111   - set_opf64(PARAM1, float64_zero);
112   - FORCE_RET();
113   -}
114   -
115   -OP(add32)
116   -{
117   - uint32_t op2 = get_op(PARAM2);
118   - uint32_t op3 = get_op(PARAM3);
119   - set_op(PARAM1, op2 + op3);
120   - FORCE_RET();
121   -}
122   -
123   -OP(sub32)
124   -{
125   - uint32_t op2 = get_op(PARAM2);
126   - uint32_t op3 = get_op(PARAM3);
127   - set_op(PARAM1, op2 - op3);
128   - FORCE_RET();
129   -}
130   -
131   -OP(mul32)
132   -{
133   - uint32_t op2 = get_op(PARAM2);
134   - uint32_t op3 = get_op(PARAM3);
135   - set_op(PARAM1, op2 * op3);
136   - FORCE_RET();
137   -}
138   -
139   -OP(not32)
140   -{
141   - uint32_t arg = get_op(PARAM2);
142   - set_op(PARAM1, ~arg);
143   - FORCE_RET();
144   -}
145   -
146   -OP(neg32)
147   -{
148   - uint32_t arg = get_op(PARAM2);
149   - set_op(PARAM1, -arg);
150   - FORCE_RET();
151   -}
152   -
153   -OP(bswap32)
154   -{
155   - uint32_t arg = get_op(PARAM2);
156   - arg = (arg >> 24) | (arg << 24)
157   - | ((arg >> 16) & 0xff00) | ((arg << 16) & 0xff0000);
158   - set_op(PARAM1, arg);
159   - FORCE_RET();
160   -}
161   -
162   -OP(btest)
163   -{
164   - uint32_t op1 = get_op(PARAM1);
165   - uint32_t op2 = get_op(PARAM2);
166   - if (op1 & op2)
167   - env->cc_dest &= ~CCF_Z;
168   - else
169   - env->cc_dest |= CCF_Z;
170   - FORCE_RET();
171   -}
172   -
173   -OP(ff1)
174   -{
175   - uint32_t arg = get_op(PARAM2);
176   - int n;
177   - for (n = 32; arg; n--)
178   - arg >>= 1;
179   - set_op(PARAM1, n);
180   - FORCE_RET();
181   -}
182   -
183   -OP(subx_cc)
184   -{
185   - uint32_t op1 = get_op(PARAM1);
186   - uint32_t op2 = get_op(PARAM2);
187   - uint32_t res;
188   - if (env->cc_x) {
189   - env->cc_x = (op1 <= op2);
190   - env->cc_op = CC_OP_SUBX;
191   - res = op1 - (op2 + 1);
192   - } else {
193   - env->cc_x = (op1 < op2);
194   - env->cc_op = CC_OP_SUB;
195   - res = op1 - op2;
196   - }
197   - set_op(PARAM1, res);
198   - FORCE_RET();
199   -}
200   -
201   -OP(addx_cc)
202   -{
203   - uint32_t op1 = get_op(PARAM1);
204   - uint32_t op2 = get_op(PARAM2);
205   - uint32_t res;
206   - if (env->cc_x) {
207   - res = op1 + op2 + 1;
208   - env->cc_x = (res <= op2);
209   - env->cc_op = CC_OP_ADDX;
210   - } else {
211   - res = op1 + op2;
212   - env->cc_x = (res < op2);
213   - env->cc_op = CC_OP_ADD;
214   - }
215   - set_op(PARAM1, res);
216   - FORCE_RET();
217   -}
218   -
219   -/* Logic ops. */
220   -
221   -OP(and32)
222   -{
223   - uint32_t op2 = get_op(PARAM2);
224   - uint32_t op3 = get_op(PARAM3);
225   - set_op(PARAM1, op2 & op3);
226   - FORCE_RET();
227   -}
228   -
229   -OP(or32)
230   -{
231   - uint32_t op2 = get_op(PARAM2);
232   - uint32_t op3 = get_op(PARAM3);
233   - set_op(PARAM1, op2 | op3);
234   - FORCE_RET();
235   -}
236   -
237   -OP(xor32)
238   -{
239   - uint32_t op2 = get_op(PARAM2);
240   - uint32_t op3 = get_op(PARAM3);
241   - set_op(PARAM1, op2 ^ op3);
242   - FORCE_RET();
243   -}
244   -
245   -/* Shifts. */
246   -OP(shl32)
247   -{
248   - uint32_t op2 = get_op(PARAM2);
249   - uint32_t op3 = get_op(PARAM3);
250   - uint32_t result;
251   - result = op2 << op3;
252   - set_op(PARAM1, result);
253   - FORCE_RET();
254   -}
255   -
256   -OP(shl_cc)
257   -{
258   - uint32_t op1 = get_op(PARAM1);
259   - uint32_t op2 = get_op(PARAM2);
260   - uint32_t result;
261   - result = op1 << op2;
262   - set_op(PARAM1, result);
263   - env->cc_x = (op1 << (op2 - 1)) & 1;
264   - FORCE_RET();
265   -}
266   -
267   -OP(shr32)
268   -{
269   - uint32_t op2 = get_op(PARAM2);
270   - uint32_t op3 = get_op(PARAM3);
271   - uint32_t result;
272   - result = op2 >> op3;
273   - set_op(PARAM1, result);
274   - FORCE_RET();
275   -}
276   -
277   -OP(shr_cc)
278   -{
279   - uint32_t op1 = get_op(PARAM1);
280   - uint32_t op2 = get_op(PARAM2);
281   - uint32_t result;
282   - result = op1 >> op2;
283   - set_op(PARAM1, result);
284   - env->cc_x = (op1 >> (op2 - 1)) & 1;
285   - FORCE_RET();
286   -}
287   -
288   -OP(sar32)
289   -{
290   - int32_t op2 = get_op(PARAM2);
291   - uint32_t op3 = get_op(PARAM3);
292   - uint32_t result;
293   - result = op2 >> op3;
294   - set_op(PARAM1, result);
295   - FORCE_RET();
296   -}
297   -
298   -OP(sar_cc)
299   -{
300   - int32_t op1 = get_op(PARAM1);
301   - uint32_t op2 = get_op(PARAM2);
302   - uint32_t result;
303   - result = op1 >> op2;
304   - set_op(PARAM1, result);
305   - env->cc_x = (op1 >> (op2 - 1)) & 1;
306   - FORCE_RET();
307   -}
308   -
309   -/* Value extend. */
310   -
311   -OP(ext8u32)
312   -{
313   - uint32_t op2 = get_op(PARAM2);
314   - set_op(PARAM1, (uint8_t)op2);
315   - FORCE_RET();
316   -}
317   -
318   -OP(ext8s32)
319   -{
320   - uint32_t op2 = get_op(PARAM2);
321   - set_op(PARAM1, (int8_t)op2);
322   - FORCE_RET();
323   -}
324   -
325   -OP(ext16u32)
326   -{
327   - uint32_t op2 = get_op(PARAM2);
328   - set_op(PARAM1, (uint16_t)op2);
329   - FORCE_RET();
330   -}
331   -
332   -OP(ext16s32)
333   -{
334   - uint32_t op2 = get_op(PARAM2);
335   - set_op(PARAM1, (int16_t)op2);
336   - FORCE_RET();
337   -}
338   -
339   -OP(flush_flags)
340   -{
341   - cpu_m68k_flush_flags(env, env->cc_op);
342   - FORCE_RET();
343   -}
344   -
345   -OP(divu)
346   -{
347   - uint32_t num;
348   - uint32_t den;
349   - uint32_t quot;
350   - uint32_t rem;
351   - uint32_t flags;
352   -
353   - num = env->div1;
354   - den = env->div2;
355   - /* ??? This needs to make sure the throwing location is accurate. */
356   - if (den == 0)
357   - RAISE_EXCEPTION(EXCP_DIV0);
358   - quot = num / den;
359   - rem = num % den;
360   - flags = 0;
361   - /* Avoid using a PARAM1 of zero. This breaks dyngen because it uses
362   - the address of a symbol, and gcc knows symbols can't have address
363   - zero. */
364   - if (PARAM1 == 2 && quot > 0xffff)
365   - flags |= CCF_V;
366   - if (quot == 0)
367   - flags |= CCF_Z;
368   - else if ((int32_t)quot < 0)
369   - flags |= CCF_N;
370   - env->div1 = quot;
371   - env->div2 = rem;
372   - env->cc_dest = flags;
373   - FORCE_RET();
374   -}
375   -
376   -OP(divs)
377   -{
378   - int32_t num;
379   - int32_t den;
380   - int32_t quot;
381   - int32_t rem;
382   - int32_t flags;
383   -
384   - num = env->div1;
385   - den = env->div2;
386   - if (den == 0)
387   - RAISE_EXCEPTION(EXCP_DIV0);
388   - quot = num / den;
389   - rem = num % den;
390   - flags = 0;
391   - if (PARAM1 == 2 && quot != (int16_t)quot)
392   - flags |= CCF_V;
393   - if (quot == 0)
394   - flags |= CCF_Z;
395   - else if (quot < 0)
396   - flags |= CCF_N;
397   - env->div1 = quot;
398   - env->div2 = rem;
399   - env->cc_dest = flags;
400   - FORCE_RET();
401   -}
402   -
403   -/* Halt is special because it may be a semihosting call. */
404   -OP(halt)
405   -{
406   - RAISE_EXCEPTION(EXCP_HALT_INSN);
407   - FORCE_RET();
408   -}
409   -
410   -OP(stop)
411   -{
412   - env->halted = 1;
413   - RAISE_EXCEPTION(EXCP_HLT);
414   - FORCE_RET();
415   -}
416   -
417   -OP(raise_exception)
418   -{
419   - RAISE_EXCEPTION(PARAM1);
420   - FORCE_RET();
421   -}
422   -
423   -/* Floating point comparison sets flags differently to other instructions. */
424   -
425   -OP(sub_cmpf64)
426   -{
427   - float64 src0;
428   - float64 src1;
429   - src0 = get_opf64(PARAM2);
430   - src1 = get_opf64(PARAM3);
431   - set_opf64(PARAM1, helper_sub_cmpf64(env, src0, src1));
432   - FORCE_RET();
433   -}
434   -
435   -OP(update_xflag_tst)
436   -{
437   - uint32_t op1 = get_op(PARAM1);
438   - env->cc_x = op1;
439   - FORCE_RET();
440   -}
441   -
442   -OP(update_xflag_lt)
443   -{
444   - uint32_t op1 = get_op(PARAM1);
445   - uint32_t op2 = get_op(PARAM2);
446   - env->cc_x = (op1 < op2);
447   - FORCE_RET();
448   -}
449   -
450   -OP(get_xflag)
451   -{
452   - set_op(PARAM1, env->cc_x);
453   - FORCE_RET();
454   -}
455   -
456   -OP(logic_cc)
457   -{
458   - uint32_t op1 = get_op(PARAM1);
459   - env->cc_dest = op1;
460   - FORCE_RET();
461   -}
462   -
463   -OP(update_cc_add)
464   -{
465   - uint32_t op1 = get_op(PARAM1);
466   - uint32_t op2 = get_op(PARAM2);
467   - env->cc_dest = op1;
468   - env->cc_src = op2;
469   - FORCE_RET();
470   -}
471   -
472   -OP(fp_result)
473   -{
474   - env->fp_result = get_opf64(PARAM1);
475   - FORCE_RET();
476   -}
477   -
478   -OP(set_sr)
479   -{
480   - env->sr = get_op(PARAM1) & 0xffff;
481   - m68k_switch_sp(env);
482   - FORCE_RET();
483   -}
484   -
485   -OP(jmp_im)
486   -{
487   - GOTO_LABEL_PARAM(1);
488   -}
489   -
490   -OP(set_T0_z32)
491   -{
492   - uint32_t arg = get_op(PARAM1);
493   - T0 = (arg == 0);
494   - FORCE_RET();
495   -}
496   -
497   -OP(set_T0_nz32)
498   -{
499   - uint32_t arg = get_op(PARAM1);
500   - T0 = (arg != 0);
501   - FORCE_RET();
502   -}
503   -
504   -OP(set_T0_s32)
505   -{
506   - int32_t arg = get_op(PARAM1);
507   - T0 = (arg < 0);
508   - FORCE_RET();
509   -}
510   -
511   -OP(set_T0_ns32)
512   -{
513   - int32_t arg = get_op(PARAM1);
514   - T0 = (arg >= 0);
515   - FORCE_RET();
516   -}
517   -
518   -OP(jmp_T0)
519   -{
520   - if (T0)
521   - GOTO_LABEL_PARAM(1);
522   - FORCE_RET();
523   -}
524   -
525   -/* Floating point. */
526   -OP(f64_to_i32)
527   -{
528   - set_op(PARAM1, float64_to_int32(get_opf64(PARAM2), &CPU_FP_STATUS));
529   - FORCE_RET();
530   -}
531   -
532   -OP(f64_to_f32)
533   -{
534   - union {
535   - float32 f;
536   - uint32_t i;
537   - } u;
538   - u.f = float64_to_float32(get_opf64(PARAM2), &CPU_FP_STATUS);
539   - set_op(PARAM1, u.i);
540   - FORCE_RET();
541   -}
542   -
543   -OP(i32_to_f64)
544   -{
545   - set_opf64(PARAM1, int32_to_float64(get_op(PARAM2), &CPU_FP_STATUS));
546   - FORCE_RET();
547   -}
548   -
549   -OP(f32_to_f64)
550   -{
551   - union {
552   - float32 f;
553   - uint32_t i;
554   - } u;
555   - u.i = get_op(PARAM2);
556   - set_opf64(PARAM1, float32_to_float64(u.f, &CPU_FP_STATUS));
557   - FORCE_RET();
558   -}
559   -
560   -OP(absf64)
561   -{
562   - float64 op0 = get_opf64(PARAM2);
563   - set_opf64(PARAM1, float64_abs(op0));
564   - FORCE_RET();
565   -}
566   -
567   -OP(chsf64)
568   -{
569   - float64 op0 = get_opf64(PARAM2);
570   - set_opf64(PARAM1, float64_chs(op0));
571   - FORCE_RET();
572   -}
573   -
574   -OP(sqrtf64)
575   -{
576   - float64 op0 = get_opf64(PARAM2);
577   - set_opf64(PARAM1, float64_sqrt(op0, &CPU_FP_STATUS));
578   - FORCE_RET();
579   -}
580   -
581   -OP(addf64)
582   -{
583   - float64 op0 = get_opf64(PARAM2);
584   - float64 op1 = get_opf64(PARAM3);
585   - set_opf64(PARAM1, float64_add(op0, op1, &CPU_FP_STATUS));
586   - FORCE_RET();
587   -}
588   -
589   -OP(subf64)
590   -{
591   - float64 op0 = get_opf64(PARAM2);
592   - float64 op1 = get_opf64(PARAM3);
593   - set_opf64(PARAM1, float64_sub(op0, op1, &CPU_FP_STATUS));
594   - FORCE_RET();
595   -}
596   -
597   -OP(mulf64)
598   -{
599   - float64 op0 = get_opf64(PARAM2);
600   - float64 op1 = get_opf64(PARAM3);
601   - set_opf64(PARAM1, float64_mul(op0, op1, &CPU_FP_STATUS));
602   - FORCE_RET();
603   -}
604   -
605   -OP(divf64)
606   -{
607   - float64 op0 = get_opf64(PARAM2);
608   - float64 op1 = get_opf64(PARAM3);
609   - set_opf64(PARAM1, float64_div(op0, op1, &CPU_FP_STATUS));
610   - FORCE_RET();
611   -}
612   -
613   -OP(iround_f64)
614   -{
615   - float64 op0 = get_opf64(PARAM2);
616   - set_opf64(PARAM1, float64_round_to_int(op0, &CPU_FP_STATUS));
617   - FORCE_RET();
618   -}
619   -
620   -OP(itrunc_f64)
621   -{
622   - float64 op0 = get_opf64(PARAM2);
623   - set_opf64(PARAM1, float64_trunc_to_int(op0, &CPU_FP_STATUS));
624   - FORCE_RET();
625   -}
626   -
627   -OP(compare_quietf64)
628   -{
629   - float64 op0 = get_opf64(PARAM2);
630   - float64 op1 = get_opf64(PARAM3);
631   - set_op(PARAM1, float64_compare_quiet(op0, op1, &CPU_FP_STATUS));
632   - FORCE_RET();
633   -}
634   -
635   -OP(movec)
636   -{
637   - int op1 = get_op(PARAM1);
638   - uint32_t op2 = get_op(PARAM2);
639   - helper_movec(env, op1, op2);
640   -}
641   -
642   -/* Memory access. */
643   -
644   -#define MEMSUFFIX _raw
645   -#include "op_mem.h"
646   -
647   -#if !defined(CONFIG_USER_ONLY)
648   -#define MEMSUFFIX _user
649   -#include "op_mem.h"
650   -#define MEMSUFFIX _kernel
651   -#include "op_mem.h"
652   -#endif
653   -
654   -/* MAC unit. */
655   -/* TODO: The MAC instructions use 64-bit arithmetic fairly extensively.
656   - This results in fairly large ops (and sometimes other issues) on 32-bit
657   - hosts. Maybe move most of them into helpers. */
658   -OP(macmuls)
659   -{
660   - uint32_t op1 = get_op(PARAM1);
661   - uint32_t op2 = get_op(PARAM2);
662   - int64_t product;
663   - int64_t res;
664   -
665   - product = (uint64_t)op1 * op2;
666   - res = (product << 24) >> 24;
667   - if (res != product) {
668   - env->macsr |= MACSR_V;
669   - if (env->macsr & MACSR_OMC) {
670   - /* Make sure the accumulate operation overflows. */
671   - if (product < 0)
672   - res = ~(1ll << 50);
673   - else
674   - res = 1ll << 50;
675   - }
676   - }
677   - env->mactmp = res;
678   - FORCE_RET();
679   -}
680   -
681   -OP(macmulu)
682   -{
683   - uint32_t op1 = get_op(PARAM1);
684   - uint32_t op2 = get_op(PARAM2);
685   - uint64_t product;
686   -
687   - product = (uint64_t)op1 * op2;
688   - if (product & (0xffffffull << 40)) {
689   - env->macsr |= MACSR_V;
690   - if (env->macsr & MACSR_OMC) {
691   - /* Make sure the accumulate operation overflows. */
692   - product = 1ll << 50;
693   - } else {
694   - product &= ((1ull << 40) - 1);
695   - }
696   - }
697   - env->mactmp = product;
698   - FORCE_RET();
699   -}
700   -
701   -OP(macmulf)
702   -{
703   - int32_t op1 = get_op(PARAM1);
704   - int32_t op2 = get_op(PARAM2);
705   - uint64_t product;
706   - uint32_t remainder;
707   -
708   - product = (uint64_t)op1 * op2;
709   - if (env->macsr & MACSR_RT) {
710   - remainder = product & 0xffffff;
711   - product >>= 24;
712   - if (remainder > 0x800000)
713   - product++;
714   - else if (remainder == 0x800000)
715   - product += (product & 1);
716   - } else {
717   - product >>= 24;
718   - }
719   - env->mactmp = product;
720   - FORCE_RET();
721   -}
722   -
723   -OP(macshl)
724   -{
725   - env->mactmp <<= 1;
726   -}
727   -
728   -OP(macshr)
729   -{
730   - env->mactmp >>= 1;
731   -}
732   -
733   -OP(macadd)
734   -{
735   - int acc = PARAM1;
736   - env->macc[acc] += env->mactmp;
737   - FORCE_RET();
738   -}
739   -
740   -OP(macsub)
741   -{
742   - int acc = PARAM1;
743   - env->macc[acc] -= env->mactmp;
744   - FORCE_RET();
745   -}
746   -
747   -OP(macsats)
748   -{
749   - int acc = PARAM1;
750   - int64_t sum;
751   - int64_t result;
752   -
753   - sum = env->macc[acc];
754   - result = (sum << 16) >> 16;
755   - if (result != sum) {
756   - env->macsr |= MACSR_V;
757   - }
758   - if (env->macsr & MACSR_V) {
759   - env->macsr |= MACSR_PAV0 << acc;
760   - if (env->macsr & MACSR_OMC) {
761   - /* The result is saturated to 32 bits, despite overflow occuring
762   - at 48 bits. Seems weird, but that's what the hardware docs
763   - say. */
764   - result = (result >> 63) ^ 0x7fffffff;
765   - }
766   - }
767   - env->macc[acc] = result;
768   - FORCE_RET();
769   -}
770   -
771   -OP(macsatu)
772   -{
773   - int acc = PARAM1;
774   - uint64_t sum;
775   -
776   - sum = env->macc[acc];
777   - if (sum & (0xffffull << 48)) {
778   - env->macsr |= MACSR_V;
779   - }
780   - if (env->macsr & MACSR_V) {
781   - env->macsr |= MACSR_PAV0 << acc;
782   - if (env->macsr & MACSR_OMC) {
783   - if (sum > (1ull << 53))
784   - sum = 0;
785   - else
786   - sum = (1ull << 48) - 1;
787   - } else {
788   - sum &= ((1ull << 48) - 1);
789   - }
790   - }
791   - FORCE_RET();
792   -}
793   -
794   -OP(macsatf)
795   -{
796   - int acc = PARAM1;
797   - int64_t sum;
798   - int64_t result;
799   -
800   - sum = env->macc[acc];
801   - result = (sum << 16) >> 16;
802   - if (result != sum) {
803   - env->macsr |= MACSR_V;
804   - }
805   - if (env->macsr & MACSR_V) {
806   - env->macsr |= MACSR_PAV0 << acc;
807   - if (env->macsr & MACSR_OMC) {
808   - result = (result >> 63) ^ 0x7fffffffffffll;
809   - }
810   - }
811   - env->macc[acc] = result;
812   - FORCE_RET();
813   -}
814   -
815   -OP(mac_clear_flags)
816   -{
817   - env->macsr &= ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV);
818   -}
819   -
820   -OP(mac_set_flags)
821   -{
822   - int acc = PARAM1;
823   - uint64_t val;
824   - val = env->macc[acc];
825   - if (val == 0)
826   - env->macsr |= MACSR_Z;
827   - else if (val & (1ull << 47));
828   - env->macsr |= MACSR_N;
829   - if (env->macsr & (MACSR_PAV0 << acc)) {
830   - env->macsr |= MACSR_V;
831   - }
832   - if (env->macsr & MACSR_FI) {
833   - val = ((int64_t)val) >> 40;
834   - if (val != 0 && val != -1)
835   - env->macsr |= MACSR_EV;
836   - } else if (env->macsr & MACSR_SU) {
837   - val = ((int64_t)val) >> 32;
838   - if (val != 0 && val != -1)
839   - env->macsr |= MACSR_EV;
840   - } else {
841   - if ((val >> 32) != 0)
842   - env->macsr |= MACSR_EV;
843   - }
844   - FORCE_RET();
845   -}
846   -
847   -OP(get_macf)
848   -{
849   - int acc = PARAM2;
850   - int64_t val;
851   - int rem;
852   - uint32_t result;
853   -
854   - val = env->macc[acc];
855   - if (env->macsr & MACSR_SU) {
856   - /* 16-bit rounding. */
857   - rem = val & 0xffffff;
858   - val = (val >> 24) & 0xffffu;
859   - if (rem > 0x800000)
860   - val++;
861   - else if (rem == 0x800000)
862   - val += (val & 1);
863   - } else if (env->macsr & MACSR_RT) {
864   - /* 32-bit rounding. */
865   - rem = val & 0xff;
866   - val >>= 8;
867   - if (rem > 0x80)
868   - val++;
869   - else if (rem == 0x80)
870   - val += (val & 1);
871   - } else {
872   - /* No rounding. */
873   - val >>= 8;
874   - }
875   - if (env->macsr & MACSR_OMC) {
876   - /* Saturate. */
877   - if (env->macsr & MACSR_SU) {
878   - if (val != (uint16_t) val) {
879   - result = ((val >> 63) ^ 0x7fff) & 0xffff;
880   - } else {
881   - result = val & 0xffff;
882   - }
883   - } else {
884   - if (val != (uint32_t)val) {
885   - result = ((uint32_t)(val >> 63) & 0x7fffffff);
886   - } else {
887   - result = (uint32_t)val;
888   - }
889   - }
890   - } else {
891   - /* No saturation. */
892   - if (env->macsr & MACSR_SU) {
893   - result = val & 0xffff;
894   - } else {
895   - result = (uint32_t)val;
896   - }
897   - }
898   - set_op(PARAM1, result);
899   - FORCE_RET();
900   -}
901   -
902   -OP(get_maci)
903   -{
904   - int acc = PARAM2;
905   - set_op(PARAM1, (uint32_t)env->macc[acc]);
906   - FORCE_RET();
907   -}
908   -
909   -OP(get_macs)
910   -{
911   - int acc = PARAM2;
912   - int64_t val = env->macc[acc];
913   - uint32_t result;
914   - if (val == (int32_t)val) {
915   - result = (int32_t)val;
916   - } else {
917   - result = (val >> 61) ^ 0x7fffffff;
918   - }
919   - set_op(PARAM1, result);
920   - FORCE_RET();
921   -}
922   -
923   -OP(get_macu)
924   -{
925   - int acc = PARAM2;
926   - uint64_t val = env->macc[acc];
927   - uint32_t result;
928   - if ((val >> 32) == 0) {
929   - result = (uint32_t)val;
930   - } else {
931   - result = 0xffffffffu;
932   - }
933   - set_op(PARAM1, result);
934   - FORCE_RET();
935   -}
936   -
937   -OP(clear_mac)
938   -{
939   - int acc = PARAM1;
940   -
941   - env->macc[acc] = 0;
942   - env->macsr &= ~(MACSR_PAV0 << acc);
943   - FORCE_RET();
944   -}
945   -
946   -OP(move_mac)
947   -{
948   - int dest = PARAM1;
949   - int src = PARAM2;
950   - uint32_t mask;
951   - env->macc[dest] = env->macc[src];
952   - mask = MACSR_PAV0 << dest;
953   - if (env->macsr & (MACSR_PAV0 << src))
954   - env->macsr |= mask;
955   - else
956   - env->macsr &= ~mask;
957   - FORCE_RET();
958   -}
959   -
960   -OP(get_mac_extf)
961   -{
962   - uint32_t val;
963   - int acc = PARAM2;
964   - val = env->macc[acc] & 0x00ff;
965   - val = (env->macc[acc] >> 32) & 0xff00;
966   - val |= (env->macc[acc + 1] << 16) & 0x00ff0000;
967   - val |= (env->macc[acc + 1] >> 16) & 0xff000000;
968   - set_op(PARAM1, val);
969   - FORCE_RET();
970   -}
971   -
972   -OP(get_mac_exti)
973   -{
974   - uint32_t val;
975   - int acc = PARAM2;
976   - val = (env->macc[acc] >> 32) & 0xffff;
977   - val |= (env->macc[acc + 1] >> 16) & 0xffff0000;
978   - set_op(PARAM1, val);
979   - FORCE_RET();
980   -}
981   -
982   -OP(set_macf)
983   -{
984   - int acc = PARAM2;
985   - int32_t val = get_op(PARAM1);
986   - env->macc[acc] = ((int64_t)val) << 8;
987   - env->macsr &= ~(MACSR_PAV0 << acc);
988   - FORCE_RET();
989   -}
990   -
991   -OP(set_macs)
992   -{
993   - int acc = PARAM2;
994   - int32_t val = get_op(PARAM1);
995   - env->macc[acc] = val;
996   - env->macsr &= ~(MACSR_PAV0 << acc);
997   - FORCE_RET();
998   -}
999   -
1000   -OP(set_macu)
1001   -{
1002   - int acc = PARAM2;
1003   - uint32_t val = get_op(PARAM1);
1004   - env->macc[acc] = val;
1005   - env->macsr &= ~(MACSR_PAV0 << acc);
1006   - FORCE_RET();
1007   -}
1008   -
1009   -OP(set_mac_extf)
1010   -{
1011   - int acc = PARAM2;
1012   - int32_t val = get_op(PARAM1);
1013   - int64_t res;
1014   - int32_t tmp;
1015   - res = env->macc[acc] & 0xffffffff00ull;
1016   - tmp = (int16_t)(val & 0xff00);
1017   - res |= ((int64_t)tmp) << 32;
1018   - res |= val & 0xff;
1019   - env->macc[acc] = res;
1020   - res = env->macc[acc + 1] & 0xffffffff00ull;
1021   - tmp = (val & 0xff000000);
1022   - res |= ((int64_t)tmp) << 16;
1023   - res |= (val >> 16) & 0xff;
1024   - env->macc[acc + 1] = res;
1025   -}
1026   -
1027   -OP(set_mac_exts)
1028   -{
1029   - int acc = PARAM2;
1030   - int32_t val = get_op(PARAM1);
1031   - int64_t res;
1032   - int32_t tmp;
1033   - res = (uint32_t)env->macc[acc];
1034   - tmp = (int16_t)val;
1035   - res |= ((int64_t)tmp) << 32;
1036   - env->macc[acc] = res;
1037   - res = (uint32_t)env->macc[acc + 1];
1038   - tmp = val & 0xffff0000;
1039   - res |= (int64_t)tmp << 16;
1040   - env->macc[acc + 1] = res;
1041   -}
1042   -
1043   -OP(set_mac_extu)
1044   -{
1045   - int acc = PARAM2;
1046   - int32_t val = get_op(PARAM1);
1047   - uint64_t res;
1048   - res = (uint32_t)env->macc[acc];
1049   - res |= ((uint64_t)(val & 0xffff)) << 32;
1050   - env->macc[acc] = res;
1051   - res = (uint32_t)env->macc[acc + 1];
1052   - res |= (uint64_t)(val & 0xffff0000) << 16;
1053   - env->macc[acc + 1] = res;
1054   -}
1055   -
1056   -OP(set_macsr)
1057   -{
1058   - m68k_set_macsr(env, get_op(PARAM1));
1059   -}
target-m68k/op_helper.c
  View file @e1f3808
... ... @@ -18,6 +18,7 @@
18 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 */
20 20 #include "exec.h"
  21 +#include "helpers.h"
21 22  
22 23 #if defined(CONFIG_USER_ONLY)
23 24  
... ... @@ -161,3 +162,71 @@ void do_interrupt(int is_hw)
161 162 }
162 163  
163 164 #endif
  165 +
  166 +static void raise_exception(int tt)
  167 +{
  168 + env->exception_index = tt;
  169 + cpu_loop_exit();
  170 +}
  171 +
  172 +void HELPER(raise_exception)(uint32_t tt)
  173 +{
  174 + raise_exception(tt);
  175 +}
  176 +
  177 +void HELPER(divu)(CPUState *env, uint32_t word)
  178 +{
  179 + uint32_t num;
  180 + uint32_t den;
  181 + uint32_t quot;
  182 + uint32_t rem;
  183 + uint32_t flags;
  184 +
  185 + num = env->div1;
  186 + den = env->div2;
  187 + /* ??? This needs to make sure the throwing location is accurate. */
  188 + if (den == 0)
  189 + raise_exception(EXCP_DIV0);
  190 + quot = num / den;
  191 + rem = num % den;
  192 + flags = 0;
  193 + /* Avoid using a PARAM1 of zero. This breaks dyngen because it uses
  194 + the address of a symbol, and gcc knows symbols can't have address
  195 + zero. */
  196 + if (word && quot > 0xffff)
  197 + flags |= CCF_V;
  198 + if (quot == 0)
  199 + flags |= CCF_Z;
  200 + else if ((int32_t)quot < 0)
  201 + flags |= CCF_N;
  202 + env->div1 = quot;
  203 + env->div2 = rem;
  204 + env->cc_dest = flags;
  205 +}
  206 +
  207 +void HELPER(divs)(CPUState *env, uint32_t word)
  208 +{
  209 + int32_t num;
  210 + int32_t den;
  211 + int32_t quot;
  212 + int32_t rem;
  213 + int32_t flags;
  214 +
  215 + num = env->div1;
  216 + den = env->div2;
  217 + if (den == 0)
  218 + raise_exception(EXCP_DIV0);
  219 + quot = num / den;
  220 + rem = num % den;
  221 + flags = 0;
  222 + if (word && quot != (int16_t)quot)
  223 + flags |= CCF_V;
  224 + if (quot == 0)
  225 + flags |= CCF_Z;
  226 + else if (quot < 0)
  227 + flags |= CCF_N;
  228 + env->div1 = quot;
  229 + env->div2 = rem;
  230 + env->cc_dest = flags;
  231 +}
  232 +
... ...
target-m68k/op_mem.h deleted 100644 → 0
  View file @3979144
1   -/* Load/store ops. */
2   -#define MEM_LD_OP(name,suffix) \
3   -OP(glue(glue(ld,name),MEMSUFFIX)) \
4   -{ \
5   - uint32_t addr = get_op(PARAM2); \
6   - set_op(PARAM1, glue(glue(ld,suffix),MEMSUFFIX)(addr)); \
7   - FORCE_RET(); \
8   -}
9   -
10   -MEM_LD_OP(8u32,ub)
11   -MEM_LD_OP(8s32,sb)
12   -MEM_LD_OP(16u32,uw)
13   -MEM_LD_OP(16s32,sw)
14   -MEM_LD_OP(32,l)
15   -
16   -#undef MEM_LD_OP
17   -
18   -#define MEM_ST_OP(name,suffix) \
19   -OP(glue(glue(st,name),MEMSUFFIX)) \
20   -{ \
21   - uint32_t addr = get_op(PARAM1); \
22   - glue(glue(st,suffix),MEMSUFFIX)(addr, get_op(PARAM2)); \
23   - FORCE_RET(); \
24   -}
25   -
26   -MEM_ST_OP(8,b)
27   -MEM_ST_OP(16,w)
28   -MEM_ST_OP(32,l)
29   -
30   -#undef MEM_ST_OP
31   -
32   -OP(glue(ldf64,MEMSUFFIX))
33   -{
34   - uint32_t addr = get_op(PARAM2);
35   - set_opf64(PARAM1, glue(ldfq,MEMSUFFIX)(addr));
36   - FORCE_RET();
37   -}
38   -
39   -OP(glue(stf64,MEMSUFFIX))
40   -{
41   - uint32_t addr = get_op(PARAM1);
42   - glue(stfq,MEMSUFFIX)(addr, get_opf64(PARAM2));
43   - FORCE_RET();
44   -}
45   -
46   -#undef MEMSUFFIX
target-m68k/qregs.def
  View file @e1f3808
1   -DEFO32(D0, dregs[0])
2   -DEFO32(D1, dregs[1])
3   -DEFO32(D2, dregs[2])
4   -DEFO32(D3, dregs[3])
5   -DEFO32(D4, dregs[4])
6   -DEFO32(D5, dregs[5])
7   -DEFO32(D6, dregs[6])
8   -DEFO32(D7, dregs[7])
9   -DEFO32(A0, aregs[0])
10   -DEFO32(A1, aregs[1])
11   -DEFO32(A2, aregs[2])
12   -DEFO32(A3, aregs[3])
13   -DEFO32(A4, aregs[4])
14   -DEFO32(A5, aregs[5])
15   -DEFO32(A6, aregs[6])
16   -DEFO32(SP, aregs[7]) /* A7 */
17   -DEFF64(F0, fregs[0])
18   -DEFF64(F1, fregs[1])
19   -DEFF64(F2, fregs[2])
20   -DEFF64(F3, fregs[3])
21   -DEFF64(F4, fregs[4])
22   -DEFF64(F5, fregs[5])
23   -DEFF64(F6, fregs[6])
24   -DEFF64(F7, fregs[7])
25 1 DEFF64(FP_RESULT, fp_result)
26 2 DEFO32(PC, pc)
27 3 DEFO32(SR, sr)
28 4 DEFO32(CC_OP, cc_op)
29   -DEFR(T0, AREG1, QMODE_I32)
30 5 DEFO32(CC_DEST, cc_dest)
31 6 DEFO32(CC_SRC, cc_src)
32 7 DEFO32(CC_X, cc_x)
33 8 DEFO32(DIV1, div1)
34 9 DEFO32(DIV2, div2)
35 10 DEFO32(EXCEPTION, exception_index)
  11 +DEFO32(HALTED, halted)
36 12 DEFO32(MACSR, macsr)
37 13 DEFO32(MAC_MASK, mac_mask)
... ...
target-m68k/translate.c
  View file @e1f3808
... ... @@ -23,16 +23,91 @@
23 23 #include <stdio.h>
24 24 #include <string.h>
25 25 #include <inttypes.h>
  26 +#include <assert.h>
26 27  
27 28 #include "config.h"
28 29 #include "cpu.h"
29 30 #include "exec-all.h"
30 31 #include "disas.h"
31 32 #include "tcg-op.h"
32   -#include "m68k-qreg.h"
  33 +
  34 +#define GEN_HELPER 1
  35 +#include "helpers.h"
33 36  
34 37 //#define DEBUG_DISPATCH 1
35 38  
  39 +#define DEFO32(name, offset) static TCGv QREG_##name;
  40 +#define DEFO64(name, offset) static TCGv QREG_##name;
  41 +#define DEFF64(name, offset) static TCGv QREG_##name;
  42 +#include "qregs.def"
  43 +#undef DEFO32
  44 +#undef DEFO64
  45 +#undef DEFF64
  46 +
  47 +static TCGv cpu_env;
  48 +
  49 +static char cpu_reg_names[3*8*3 + 5*4];
  50 +static TCGv cpu_dregs[8];
  51 +static TCGv cpu_aregs[8];
  52 +static TCGv cpu_fregs[8];
  53 +static TCGv cpu_macc[4];
  54 +
  55 +#define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
  56 +#define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
  57 +#define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
  58 +#define MACREG(acc) cpu_macc[acc]
  59 +#define QREG_SP cpu_aregs[7]
  60 +
  61 +static TCGv NULL_QREG;
  62 +#define IS_NULL_QREG(t) (GET_TCGV(t) == GET_TCGV(NULL_QREG))
  63 +/* Used to distinguish stores from bad addressing modes. */
  64 +static TCGv store_dummy;
  65 +
  66 +void m68k_tcg_init(void)
  67 +{
  68 + char *p;
  69 + int i;
  70 +
  71 +#define DEFO32(name, offset) QREG_##name = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, offset), #name);
  72 +#define DEFO64(name, offset) QREG_##name = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, offset), #name);
  73 +#define DEFF64(name, offset) DEFO64(name, offset)
  74 +#include "qregs.def"
  75 +#undef DEFO32
  76 +#undef DEFO64
  77 +#undef DEFF64
  78 +
  79 + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
  80 +
  81 + p = cpu_reg_names;
  82 + for (i = 0; i < 8; i++) {
  83 + sprintf(p, "D%d", i);
  84 + cpu_dregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  85 + offsetof(CPUM68KState, dregs[i]), p);
  86 + p += 3;
  87 + sprintf(p, "A%d", i);
  88 + cpu_aregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  89 + offsetof(CPUM68KState, aregs[i]), p);
  90 + p += 3;
  91 + sprintf(p, "F%d", i);
  92 + cpu_fregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  93 + offsetof(CPUM68KState, fregs[i]), p);
  94 + p += 3;
  95 + }
  96 + for (i = 0; i < 4; i++) {
  97 + sprintf(p, "ACC%d", i);
  98 + cpu_macc[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  99 + offsetof(CPUM68KState, macc[i]), p);
  100 + p += 5;
  101 + }
  102 +
  103 + NULL_QREG = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, -4, "NULL");
  104 + store_dummy = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, -8, "NULL");
  105 +
  106 +#define DEF_HELPER(name, ret, args) \
  107 + tcg_register_helper(HELPER(name), #name);
  108 +#include "helpers.h"
  109 +}
  110 +
36 111 static inline void qemu_assert(int cond, const char *msg)
37 112 {
38 113 if (!cond) {
... ... @@ -53,6 +128,7 @@ typedef struct DisasContext {
53 128 struct TranslationBlock *tb;
54 129 int singlestep_enabled;
55 130 int is_mem;
  131 + TCGv mactmp;
56 132 } DisasContext;
57 133  
58 134 #define DISAS_JUMP_NEXT 4
... ... @@ -71,36 +147,12 @@ static void *gen_throws_exception;
71 147 extern FILE *logfile;
72 148 extern int loglevel;
73 149  
74   -#if defined(CONFIG_USER_ONLY)
75   -#define gen_st(s, name, addr, val) gen_op_st##name##_raw(addr, val)
76   -#define gen_ld(s, name, val, addr) gen_op_ld##name##_raw(val, addr)
77   -#else
78   -#define gen_st(s, name, addr, val) do { \
79   - if (IS_USER(s)) \
80   - gen_op_st##name##_user(addr, val); \
81   - else \
82   - gen_op_st##name##_kernel(addr, val); \
83   - } while (0)
84   -#define gen_ld(s, name, val, addr) do { \
85   - if (IS_USER(s)) \
86   - gen_op_ld##name##_user(val, addr); \
87   - else \
88   - gen_op_ld##name##_kernel(val, addr); \
89   - } while (0)
90   -#endif
91   -
92   -#include "op-hacks.h"
93   -
94 150 #define OS_BYTE 0
95 151 #define OS_WORD 1
96 152 #define OS_LONG 2
97 153 #define OS_SINGLE 4
98 154 #define OS_DOUBLE 5
99 155  
100   -#define DREG(insn, pos) (((insn >> pos) & 7) + QREG_D0)
101   -#define AREG(insn, pos) (((insn >> pos) & 7) + QREG_A0)
102   -#define FREG(insn, pos) (((insn >> pos) & 7) + QREG_F0)
103   -
104 156 typedef void (*disas_proc)(DisasContext *, uint16_t);
105 157  
106 158 #ifdef DEBUG_DISPATCH
... ... @@ -115,38 +167,62 @@ typedef void (*disas_proc)(DisasContext *, uint16_t);
115 167 static void disas_##name (DisasContext *s, uint16_t insn)
116 168 #endif
117 169  
  170 +/* FIXME: Remove this. */
  171 +#define gen_im32(val) tcg_const_i32(val)
  172 +
  173 +/* Fake floating point. */
  174 +#define TCG_TYPE_F32 TCG_TYPE_I32
  175 +#define TCG_TYPE_F64 TCG_TYPE_I64
  176 +#define tcg_gen_mov_f64 tcg_gen_mov_i64
  177 +#define tcg_gen_qemu_ldf32 tcg_gen_qemu_ld32u
  178 +#define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
  179 +#define tcg_gen_qemu_stf32 tcg_gen_qemu_st32
  180 +#define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
  181 +#define gen_helper_pack_32_f32 tcg_gen_mov_i32
  182 +#define gen_helper_pack_f32_32 tcg_gen_mov_i32
  183 +
  184 +#define QMODE_I32 TCG_TYPE_I32
  185 +#define QMODE_I64 TCG_TYPE_I64
  186 +#define QMODE_F32 TCG_TYPE_F32
  187 +#define QMODE_F64 TCG_TYPE_F64
  188 +static inline TCGv gen_new_qreg(int mode)
  189 +{
  190 + return tcg_temp_new(mode);
  191 +}
  192 +
118 193 /* Generate a load from the specified address. Narrow values are
119 194 sign extended to full register width. */
120   -static inline int gen_load(DisasContext * s, int opsize, int addr, int sign)
  195 +static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
121 196 {
122   - int tmp;
  197 + TCGv tmp;
  198 + int index = IS_USER(s);
123 199 s->is_mem = 1;
124 200 switch(opsize) {
125 201 case OS_BYTE:
126 202 tmp = gen_new_qreg(QMODE_I32);
127 203 if (sign)
128   - gen_ld(s, 8s32, tmp, addr);
  204 + tcg_gen_qemu_ld8s(tmp, addr, index);
129 205 else
130   - gen_ld(s, 8u32, tmp, addr);
  206 + tcg_gen_qemu_ld8u(tmp, addr, index);
131 207 break;
132 208 case OS_WORD:
133 209 tmp = gen_new_qreg(QMODE_I32);
134 210 if (sign)
135   - gen_ld(s, 16s32, tmp, addr);
  211 + tcg_gen_qemu_ld16s(tmp, addr, index);
136 212 else
137   - gen_ld(s, 16u32, tmp, addr);
  213 + tcg_gen_qemu_ld16u(tmp, addr, index);
138 214 break;
139 215 case OS_LONG:
140 216 tmp = gen_new_qreg(QMODE_I32);
141   - gen_ld(s, 32, tmp, addr);
  217 + tcg_gen_qemu_ld32u(tmp, addr, index);
142 218 break;
143 219 case OS_SINGLE:
144 220 tmp = gen_new_qreg(QMODE_F32);
145   - gen_ld(s, f32, tmp, addr);
  221 + tcg_gen_qemu_ldf32(tmp, addr, index);
146 222 break;
147 223 case OS_DOUBLE:
148 224 tmp = gen_new_qreg(QMODE_F64);
149   - gen_ld(s, f64, tmp, addr);
  225 + tcg_gen_qemu_ldf64(tmp, addr, index);
150 226 break;
151 227 default:
152 228 qemu_assert(0, "bad load size");
... ... @@ -156,24 +232,25 @@ static inline int gen_load(DisasContext * s, int opsize, int addr, int sign)
156 232 }
157 233  
158 234 /* Generate a store. */
159   -static inline void gen_store(DisasContext *s, int opsize, int addr, int val)
  235 +static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
160 236 {
  237 + int index = IS_USER(s);
161 238 s->is_mem = 1;
162 239 switch(opsize) {
163 240 case OS_BYTE:
164   - gen_st(s, 8, addr, val);
  241 + tcg_gen_qemu_st8(val, addr, index);
165 242 break;
166 243 case OS_WORD:
167   - gen_st(s, 16, addr, val);
  244 + tcg_gen_qemu_st16(val, addr, index);
168 245 break;
169 246 case OS_LONG:
170   - gen_st(s, 32, addr, val);
  247 + tcg_gen_qemu_st32(val, addr, index);
171 248 break;
172 249 case OS_SINGLE:
173   - gen_st(s, f32, addr, val);
  250 + tcg_gen_qemu_stf32(val, addr, index);
174 251 break;
175 252 case OS_DOUBLE:
176   - gen_st(s, f64, addr, val);
  253 + tcg_gen_qemu_stf64(val, addr, index);
177 254 break;
178 255 default:
179 256 qemu_assert(0, "bad store size");
... ... @@ -181,15 +258,22 @@ static inline void gen_store(DisasContext *s, int opsize, int addr, int val)
181 258 gen_throws_exception = gen_last_qop;
182 259 }
183 260  
  261 +typedef enum {
  262 + EA_STORE,
  263 + EA_LOADU,
  264 + EA_LOADS
  265 +} ea_what;
  266 +
184 267 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
185 268 otherwise generate a store. */
186   -static int gen_ldst(DisasContext *s, int opsize, int addr, int val)
  269 +static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
  270 + ea_what what)
187 271 {
188   - if (val > 0) {
  272 + if (what == EA_STORE) {
189 273 gen_store(s, opsize, addr, val);
190   - return 0;
  274 + return store_dummy;
191 275 } else {
192   - return gen_load(s, opsize, addr, val != 0);
  276 + return gen_load(s, opsize, addr, what == EA_LOADS);
193 277 }
194 278 }
195 279  
... ... @@ -205,32 +289,32 @@ static inline uint32_t read_im32(DisasContext *s)
205 289 }
206 290  
207 291 /* Calculate and address index. */
208   -static int gen_addr_index(uint16_t ext, int tmp)
  292 +static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
209 293 {
210   - int add;
  294 + TCGv add;
211 295 int scale;
212 296  
213 297 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
214 298 if ((ext & 0x800) == 0) {
215   - gen_op_ext16s32(tmp, add);
  299 + tcg_gen_ext16s_i32(tmp, add);
216 300 add = tmp;
217 301 }
218 302 scale = (ext >> 9) & 3;
219 303 if (scale != 0) {
220   - gen_op_shl32(tmp, add, gen_im32(scale));
  304 + tcg_gen_shli_i32(tmp, add, scale);
221 305 add = tmp;
222 306 }
223 307 return add;
224 308 }
225 309  
226   -/* Handle a base + index + displacement effective addresss. A base of
227   - -1 means pc-relative. */
228   -static int gen_lea_indexed(DisasContext *s, int opsize, int base)
  310 +/* Handle a base + index + displacement effective addresss.
  311 + A NULL_QREG base means pc-relative. */
  312 +static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
229 313 {
230 314 uint32_t offset;
231 315 uint16_t ext;
232   - int add;
233   - int tmp;
  316 + TCGv add;
  317 + TCGv tmp;
234 318 uint32_t bd, od;
235 319  
236 320 offset = s->pc;
... ... @@ -238,12 +322,12 @@ static int gen_lea_indexed(DisasContext *s, int opsize, int base)
238 322 s->pc += 2;
239 323  
240 324 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
241   - return -1;
  325 + return NULL_QREG;
242 326  
243 327 if (ext & 0x100) {
244 328 /* full extension word format */
245 329 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
246   - return -1;
  330 + return NULL_QREG;
247 331  
248 332 if ((ext & 0x30) > 0x10) {
249 333 /* base displacement */
... ... @@ -261,24 +345,24 @@ static int gen_lea_indexed(DisasContext *s, int opsize, int base)
261 345 /* pre-index */
262 346 add = gen_addr_index(ext, tmp);
263 347 } else {
264   - add = QREG_NULL;
  348 + add = NULL_QREG;
265 349 }
266 350 if ((ext & 0x80) == 0) {
267 351 /* base not suppressed */
268   - if (base == -1) {
  352 + if (IS_NULL_QREG(base)) {
269 353 base = gen_im32(offset + bd);
270 354 bd = 0;
271 355 }
272   - if (add) {
273   - gen_op_add32(tmp, add, base);
  356 + if (!IS_NULL_QREG(add)) {
  357 + tcg_gen_add_i32(tmp, add, base);
274 358 add = tmp;
275 359 } else {
276 360 add = base;
277 361 }
278 362 }
279   - if (add) {
  363 + if (!IS_NULL_QREG(add)) {
280 364 if (bd != 0) {
281   - gen_op_add32(tmp, add, gen_im32(bd));
  365 + tcg_gen_addi_i32(tmp, add, bd);
282 366 add = tmp;
283 367 }
284 368 } else {
... ... @@ -289,7 +373,7 @@ static int gen_lea_indexed(DisasContext *s, int opsize, int base)
289 373 base = gen_load(s, OS_LONG, add, 0);
290 374 if ((ext & 0x44) == 4) {
291 375 add = gen_addr_index(ext, tmp);
292   - gen_op_add32(tmp, add, base);
  376 + tcg_gen_add_i32(tmp, add, base);
293 377 add = tmp;
294 378 } else {
295 379 add = base;
... ... @@ -306,7 +390,7 @@ static int gen_lea_indexed(DisasContext *s, int opsize, int base)
306 390 od = 0;
307 391 }
308 392 if (od != 0) {
309   - gen_op_add32(tmp, add, gen_im32(od));
  393 + tcg_gen_addi_i32(tmp, add, od);
310 394 add = tmp;
311 395 }
312 396 }
... ... @@ -314,12 +398,12 @@ static int gen_lea_indexed(DisasContext *s, int opsize, int base)
314 398 /* brief extension word format */
315 399 tmp = gen_new_qreg(QMODE_I32);
316 400 add = gen_addr_index(ext, tmp);
317   - if (base != -1) {
318   - gen_op_add32(tmp, add, base);
  401 + if (!IS_NULL_QREG(base)) {
  402 + tcg_gen_add_i32(tmp, add, base);
319 403 if ((int8_t)ext)
320   - gen_op_add32(tmp, tmp, gen_im32((int8_t)ext));
  404 + tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
321 405 } else {
322   - gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext));
  406 + tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
323 407 }
324 408 add = tmp;
325 409 }
... ... @@ -330,7 +414,7 @@ static int gen_lea_indexed(DisasContext *s, int opsize, int base)
330 414 static inline void gen_flush_cc_op(DisasContext *s)
331 415 {
332 416 if (s->cc_op != CC_OP_DYNAMIC)
333   - gen_op_mov32(QREG_CC_OP, gen_im32(s->cc_op));
  417 + tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
334 418 }
335 419  
336 420 /* Evaluate all the CC flags. */
... ... @@ -339,10 +423,22 @@ static inline void gen_flush_flags(DisasContext *s)
339 423 if (s->cc_op == CC_OP_FLAGS)
340 424 return;
341 425 gen_flush_cc_op(s);
342   - gen_op_flush_flags();
  426 + gen_helper_flush_flags(cpu_env, QREG_CC_OP);
343 427 s->cc_op = CC_OP_FLAGS;
344 428 }
345 429  
  430 +static void gen_logic_cc(DisasContext *s, TCGv val)
  431 +{
  432 + tcg_gen_mov_i32(QREG_CC_DEST, val);
  433 + s->cc_op = CC_OP_LOGIC;
  434 +}
  435 +
  436 +static void gen_update_cc_add(TCGv dest, TCGv src)
  437 +{
  438 + tcg_gen_mov_i32(QREG_CC_DEST, dest);
  439 + tcg_gen_mov_i32(QREG_CC_SRC, src);
  440 +}
  441 +
346 442 static inline int opsize_bytes(int opsize)
347 443 {
348 444 switch (opsize) {
... ... @@ -358,27 +454,27 @@ static inline int opsize_bytes(int opsize)
358 454  
359 455 /* Assign value to a register. If the width is less than the register width
360 456 only the low part of the register is set. */
361   -static void gen_partset_reg(int opsize, int reg, int val)
  457 +static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
362 458 {
363   - int tmp;
  459 + TCGv tmp;
364 460 switch (opsize) {
365 461 case OS_BYTE:
366   - gen_op_and32(reg, reg, gen_im32(0xffffff00));
  462 + tcg_gen_andi_i32(reg, reg, 0xffffff00);
367 463 tmp = gen_new_qreg(QMODE_I32);
368   - gen_op_and32(tmp, val, gen_im32(0xff));
369   - gen_op_or32(reg, reg, tmp);
  464 + tcg_gen_ext8u_i32(tmp, val);
  465 + tcg_gen_or_i32(reg, reg, tmp);
370 466 break;
371 467 case OS_WORD:
372   - gen_op_and32(reg, reg, gen_im32(0xffff0000));
  468 + tcg_gen_andi_i32(reg, reg, 0xffff0000);
373 469 tmp = gen_new_qreg(QMODE_I32);
374   - gen_op_and32(tmp, val, gen_im32(0xffff));
375   - gen_op_or32(reg, reg, tmp);
  470 + tcg_gen_ext16u_i32(tmp, val);
  471 + tcg_gen_or_i32(reg, reg, tmp);
376 472 break;
377 473 case OS_LONG:
378   - gen_op_mov32(reg, val);
  474 + tcg_gen_mov_i32(reg, val);
379 475 break;
380 476 case OS_SINGLE:
381   - gen_op_pack_32_f32(reg, val);
  477 + gen_helper_pack_32_f32(reg, val);
382 478 break;
383 479 default:
384 480 qemu_assert(0, "Bad operand size");
... ... @@ -387,31 +483,31 @@ static void gen_partset_reg(int opsize, int reg, int val)
387 483 }
388 484  
389 485 /* Sign or zero extend a value. */
390   -static inline int gen_extend(int val, int opsize, int sign)
  486 +static inline TCGv gen_extend(TCGv val, int opsize, int sign)
391 487 {
392   - int tmp;
  488 + TCGv tmp;
393 489  
394 490 switch (opsize) {
395 491 case OS_BYTE:
396 492 tmp = gen_new_qreg(QMODE_I32);
397 493 if (sign)
398   - gen_op_ext8s32(tmp, val);
  494 + tcg_gen_ext8s_i32(tmp, val);
399 495 else
400   - gen_op_ext8u32(tmp, val);
  496 + tcg_gen_ext8u_i32(tmp, val);
401 497 break;
402 498 case OS_WORD:
403 499 tmp = gen_new_qreg(QMODE_I32);
404 500 if (sign)
405   - gen_op_ext16s32(tmp, val);
  501 + tcg_gen_ext16s_i32(tmp, val);
406 502 else
407   - gen_op_ext16u32(tmp, val);
  503 + tcg_gen_ext16u_i32(tmp, val);
408 504 break;
409 505 case OS_LONG:
410 506 tmp = val;
411 507 break;
412 508 case OS_SINGLE:
413 509 tmp = gen_new_qreg(QMODE_F32);
414   - gen_op_pack_f32_32(tmp, val);
  510 + gen_helper_pack_f32_32(tmp, val);
415 511 break;
416 512 default:
417 513 qemu_assert(0, "Bad operand size");
... ... @@ -421,39 +517,37 @@ static inline int gen_extend(int val, int opsize, int sign)
421 517  
422 518 /* Generate code for an "effective address". Does not adjust the base
423 519 register for autoincrememnt addressing modes. */
424   -static int gen_lea(DisasContext *s, uint16_t insn, int opsize)
  520 +static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
425 521 {
426   - int reg;
427   - int tmp;
  522 + TCGv reg;
  523 + TCGv tmp;
428 524 uint16_t ext;
429 525 uint32_t offset;
430 526  
431   - reg = insn & 7;
432 527 switch ((insn >> 3) & 7) {
433 528 case 0: /* Data register direct. */
434 529 case 1: /* Address register direct. */
435   - return -1;
  530 + return NULL_QREG;
436 531 case 2: /* Indirect register */
437 532 case 3: /* Indirect postincrement. */
438   - reg += QREG_A0;
439   - return reg;
  533 + return AREG(insn, 0);
440 534 case 4: /* Indirect predecrememnt. */
441   - reg += QREG_A0;
  535 + reg = AREG(insn, 0);
442 536 tmp = gen_new_qreg(QMODE_I32);
443   - gen_op_sub32(tmp, reg, gen_im32(opsize_bytes(opsize)));
  537 + tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
444 538 return tmp;
445 539 case 5: /* Indirect displacement. */
446   - reg += QREG_A0;
  540 + reg = AREG(insn, 0);
447 541 tmp = gen_new_qreg(QMODE_I32);
448 542 ext = lduw_code(s->pc);
449 543 s->pc += 2;
450   - gen_op_add32(tmp, reg, gen_im32((int16_t)ext));
  544 + tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
451 545 return tmp;
452 546 case 6: /* Indirect index + displacement. */
453   - reg += QREG_A0;
  547 + reg = AREG(insn, 0);
454 548 return gen_lea_indexed(s, opsize, reg);
455 549 case 7: /* Other */
456   - switch (reg) {
  550 + switch (insn & 7) {
457 551 case 0: /* Absolute short. */
458 552 offset = ldsw_code(s->pc);
459 553 s->pc += 2;
... ... @@ -468,117 +562,116 @@ static int gen_lea(DisasContext *s, uint16_t insn, int opsize)
468 562 s->pc += 2;
469 563 return gen_im32(offset);
470 564 case 3: /* pc index+displacement. */
471   - return gen_lea_indexed(s, opsize, -1);
  565 + return gen_lea_indexed(s, opsize, NULL_QREG);
472 566 case 4: /* Immediate. */
473 567 default:
474   - return -1;
  568 + return NULL_QREG;
475 569 }
476 570 }
477 571 /* Should never happen. */
478   - return -1;
  572 + return NULL_QREG;
479 573 }
480 574  
481 575 /* Helper function for gen_ea. Reuse the computed address between the
482 576 for read/write operands. */
483   -static inline int gen_ea_once(DisasContext *s, uint16_t insn, int opsize,
484   - int val, int *addrp)
  577 +static inline TCGv gen_ea_once(DisasContext *s, uint16_t insn, int opsize,
  578 + TCGv val, TCGv *addrp, ea_what what)
485 579 {
486   - int tmp;
  580 + TCGv tmp;
487 581  
488   - if (addrp && val > 0) {
  582 + if (addrp && what == EA_STORE) {
489 583 tmp = *addrp;
490 584 } else {
491 585 tmp = gen_lea(s, insn, opsize);
492   - if (tmp == -1)
493   - return -1;
  586 + if (IS_NULL_QREG(tmp))
  587 + return tmp;
494 588 if (addrp)
495 589 *addrp = tmp;
496 590 }
497   - return gen_ldst(s, opsize, tmp, val);
  591 + return gen_ldst(s, opsize, tmp, val, what);
498 592 }
499 593  
500 594 /* Generate code to load/store a value ito/from an EA. If VAL > 0 this is
501 595 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
502 596 ADDRP is non-null for readwrite operands. */
503   -static int gen_ea(DisasContext *s, uint16_t insn, int opsize, int val,
504   - int *addrp)
  597 +static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
  598 + TCGv *addrp, ea_what what)
505 599 {
506   - int reg;
507   - int result;
  600 + TCGv reg;
  601 + TCGv result;
508 602 uint32_t offset;
509 603  
510   - reg = insn & 7;
511 604 switch ((insn >> 3) & 7) {
512 605 case 0: /* Data register direct. */
513   - reg += QREG_D0;
514   - if (val > 0) {
  606 + reg = DREG(insn, 0);
  607 + if (what == EA_STORE) {
515 608 gen_partset_reg(opsize, reg, val);
516   - return 0;
  609 + return store_dummy;
517 610 } else {
518   - return gen_extend(reg, opsize, val);
  611 + return gen_extend(reg, opsize, what == EA_LOADS);
519 612 }
520 613 case 1: /* Address register direct. */
521   - reg += QREG_A0;
522   - if (val > 0) {
523   - gen_op_mov32(reg, val);
524   - return 0;
  614 + reg = AREG(insn, 0);
  615 + if (what == EA_STORE) {
  616 + tcg_gen_mov_i32(reg, val);
  617 + return store_dummy;
525 618 } else {
526   - return gen_extend(reg, opsize, val);
  619 + return gen_extend(reg, opsize, what == EA_LOADS);
527 620 }
528 621 case 2: /* Indirect register */
529   - reg += QREG_A0;
530   - return gen_ldst(s, opsize, reg, val);
  622 + reg = AREG(insn, 0);
  623 + return gen_ldst(s, opsize, reg, val, what);
531 624 case 3: /* Indirect postincrement. */
532   - reg += QREG_A0;
533   - result = gen_ldst(s, opsize, reg, val);
  625 + reg = AREG(insn, 0);
  626 + result = gen_ldst(s, opsize, reg, val, what);
534 627 /* ??? This is not exception safe. The instruction may still
535 628 fault after this point. */
536   - if (val > 0 || !addrp)
537   - gen_op_add32(reg, reg, gen_im32(opsize_bytes(opsize)));
  629 + if (what == EA_STORE || !addrp)
  630 + tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
538 631 return result;
539 632 case 4: /* Indirect predecrememnt. */
540 633 {
541   - int tmp;
542   - if (addrp && val > 0) {
  634 + TCGv tmp;
  635 + if (addrp && what == EA_STORE) {
543 636 tmp = *addrp;
544 637 } else {
545 638 tmp = gen_lea(s, insn, opsize);
546   - if (tmp == -1)
547   - return -1;
  639 + if (IS_NULL_QREG(tmp))
  640 + return tmp;
548 641 if (addrp)
549 642 *addrp = tmp;
550 643 }
551   - result = gen_ldst(s, opsize, tmp, val);
  644 + result = gen_ldst(s, opsize, tmp, val, what);
552 645 /* ??? This is not exception safe. The instruction may still
553 646 fault after this point. */
554   - if (val > 0 || !addrp) {
555   - reg += QREG_A0;
556   - gen_op_mov32(reg, tmp);
  647 + if (what == EA_STORE || !addrp) {
  648 + reg = AREG(insn, 0);
  649 + tcg_gen_mov_i32(reg, tmp);
557 650 }
558 651 }
559 652 return result;
560 653 case 5: /* Indirect displacement. */
561 654 case 6: /* Indirect index + displacement. */
562   - return gen_ea_once(s, insn, opsize, val, addrp);
  655 + return gen_ea_once(s, insn, opsize, val, addrp, what);
563 656 case 7: /* Other */
564   - switch (reg) {
  657 + switch (insn & 7) {
565 658 case 0: /* Absolute short. */
566 659 case 1: /* Absolute long. */
567 660 case 2: /* pc displacement */
568 661 case 3: /* pc index+displacement. */
569   - return gen_ea_once(s, insn, opsize, val, addrp);
  662 + return gen_ea_once(s, insn, opsize, val, addrp, what);
570 663 case 4: /* Immediate. */
571 664 /* Sign extend values for consistency. */
572 665 switch (opsize) {
573 666 case OS_BYTE:
574   - if (val)
  667 + if (what == EA_LOADS)
575 668 offset = ldsb_code(s->pc + 1);
576 669 else
577 670 offset = ldub_code(s->pc + 1);
578 671 s->pc += 2;
579 672 break;
580 673 case OS_WORD:
581   - if (val)
  674 + if (what == EA_LOADS)
582 675 offset = ldsw_code(s->pc);
583 676 else
584 677 offset = lduw_code(s->pc);
... ... @@ -590,121 +683,112 @@ static int gen_ea(DisasContext *s, uint16_t insn, int opsize, int val,
590 683 default:
591 684 qemu_assert(0, "Bad immediate operand");
592 685 }
593   - return gen_im32(offset);
  686 + return tcg_const_i32(offset);
594 687 default:
595   - return -1;
  688 + return NULL_QREG;
596 689 }
597 690 }
598 691 /* Should never happen. */
599   - return -1;
600   -}
601   -
602   -static void gen_logic_cc(DisasContext *s, int val)
603   -{
604   - gen_op_logic_cc(val);
605   - s->cc_op = CC_OP_LOGIC;
  692 + return NULL_QREG;
606 693 }
607 694  
  695 +/* This generates a conditional branch, clobbering all temporaries. */
608 696 static void gen_jmpcc(DisasContext *s, int cond, int l1)
609 697 {
610   - int tmp;
  698 + TCGv tmp;
611 699  
  700 + /* TODO: Optimize compare/branch pairs rather than always flushing
  701 + flag state to CC_OP_FLAGS. */
612 702 gen_flush_flags(s);
613 703 switch (cond) {
614 704 case 0: /* T */
615   - gen_op_jmp_im(l1);
  705 + tcg_gen_br(l1);
616 706 break;
617 707 case 1: /* F */
618 708 break;
619 709 case 2: /* HI (!C && !Z) */
620 710 tmp = gen_new_qreg(QMODE_I32);
621   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_C | CCF_Z));
622   - gen_op_jmp_z32(tmp, l1);
  711 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
  712 + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
623 713 break;
624 714 case 3: /* LS (C || Z) */
625 715 tmp = gen_new_qreg(QMODE_I32);
626   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_C | CCF_Z));
627   - gen_op_jmp_nz32(tmp, l1);
  716 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
  717 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
628 718 break;
629 719 case 4: /* CC (!C) */
630 720 tmp = gen_new_qreg(QMODE_I32);
631   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_C));
632   - gen_op_jmp_z32(tmp, l1);
  721 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
  722 + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
633 723 break;
634 724 case 5: /* CS (C) */
635 725 tmp = gen_new_qreg(QMODE_I32);
636   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_C));
637   - gen_op_jmp_nz32(tmp, l1);
  726 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
  727 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
638 728 break;
639 729 case 6: /* NE (!Z) */
640 730 tmp = gen_new_qreg(QMODE_I32);
641   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_Z));
642   - gen_op_jmp_z32(tmp, l1);
  731 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
  732 + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
643 733 break;
644 734 case 7: /* EQ (Z) */
645 735 tmp = gen_new_qreg(QMODE_I32);
646   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_Z));
647   - gen_op_jmp_nz32(tmp, l1);
  736 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
  737 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
648 738 break;
649 739 case 8: /* VC (!V) */
650 740 tmp = gen_new_qreg(QMODE_I32);
651   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_V));
652   - gen_op_jmp_z32(tmp, l1);
  741 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
  742 + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
653 743 break;
654 744 case 9: /* VS (V) */
655 745 tmp = gen_new_qreg(QMODE_I32);
656   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_V));
657   - gen_op_jmp_nz32(tmp, l1);
  746 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
  747 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
658 748 break;
659 749 case 10: /* PL (!N) */
660 750 tmp = gen_new_qreg(QMODE_I32);
661   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_N));
662   - gen_op_jmp_z32(tmp, l1);
  751 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
  752 + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
663 753 break;
664 754 case 11: /* MI (N) */
665 755 tmp = gen_new_qreg(QMODE_I32);
666   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_N));
667   - gen_op_jmp_nz32(tmp, l1);
  756 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
  757 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
668 758 break;
669 759 case 12: /* GE (!(N ^ V)) */
670 760 tmp = gen_new_qreg(QMODE_I32);
671   - gen_op_shr32(tmp, QREG_CC_DEST, gen_im32(2));
672   - gen_op_xor32(tmp, tmp, QREG_CC_DEST);
673   - gen_op_and32(tmp, tmp, gen_im32(CCF_V));
674   - gen_op_jmp_z32(tmp, l1);
  761 + assert(CCF_V == (CCF_N >> 2));
  762 + tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
  763 + tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
  764 + tcg_gen_andi_i32(tmp, tmp, CCF_V);
  765 + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
675 766 break;
676 767 case 13: /* LT (N ^ V) */
677 768 tmp = gen_new_qreg(QMODE_I32);
678   - gen_op_shr32(tmp, QREG_CC_DEST, gen_im32(2));
679   - gen_op_xor32(tmp, tmp, QREG_CC_DEST);
680   - gen_op_and32(tmp, tmp, gen_im32(CCF_V));
681   - gen_op_jmp_nz32(tmp, l1);
  769 + assert(CCF_V == (CCF_N >> 2));
  770 + tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
  771 + tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
  772 + tcg_gen_andi_i32(tmp, tmp, CCF_V);
  773 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
682 774 break;
683 775 case 14: /* GT (!(Z || (N ^ V))) */
684   - {
685   - int l2;
686   - l2 = gen_new_label();
687   - tmp = gen_new_qreg(QMODE_I32);
688   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_Z));
689   - gen_op_jmp_nz32(tmp, l2);
690   - tmp = gen_new_qreg(QMODE_I32);
691   - gen_op_shr32(tmp, QREG_CC_DEST, gen_im32(2));
692   - gen_op_xor32(tmp, tmp, QREG_CC_DEST);
693   - gen_op_and32(tmp, tmp, gen_im32(CCF_V));
694   - gen_op_jmp_nz32(tmp, l2);
695   - gen_op_jmp_im(l1);
696   - gen_set_label(l2);
697   - }
  776 + tmp = gen_new_qreg(QMODE_I32);
  777 + assert(CCF_V == (CCF_N >> 2));
  778 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
  779 + tcg_gen_shri_i32(tmp, tmp, 2);
  780 + tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
  781 + tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
  782 + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
698 783 break;
699 784 case 15: /* LE (Z || (N ^ V)) */
700 785 tmp = gen_new_qreg(QMODE_I32);
701   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_Z));
702   - gen_op_jmp_nz32(tmp, l1);
703   - tmp = gen_new_qreg(QMODE_I32);
704   - gen_op_shr32(tmp, QREG_CC_DEST, gen_im32(2));
705   - gen_op_xor32(tmp, tmp, QREG_CC_DEST);
706   - gen_op_and32(tmp, tmp, gen_im32(CCF_V));
707   - gen_op_jmp_nz32(tmp, l1);
  786 + assert(CCF_V == (CCF_N >> 2));
  787 + tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
  788 + tcg_gen_shri_i32(tmp, tmp, 2);
  789 + tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
  790 + tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
  791 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
708 792 break;
709 793 default:
710 794 /* Should ever happen. */
... ... @@ -716,14 +800,16 @@ DISAS_INSN(scc)
716 800 {
717 801 int l1;
718 802 int cond;
719   - int reg;
  803 + TCGv reg;
720 804  
721 805 l1 = gen_new_label();
722 806 cond = (insn >> 8) & 0xf;
723 807 reg = DREG(insn, 0);
724   - gen_op_and32(reg, reg, gen_im32(0xffffff00));
  808 + tcg_gen_andi_i32(reg, reg, 0xffffff00);
  809 + /* This is safe because we modify the reg directly, with no other values
  810 + live. */
725 811 gen_jmpcc(s, cond ^ 1, l1);
726   - gen_op_or32(reg, reg, gen_im32(0xff));
  812 + tcg_gen_ori_i32(reg, reg, 0xff);
727 813 gen_set_label(l1);
728 814 }
729 815  
... ... @@ -731,23 +817,31 @@ DISAS_INSN(scc)
731 817 static void gen_lookup_tb(DisasContext *s)
732 818 {
733 819 gen_flush_cc_op(s);
734   - gen_op_mov32(QREG_PC, gen_im32(s->pc));
  820 + tcg_gen_movi_i32(QREG_PC, s->pc);
735 821 s->is_jmp = DISAS_UPDATE;
736 822 }
737 823  
738   -/* Generate a jump to to the address in qreg DEST. */
739   -static void gen_jmp(DisasContext *s, int dest)
  824 +/* Generate a jump to an immediate address. */
  825 +static void gen_jmp_im(DisasContext *s, uint32_t dest)
  826 +{
  827 + gen_flush_cc_op(s);
  828 + tcg_gen_movi_i32(QREG_PC, dest);
  829 + s->is_jmp = DISAS_JUMP;
  830 +}
  831 +
  832 +/* Generate a jump to the address in qreg DEST. */
  833 +static void gen_jmp(DisasContext *s, TCGv dest)
740 834 {
741 835 gen_flush_cc_op(s);
742   - gen_op_mov32(QREG_PC, dest);
  836 + tcg_gen_mov_i32(QREG_PC, dest);
743 837 s->is_jmp = DISAS_JUMP;
744 838 }
745 839  
746 840 static void gen_exception(DisasContext *s, uint32_t where, int nr)
747 841 {
748 842 gen_flush_cc_op(s);
749   - gen_jmp(s, gen_im32(where));
750   - gen_op_raise_exception(nr);
  843 + gen_jmp_im(s, where);
  844 + gen_helper_raise_exception(tcg_const_i32(nr));
751 845 }
752 846  
753 847 static inline void gen_addr_fault(DisasContext *s)
... ... @@ -755,17 +849,17 @@ static inline void gen_addr_fault(DisasContext *s)
755 849 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
756 850 }
757 851  
758   -#define SRC_EA(result, opsize, val, addrp) do { \
759   - result = gen_ea(s, insn, opsize, val, addrp); \
760   - if (result == -1) { \
  852 +#define SRC_EA(result, opsize, op_sign, addrp) do { \
  853 + result = gen_ea(s, insn, opsize, NULL_QREG, addrp, op_sign ? EA_LOADS : EA_LOADU); \
  854 + if (IS_NULL_QREG(result)) { \
761 855 gen_addr_fault(s); \
762 856 return; \
763 857 } \
764 858 } while (0)
765 859  
766 860 #define DEST_EA(insn, opsize, val, addrp) do { \
767   - int ea_result = gen_ea(s, insn, opsize, val, addrp); \
768   - if (ea_result == -1) { \
  861 + TCGv ea_result = gen_ea(s, insn, opsize, val, addrp, EA_STORE); \
  862 + if (IS_NULL_QREG(ea_result)) { \
769 863 gen_addr_fault(s); \
770 864 return; \
771 865 } \
... ... @@ -782,10 +876,10 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
782 876 } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
783 877 (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
784 878 tcg_gen_goto_tb(n);
785   - gen_op_mov32(QREG_PC, gen_im32(dest));
  879 + tcg_gen_movi_i32(QREG_PC, dest);
786 880 tcg_gen_exit_tb((long)tb + n);
787 881 } else {
788   - gen_jmp(s, gen_im32(dest));
  882 + gen_jmp_im(s, dest);
789 883 tcg_gen_exit_tb(0);
790 884 }
791 885 s->is_jmp = DISAS_TB_JUMP;
... ... @@ -810,61 +904,60 @@ DISAS_INSN(undef)
810 904  
811 905 DISAS_INSN(mulw)
812 906 {
813   - int reg;
814   - int tmp;
815   - int src;
  907 + TCGv reg;
  908 + TCGv tmp;
  909 + TCGv src;
816 910 int sign;
817 911  
818 912 sign = (insn & 0x100) != 0;
819 913 reg = DREG(insn, 9);
820 914 tmp = gen_new_qreg(QMODE_I32);
821 915 if (sign)
822   - gen_op_ext16s32(tmp, reg);
  916 + tcg_gen_ext16s_i32(tmp, reg);
823 917 else
824   - gen_op_ext16u32(tmp, reg);
825   - SRC_EA(src, OS_WORD, sign ? -1 : 0, NULL);
826   - gen_op_mul32(tmp, tmp, src);
827   - gen_op_mov32(reg, tmp);
  918 + tcg_gen_ext16u_i32(tmp, reg);
  919 + SRC_EA(src, OS_WORD, sign, NULL);
  920 + tcg_gen_mul_i32(tmp, tmp, src);
  921 + tcg_gen_mov_i32(reg, tmp);
828 922 /* Unlike m68k, coldfire always clears the overflow bit. */
829 923 gen_logic_cc(s, tmp);
830 924 }
831 925  
832 926 DISAS_INSN(divw)
833 927 {
834   - int reg;
835   - int tmp;
836   - int src;
  928 + TCGv reg;
  929 + TCGv tmp;
  930 + TCGv src;
837 931 int sign;
838 932  
839 933 sign = (insn & 0x100) != 0;
840 934 reg = DREG(insn, 9);
841 935 if (sign) {
842   - gen_op_ext16s32(QREG_DIV1, reg);
  936 + tcg_gen_ext16s_i32(QREG_DIV1, reg);
843 937 } else {
844   - gen_op_ext16u32(QREG_DIV1, reg);
  938 + tcg_gen_ext16u_i32(QREG_DIV1, reg);
845 939 }
846   - SRC_EA(src, OS_WORD, sign ? -1 : 0, NULL);
847   - gen_op_mov32(QREG_DIV2, src);
  940 + SRC_EA(src, OS_WORD, sign, NULL);
  941 + tcg_gen_mov_i32(QREG_DIV2, src);
848 942 if (sign) {
849   - gen_op_divs(1);
  943 + gen_helper_divs(cpu_env, tcg_const_i32(1));
850 944 } else {
851   - gen_op_divu(1);
  945 + gen_helper_divu(cpu_env, tcg_const_i32(1));
852 946 }
853 947  
854 948 tmp = gen_new_qreg(QMODE_I32);
855 949 src = gen_new_qreg(QMODE_I32);
856   - gen_op_ext16u32(tmp, QREG_DIV1);
857   - gen_op_shl32(src, QREG_DIV2, gen_im32(16));
858   - gen_op_or32(reg, tmp, src);
859   - gen_op_flags_set();
  950 + tcg_gen_ext16u_i32(tmp, QREG_DIV1);
  951 + tcg_gen_shli_i32(src, QREG_DIV2, 16);
  952 + tcg_gen_or_i32(reg, tmp, src);
860 953 s->cc_op = CC_OP_FLAGS;
861 954 }
862 955  
863 956 DISAS_INSN(divl)
864 957 {
865   - int num;
866   - int den;
867   - int reg;
  958 + TCGv num;
  959 + TCGv den;
  960 + TCGv reg;
868 961 uint16_t ext;
869 962  
870 963 ext = lduw_code(s->pc);
... ... @@ -875,32 +968,31 @@ DISAS_INSN(divl)
875 968 }
876 969 num = DREG(ext, 12);
877 970 reg = DREG(ext, 0);
878   - gen_op_mov32(QREG_DIV1, num);
  971 + tcg_gen_mov_i32(QREG_DIV1, num);
879 972 SRC_EA(den, OS_LONG, 0, NULL);
880   - gen_op_mov32(QREG_DIV2, den);
  973 + tcg_gen_mov_i32(QREG_DIV2, den);
881 974 if (ext & 0x0800) {
882   - gen_op_divs(2);
  975 + gen_helper_divs(cpu_env, tcg_const_i32(0));
883 976 } else {
884   - gen_op_divu(2);
  977 + gen_helper_divu(cpu_env, tcg_const_i32(0));
885 978 }
886   - if (num == reg) {
  979 + if ((ext & 7) == ((ext >> 12) & 7)) {
887 980 /* div */
888   - gen_op_mov32 (reg, QREG_DIV1);
  981 + tcg_gen_mov_i32 (reg, QREG_DIV1);
889 982 } else {
890 983 /* rem */
891   - gen_op_mov32 (reg, QREG_DIV2);
  984 + tcg_gen_mov_i32 (reg, QREG_DIV2);
892 985 }
893   - gen_op_flags_set();
894 986 s->cc_op = CC_OP_FLAGS;
895 987 }
896 988  
897 989 DISAS_INSN(addsub)
898 990 {
899   - int reg;
900   - int dest;
901   - int src;
902   - int tmp;
903   - int addr;
  991 + TCGv reg;
  992 + TCGv dest;
  993 + TCGv src;
  994 + TCGv tmp;
  995 + TCGv addr;
904 996 int add;
905 997  
906 998 add = (insn & 0x4000) != 0;
... ... @@ -914,19 +1006,19 @@ DISAS_INSN(addsub)
914 1006 SRC_EA(src, OS_LONG, 0, NULL);
915 1007 }
916 1008 if (add) {
917   - gen_op_add32(dest, tmp, src);
918   - gen_op_update_xflag_lt(dest, src);
  1009 + tcg_gen_add_i32(dest, tmp, src);
  1010 + gen_helper_xflag_lt(QREG_CC_X, dest, src);
919 1011 s->cc_op = CC_OP_ADD;
920 1012 } else {
921   - gen_op_update_xflag_lt(tmp, src);
922   - gen_op_sub32(dest, tmp, src);
  1013 + gen_helper_xflag_lt(QREG_CC_X, tmp, src);
  1014 + tcg_gen_sub_i32(dest, tmp, src);
923 1015 s->cc_op = CC_OP_SUB;
924 1016 }
925   - gen_op_update_cc_add(dest, src);
  1017 + gen_update_cc_add(dest, src);
926 1018 if (insn & 0x100) {
927 1019 DEST_EA(insn, OS_LONG, dest, &addr);
928 1020 } else {
929   - gen_op_mov32(reg, dest);
  1021 + tcg_gen_mov_i32(reg, dest);
930 1022 }
931 1023 }
932 1024  
... ... @@ -934,48 +1026,20 @@ DISAS_INSN(addsub)
934 1026 /* Reverse the order of the bits in REG. */
935 1027 DISAS_INSN(bitrev)
936 1028 {
937   - int val;
938   - int tmp1;
939   - int tmp2;
940   - int reg;
941   -
942   - val = gen_new_qreg(QMODE_I32);
943   - tmp1 = gen_new_qreg(QMODE_I32);
944   - tmp2 = gen_new_qreg(QMODE_I32);
  1029 + TCGv reg;
945 1030 reg = DREG(insn, 0);
946   - gen_op_mov32(val, reg);
947   - /* Reverse bits within each nibble. */
948   - gen_op_shl32(tmp1, val, gen_im32(3));
949   - gen_op_and32(tmp1, tmp1, gen_im32(0x88888888));
950   - gen_op_shl32(tmp2, val, gen_im32(1));
951   - gen_op_and32(tmp2, tmp2, gen_im32(0x44444444));
952   - gen_op_or32(tmp1, tmp1, tmp2);
953   - gen_op_shr32(tmp2, val, gen_im32(1));
954   - gen_op_and32(tmp2, tmp2, gen_im32(0x22222222));
955   - gen_op_or32(tmp1, tmp1, tmp2);
956   - gen_op_shr32(tmp2, val, gen_im32(3));
957   - gen_op_and32(tmp2, tmp2, gen_im32(0x11111111));
958   - gen_op_or32(tmp1, tmp1, tmp2);
959   - /* Reverse nibbles withing bytes. */
960   - gen_op_shl32(val, tmp1, gen_im32(4));
961   - gen_op_and32(val, val, gen_im32(0xf0f0f0f0));
962   - gen_op_shr32(tmp2, tmp1, gen_im32(4));
963   - gen_op_and32(tmp2, tmp2, gen_im32(0x0f0f0f0f));
964   - gen_op_or32(val, val, tmp2);
965   - /* Reverse bytes. */
966   - gen_op_bswap32(reg, val);
967   - gen_op_mov32(reg, val);
  1031 + gen_helper_bitrev(reg, reg);
968 1032 }
969 1033  
970 1034 DISAS_INSN(bitop_reg)
971 1035 {
972 1036 int opsize;
973 1037 int op;
974   - int src1;
975   - int src2;
976   - int tmp;
977   - int addr;
978   - int dest;
  1038 + TCGv src1;
  1039 + TCGv src2;
  1040 + TCGv tmp;
  1041 + TCGv addr;
  1042 + TCGv dest;
979 1043  
980 1044 if ((insn & 0x38) != 0)
981 1045 opsize = OS_BYTE;
... ... @@ -989,24 +1053,29 @@ DISAS_INSN(bitop_reg)
989 1053 gen_flush_flags(s);
990 1054 tmp = gen_new_qreg(QMODE_I32);
991 1055 if (opsize == OS_BYTE)
992   - gen_op_and32(tmp, src2, gen_im32(7));
  1056 + tcg_gen_andi_i32(tmp, src2, 7);
993 1057 else
994   - gen_op_and32(tmp, src2, gen_im32(31));
  1058 + tcg_gen_andi_i32(tmp, src2, 31);
995 1059 src2 = tmp;
996 1060 tmp = gen_new_qreg(QMODE_I32);
997   - gen_op_shl32(tmp, gen_im32(1), src2);
998   -
999   - gen_op_btest(src1, tmp);
  1061 + tcg_gen_shr_i32(tmp, src1, src2);
  1062 + tcg_gen_andi_i32(tmp, tmp, 1);
  1063 + tcg_gen_shli_i32(tmp, tmp, 2);
  1064 + /* Clear CCF_Z if bit set. */
  1065 + tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
  1066 + tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
  1067 +
  1068 + tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);
1000 1069 switch (op) {
1001 1070 case 1: /* bchg */
1002   - gen_op_xor32(dest, src1, tmp);
  1071 + tcg_gen_xor_i32(dest, src1, tmp);
1003 1072 break;
1004 1073 case 2: /* bclr */
1005   - gen_op_not32(tmp, tmp);
1006   - gen_op_and32(dest, src1, tmp);
  1074 + tcg_gen_not_i32(tmp, tmp);
  1075 + tcg_gen_and_i32(dest, src1, tmp);
1007 1076 break;
1008 1077 case 3: /* bset */
1009   - gen_op_or32(dest, src1, tmp);
  1078 + tcg_gen_or_i32(dest, src1, tmp);
1010 1079 break;
1011 1080 default: /* btst */
1012 1081 break;
... ... @@ -1017,52 +1086,41 @@ DISAS_INSN(bitop_reg)
1017 1086  
1018 1087 DISAS_INSN(sats)
1019 1088 {
1020   - int reg;
1021   - int tmp;
1022   - int l1;
1023   -
  1089 + TCGv reg;
1024 1090 reg = DREG(insn, 0);
1025   - tmp = gen_new_qreg(QMODE_I32);
1026 1091 gen_flush_flags(s);
1027   - gen_op_and32(tmp, QREG_CC_DEST, gen_im32(CCF_V));
1028   - l1 = gen_new_label();
1029   - gen_op_jmp_z32(tmp, l1);
1030   - tmp = gen_new_qreg(QMODE_I32);
1031   - gen_op_shr32(tmp, reg, gen_im32(31));
1032   - gen_op_xor32(tmp, tmp, gen_im32(0x80000000));
1033   - gen_op_mov32(reg, tmp);
1034   - gen_set_label(l1);
1035   - gen_logic_cc(s, tmp);
  1092 + gen_helper_sats(reg, reg, QREG_CC_DEST);
  1093 + gen_logic_cc(s, reg);
1036 1094 }
1037 1095  
1038   -static void gen_push(DisasContext *s, int val)
  1096 +static void gen_push(DisasContext *s, TCGv val)
1039 1097 {
1040   - int tmp;
  1098 + TCGv tmp;
1041 1099  
1042 1100 tmp = gen_new_qreg(QMODE_I32);
1043   - gen_op_sub32(tmp, QREG_SP, gen_im32(4));
  1101 + tcg_gen_subi_i32(tmp, QREG_SP, 4);
1044 1102 gen_store(s, OS_LONG, tmp, val);
1045   - gen_op_mov32(QREG_SP, tmp);
  1103 + tcg_gen_mov_i32(QREG_SP, tmp);
1046 1104 }
1047 1105  
1048 1106 DISAS_INSN(movem)
1049 1107 {
1050   - int addr;
  1108 + TCGv addr;
1051 1109 int i;
1052 1110 uint16_t mask;
1053   - int reg;
1054   - int tmp;
  1111 + TCGv reg;
  1112 + TCGv tmp;
1055 1113 int is_load;
1056 1114  
1057 1115 mask = lduw_code(s->pc);
1058 1116 s->pc += 2;
1059 1117 tmp = gen_lea(s, insn, OS_LONG);
1060   - if (tmp == -1) {
  1118 + if (IS_NULL_QREG(tmp)) {
1061 1119 gen_addr_fault(s);
1062 1120 return;
1063 1121 }
1064 1122 addr = gen_new_qreg(QMODE_I32);
1065   - gen_op_mov32(addr, tmp);
  1123 + tcg_gen_mov_i32(addr, tmp);
1066 1124 is_load = ((insn & 0x0400) != 0);
1067 1125 for (i = 0; i < 16; i++, mask >>= 1) {
1068 1126 if (mask & 1) {
... ... @@ -1072,12 +1130,12 @@ DISAS_INSN(movem)
1072 1130 reg = AREG(i, 0);
1073 1131 if (is_load) {
1074 1132 tmp = gen_load(s, OS_LONG, addr, 0);
1075   - gen_op_mov32(reg, tmp);
  1133 + tcg_gen_mov_i32(reg, tmp);
1076 1134 } else {
1077 1135 gen_store(s, OS_LONG, addr, reg);
1078 1136 }
1079 1137 if (mask != 1)
1080   - gen_op_add32(addr, addr, gen_im32(4));
  1138 + tcg_gen_addi_i32(addr, addr, 4);
1081 1139 }
1082 1140 }
1083 1141 }
... ... @@ -1086,12 +1144,11 @@ DISAS_INSN(bitop_im)
1086 1144 {
1087 1145 int opsize;
1088 1146 int op;
1089   - int src1;
  1147 + TCGv src1;
1090 1148 uint32_t mask;
1091 1149 int bitnum;
1092   - int tmp;
1093   - int addr;
1094   - int dest;
  1150 + TCGv tmp;
  1151 + TCGv addr;
1095 1152  
1096 1153 if ((insn & 0x38) != 0)
1097 1154 opsize = OS_BYTE;
... ... @@ -1109,79 +1166,85 @@ DISAS_INSN(bitop_im)
1109 1166 SRC_EA(src1, opsize, 0, op ? &addr: NULL);
1110 1167  
1111 1168 gen_flush_flags(s);
1112   - tmp = gen_new_qreg(QMODE_I32);
1113 1169 if (opsize == OS_BYTE)
1114 1170 bitnum &= 7;
1115 1171 else
1116 1172 bitnum &= 31;
1117 1173 mask = 1 << bitnum;
1118 1174  
1119   - gen_op_btest(src1, gen_im32(mask));
1120   - if (op)
1121   - dest = gen_new_qreg(QMODE_I32);
  1175 + tmp = gen_new_qreg(QMODE_I32);
  1176 + assert (CCF_Z == (1 << 2));
  1177 + if (bitnum > 2)
  1178 + tcg_gen_shri_i32(tmp, src1, bitnum - 2);
  1179 + else if (bitnum < 2)
  1180 + tcg_gen_shli_i32(tmp, src1, 2 - bitnum);
1122 1181 else
1123   - dest = -1;
1124   -
1125   - switch (op) {
1126   - case 1: /* bchg */
1127   - gen_op_xor32(dest, src1, gen_im32(mask));
1128   - break;
1129   - case 2: /* bclr */
1130   - gen_op_and32(dest, src1, gen_im32(~mask));
1131   - break;
1132   - case 3: /* bset */
1133   - gen_op_or32(dest, src1, gen_im32(mask));
1134   - break;
1135   - default: /* btst */
1136   - break;
  1182 + tcg_gen_mov_i32(tmp, src1);
  1183 + tcg_gen_andi_i32(tmp, tmp, CCF_Z);
  1184 + /* Clear CCF_Z if bit set. */
  1185 + tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
  1186 + tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
  1187 + if (op) {
  1188 + switch (op) {
  1189 + case 1: /* bchg */
  1190 + tcg_gen_xori_i32(tmp, src1, mask);
  1191 + break;
  1192 + case 2: /* bclr */
  1193 + tcg_gen_andi_i32(tmp, src1, ~mask);
  1194 + break;
  1195 + case 3: /* bset */
  1196 + tcg_gen_ori_i32(tmp, src1, mask);
  1197 + break;
  1198 + default: /* btst */
  1199 + break;
  1200 + }
  1201 + DEST_EA(insn, opsize, tmp, &addr);
1137 1202 }
1138   - if (op)
1139   - DEST_EA(insn, opsize, dest, &addr);
1140 1203 }
1141 1204  
1142 1205 DISAS_INSN(arith_im)
1143 1206 {
1144 1207 int op;
1145   - int src1;
1146   - int dest;
1147   - int src2;
1148   - int addr;
  1208 + uint32_t im;
  1209 + TCGv src1;
  1210 + TCGv dest;
  1211 + TCGv addr;
1149 1212  
1150 1213 op = (insn >> 9) & 7;
1151 1214 SRC_EA(src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1152   - src2 = gen_im32(read_im32(s));
  1215 + im = read_im32(s);
1153 1216 dest = gen_new_qreg(QMODE_I32);
1154 1217 switch (op) {
1155 1218 case 0: /* ori */
1156   - gen_op_or32(dest, src1, src2);
  1219 + tcg_gen_ori_i32(dest, src1, im);
1157 1220 gen_logic_cc(s, dest);
1158 1221 break;
1159 1222 case 1: /* andi */
1160   - gen_op_and32(dest, src1, src2);
  1223 + tcg_gen_andi_i32(dest, src1, im);
1161 1224 gen_logic_cc(s, dest);
1162 1225 break;
1163 1226 case 2: /* subi */
1164   - gen_op_mov32(dest, src1);
1165   - gen_op_update_xflag_lt(dest, src2);
1166   - gen_op_sub32(dest, dest, src2);
1167   - gen_op_update_cc_add(dest, src2);
  1227 + tcg_gen_mov_i32(dest, src1);
  1228 + gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im));
  1229 + tcg_gen_subi_i32(dest, dest, im);
  1230 + gen_update_cc_add(dest, gen_im32(im));
1168 1231 s->cc_op = CC_OP_SUB;
1169 1232 break;
1170 1233 case 3: /* addi */
1171   - gen_op_mov32(dest, src1);
1172   - gen_op_add32(dest, dest, src2);
1173   - gen_op_update_cc_add(dest, src2);
1174   - gen_op_update_xflag_lt(dest, src2);
  1234 + tcg_gen_mov_i32(dest, src1);
  1235 + tcg_gen_addi_i32(dest, dest, im);
  1236 + gen_update_cc_add(dest, gen_im32(im));
  1237 + gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im));
1175 1238 s->cc_op = CC_OP_ADD;
1176 1239 break;
1177 1240 case 5: /* eori */
1178   - gen_op_xor32(dest, src1, src2);
  1241 + tcg_gen_xori_i32(dest, src1, im);
1179 1242 gen_logic_cc(s, dest);
1180 1243 break;
1181 1244 case 6: /* cmpi */
1182   - gen_op_mov32(dest, src1);
1183   - gen_op_sub32(dest, dest, src2);
1184   - gen_op_update_cc_add(dest, src2);
  1245 + tcg_gen_mov_i32(dest, src1);
  1246 + tcg_gen_subi_i32(dest, dest, im);
  1247 + gen_update_cc_add(dest, gen_im32(im));
1185 1248 s->cc_op = CC_OP_SUB;
1186 1249 break;
1187 1250 default:
... ... @@ -1194,16 +1257,16 @@ DISAS_INSN(arith_im)
1194 1257  
1195 1258 DISAS_INSN(byterev)
1196 1259 {
1197   - int reg;
  1260 + TCGv reg;
1198 1261  
1199 1262 reg = DREG(insn, 0);
1200   - gen_op_bswap32(reg, reg);
  1263 + tcg_gen_bswap_i32(reg, reg);
1201 1264 }
1202 1265  
1203 1266 DISAS_INSN(move)
1204 1267 {
1205   - int src;
1206   - int dest;
  1268 + TCGv src;
  1269 + TCGv dest;
1207 1270 int op;
1208 1271 int opsize;
1209 1272  
... ... @@ -1220,13 +1283,13 @@ DISAS_INSN(move)
1220 1283 default:
1221 1284 abort();
1222 1285 }
1223   - SRC_EA(src, opsize, -1, NULL);
  1286 + SRC_EA(src, opsize, 1, NULL);
1224 1287 op = (insn >> 6) & 7;
1225 1288 if (op == 1) {
1226 1289 /* movea */
1227 1290 /* The value will already have been sign extended. */
1228 1291 dest = AREG(insn, 9);
1229   - gen_op_mov32(dest, src);
  1292 + tcg_gen_mov_i32(dest, src);
1230 1293 } else {
1231 1294 /* normal move */
1232 1295 uint16_t dest_ea;
... ... @@ -1239,39 +1302,25 @@ DISAS_INSN(move)
1239 1302  
1240 1303 DISAS_INSN(negx)
1241 1304 {
1242   - int reg;
1243   - int dest;
1244   - int tmp;
  1305 + TCGv reg;
1245 1306  
1246 1307 gen_flush_flags(s);
1247 1308 reg = DREG(insn, 0);
1248   - dest = gen_new_qreg(QMODE_I32);
1249   - gen_op_mov32 (dest, gen_im32(0));
1250   - gen_op_subx_cc(dest, reg);
1251   - /* !Z is sticky. */
1252   - tmp = gen_new_qreg(QMODE_I32);
1253   - gen_op_mov32 (tmp, QREG_CC_DEST);
1254   - gen_op_update_cc_add(dest, reg);
1255   - gen_op_mov32(reg, dest);
1256   - s->cc_op = CC_OP_DYNAMIC;
1257   - gen_flush_flags(s);
1258   - gen_op_or32(tmp, tmp, gen_im32(~CCF_Z));
1259   - gen_op_and32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1260   - s->cc_op = CC_OP_FLAGS;
  1309 + gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1261 1310 }
1262 1311  
1263 1312 DISAS_INSN(lea)
1264 1313 {
1265   - int reg;
1266   - int tmp;
  1314 + TCGv reg;
  1315 + TCGv tmp;
1267 1316  
1268 1317 reg = AREG(insn, 9);
1269 1318 tmp = gen_lea(s, insn, OS_LONG);
1270   - if (tmp == -1) {
  1319 + if (IS_NULL_QREG(tmp)) {
1271 1320 gen_addr_fault(s);
1272 1321 return;
1273 1322 }
1274   - gen_op_mov32(reg, tmp);
  1323 + tcg_gen_mov_i32(reg, tmp);
1275 1324 }
1276 1325  
1277 1326 DISAS_INSN(clr)
... ... @@ -1295,22 +1344,21 @@ DISAS_INSN(clr)
1295 1344 gen_logic_cc(s, gen_im32(0));
1296 1345 }
1297 1346  
1298   -static int gen_get_ccr(DisasContext *s)
  1347 +static TCGv gen_get_ccr(DisasContext *s)
1299 1348 {
1300   - int dest;
  1349 + TCGv dest;
1301 1350  
1302 1351 gen_flush_flags(s);
1303 1352 dest = gen_new_qreg(QMODE_I32);
1304   - gen_op_get_xflag(dest);
1305   - gen_op_shl32(dest, dest, gen_im32(4));
1306   - gen_op_or32(dest, dest, QREG_CC_DEST);
  1353 + tcg_gen_shli_i32(dest, QREG_CC_X, 4);
  1354 + tcg_gen_or_i32(dest, dest, QREG_CC_DEST);
1307 1355 return dest;
1308 1356 }
1309 1357  
1310 1358 DISAS_INSN(move_from_ccr)
1311 1359 {
1312   - int reg;
1313   - int ccr;
  1360 + TCGv reg;
  1361 + TCGv ccr;
1314 1362  
1315 1363 ccr = gen_get_ccr(s);
1316 1364 reg = DREG(insn, 0);
... ... @@ -1319,45 +1367,43 @@ DISAS_INSN(move_from_ccr)
1319 1367  
1320 1368 DISAS_INSN(neg)
1321 1369 {
1322   - int reg;
1323   - int src1;
  1370 + TCGv reg;
  1371 + TCGv src1;
1324 1372  
1325 1373 reg = DREG(insn, 0);
1326 1374 src1 = gen_new_qreg(QMODE_I32);
1327   - gen_op_mov32(src1, reg);
1328   - gen_op_neg32(reg, src1);
  1375 + tcg_gen_mov_i32(src1, reg);
  1376 + tcg_gen_neg_i32(reg, src1);
1329 1377 s->cc_op = CC_OP_SUB;
1330   - gen_op_update_cc_add(reg, src1);
1331   - gen_op_update_xflag_lt(gen_im32(0), src1);
  1378 + gen_update_cc_add(reg, src1);
  1379 + gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
1332 1380 s->cc_op = CC_OP_SUB;
1333 1381 }
1334 1382  
1335 1383 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1336 1384 {
1337   - gen_op_logic_cc(gen_im32(val & 0xf));
1338   - gen_op_update_xflag_tst(gen_im32((val & 0x10) >> 4));
  1385 + tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf);
  1386 + tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4);
1339 1387 if (!ccr_only) {
1340   - gen_op_set_sr(gen_im32(val & 0xff00));
  1388 + gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
1341 1389 }
1342 1390 }
1343 1391  
1344 1392 static void gen_set_sr(DisasContext *s, uint16_t insn, int ccr_only)
1345 1393 {
1346   - int src1;
1347   - int reg;
  1394 + TCGv tmp;
  1395 + TCGv reg;
1348 1396  
1349 1397 s->cc_op = CC_OP_FLAGS;
1350 1398 if ((insn & 0x38) == 0)
1351 1399 {
1352   - src1 = gen_new_qreg(QMODE_I32);
  1400 + tmp = gen_new_qreg(QMODE_I32);
1353 1401 reg = DREG(insn, 0);
1354   - gen_op_and32(src1, reg, gen_im32(0xf));
1355   - gen_op_logic_cc(src1);
1356   - gen_op_shr32(src1, reg, gen_im32(4));
1357   - gen_op_and32(src1, src1, gen_im32(1));
1358   - gen_op_update_xflag_tst(src1);
  1402 + tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
  1403 + tcg_gen_shri_i32(tmp, reg, 4);
  1404 + tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
1359 1405 if (!ccr_only) {
1360   - gen_op_set_sr(reg);
  1406 + gen_helper_set_sr(cpu_env, reg);
1361 1407 }
1362 1408 }
1363 1409 else if ((insn & 0x3f) == 0x3c)
... ... @@ -1378,37 +1424,34 @@ DISAS_INSN(move_to_ccr)
1378 1424  
1379 1425 DISAS_INSN(not)
1380 1426 {
1381   - int reg;
  1427 + TCGv reg;
1382 1428  
1383 1429 reg = DREG(insn, 0);
1384   - gen_op_not32(reg, reg);
  1430 + tcg_gen_not_i32(reg, reg);
1385 1431 gen_logic_cc(s, reg);
1386 1432 }
1387 1433  
1388 1434 DISAS_INSN(swap)
1389 1435 {
1390   - int dest;
1391   - int src1;
1392   - int src2;
1393   - int reg;
  1436 + TCGv src1;
  1437 + TCGv src2;
  1438 + TCGv reg;
1394 1439  
1395   - dest = gen_new_qreg(QMODE_I32);
1396 1440 src1 = gen_new_qreg(QMODE_I32);
1397 1441 src2 = gen_new_qreg(QMODE_I32);
1398 1442 reg = DREG(insn, 0);
1399   - gen_op_shl32(src1, reg, gen_im32(16));
1400   - gen_op_shr32(src2, reg, gen_im32(16));
1401   - gen_op_or32(dest, src1, src2);
1402   - gen_op_mov32(reg, dest);
1403   - gen_logic_cc(s, dest);
  1443 + tcg_gen_shli_i32(src1, reg, 16);
  1444 + tcg_gen_shri_i32(src2, reg, 16);
  1445 + tcg_gen_or_i32(reg, src1, src2);
  1446 + gen_logic_cc(s, reg);
1404 1447 }
1405 1448  
1406 1449 DISAS_INSN(pea)
1407 1450 {
1408   - int tmp;
  1451 + TCGv tmp;
1409 1452  
1410 1453 tmp = gen_lea(s, insn, OS_LONG);
1411   - if (tmp == -1) {
  1454 + if (IS_NULL_QREG(tmp)) {
1412 1455 gen_addr_fault(s);
1413 1456 return;
1414 1457 }
... ... @@ -1417,28 +1460,28 @@ DISAS_INSN(pea)
1417 1460  
1418 1461 DISAS_INSN(ext)
1419 1462 {
1420   - int reg;
1421 1463 int op;
1422   - int tmp;
  1464 + TCGv reg;
  1465 + TCGv tmp;
1423 1466  
1424 1467 reg = DREG(insn, 0);
1425 1468 op = (insn >> 6) & 7;
1426 1469 tmp = gen_new_qreg(QMODE_I32);
1427 1470 if (op == 3)
1428   - gen_op_ext16s32(tmp, reg);
  1471 + tcg_gen_ext16s_i32(tmp, reg);
1429 1472 else
1430   - gen_op_ext8s32(tmp, reg);
  1473 + tcg_gen_ext8s_i32(tmp, reg);
1431 1474 if (op == 2)
1432 1475 gen_partset_reg(OS_WORD, reg, tmp);
1433 1476 else
1434   - gen_op_mov32(reg, tmp);
  1477 + tcg_gen_mov_i32(reg, tmp);
1435 1478 gen_logic_cc(s, tmp);
1436 1479 }
1437 1480  
1438 1481 DISAS_INSN(tst)
1439 1482 {
1440 1483 int opsize;
1441   - int tmp;
  1484 + TCGv tmp;
1442 1485  
1443 1486 switch ((insn >> 6) & 3) {
1444 1487 case 0: /* tst.b */
... ... @@ -1453,7 +1496,7 @@ DISAS_INSN(tst)
1453 1496 default:
1454 1497 abort();
1455 1498 }
1456   - SRC_EA(tmp, opsize, -1, NULL);
  1499 + SRC_EA(tmp, opsize, 1, NULL);
1457 1500 gen_logic_cc(s, tmp);
1458 1501 }
1459 1502  
... ... @@ -1470,23 +1513,23 @@ DISAS_INSN(illegal)
1470 1513 /* ??? This should be atomic. */
1471 1514 DISAS_INSN(tas)
1472 1515 {
1473   - int dest;
1474   - int src1;
1475   - int addr;
  1516 + TCGv dest;
  1517 + TCGv src1;
  1518 + TCGv addr;
1476 1519  
1477 1520 dest = gen_new_qreg(QMODE_I32);
1478   - SRC_EA(src1, OS_BYTE, -1, &addr);
  1521 + SRC_EA(src1, OS_BYTE, 1, &addr);
1479 1522 gen_logic_cc(s, src1);
1480   - gen_op_or32(dest, src1, gen_im32(0x80));
  1523 + tcg_gen_ori_i32(dest, src1, 0x80);
1481 1524 DEST_EA(insn, OS_BYTE, dest, &addr);
1482 1525 }
1483 1526  
1484 1527 DISAS_INSN(mull)
1485 1528 {
1486 1529 uint16_t ext;
1487   - int reg;
1488   - int src1;
1489   - int dest;
  1530 + TCGv reg;
  1531 + TCGv src1;
  1532 + TCGv dest;
1490 1533  
1491 1534 /* The upper 32 bits of the product are discarded, so
1492 1535 muls.l and mulu.l are functionally equivalent. */
... ... @@ -1499,8 +1542,8 @@ DISAS_INSN(mull)
1499 1542 reg = DREG(ext, 12);
1500 1543 SRC_EA(src1, OS_LONG, 0, NULL);
1501 1544 dest = gen_new_qreg(QMODE_I32);
1502   - gen_op_mul32(dest, src1, reg);
1503   - gen_op_mov32(reg, dest);
  1545 + tcg_gen_mul_i32(dest, src1, reg);
  1546 + tcg_gen_mov_i32(reg, dest);
1504 1547 /* Unlike m68k, coldfire always clears the overflow bit. */
1505 1548 gen_logic_cc(s, dest);
1506 1549 }
... ... @@ -1508,32 +1551,32 @@ DISAS_INSN(mull)
1508 1551 DISAS_INSN(link)
1509 1552 {
1510 1553 int16_t offset;
1511   - int reg;
1512   - int tmp;
  1554 + TCGv reg;
  1555 + TCGv tmp;
1513 1556  
1514 1557 offset = ldsw_code(s->pc);
1515 1558 s->pc += 2;
1516 1559 reg = AREG(insn, 0);
1517 1560 tmp = gen_new_qreg(QMODE_I32);
1518   - gen_op_sub32(tmp, QREG_SP, gen_im32(4));
  1561 + tcg_gen_subi_i32(tmp, QREG_SP, 4);
1519 1562 gen_store(s, OS_LONG, tmp, reg);
1520   - if (reg != QREG_SP)
1521   - gen_op_mov32(reg, tmp);
1522   - gen_op_add32(QREG_SP, tmp, gen_im32(offset));
  1563 + if ((insn & 7) != 7)
  1564 + tcg_gen_mov_i32(reg, tmp);
  1565 + tcg_gen_addi_i32(QREG_SP, tmp, offset);
1523 1566 }
1524 1567  
1525 1568 DISAS_INSN(unlk)
1526 1569 {
1527   - int src;
1528   - int reg;
1529   - int tmp;
  1570 + TCGv src;
  1571 + TCGv reg;
  1572 + TCGv tmp;
1530 1573  
1531 1574 src = gen_new_qreg(QMODE_I32);
1532 1575 reg = AREG(insn, 0);
1533   - gen_op_mov32(src, reg);
  1576 + tcg_gen_mov_i32(src, reg);
1534 1577 tmp = gen_load(s, OS_LONG, src, 0);
1535   - gen_op_mov32(reg, tmp);
1536   - gen_op_add32(QREG_SP, src, gen_im32(4));
  1578 + tcg_gen_mov_i32(reg, tmp);
  1579 + tcg_gen_addi_i32(QREG_SP, src, 4);
1537 1580 }
1538 1581  
1539 1582 DISAS_INSN(nop)
... ... @@ -1542,21 +1585,21 @@ DISAS_INSN(nop)
1542 1585  
1543 1586 DISAS_INSN(rts)
1544 1587 {
1545   - int tmp;
  1588 + TCGv tmp;
1546 1589  
1547 1590 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1548   - gen_op_add32(QREG_SP, QREG_SP, gen_im32(4));
  1591 + tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1549 1592 gen_jmp(s, tmp);
1550 1593 }
1551 1594  
1552 1595 DISAS_INSN(jump)
1553 1596 {
1554   - int tmp;
  1597 + TCGv tmp;
1555 1598  
1556 1599 /* Load the target address first to ensure correct exception
1557 1600 behavior. */
1558 1601 tmp = gen_lea(s, insn, OS_LONG);
1559   - if (tmp == -1) {
  1602 + if (IS_NULL_QREG(tmp)) {
1560 1603 gen_addr_fault(s);
1561 1604 return;
1562 1605 }
... ... @@ -1569,38 +1612,38 @@ DISAS_INSN(jump)
1569 1612  
1570 1613 DISAS_INSN(addsubq)
1571 1614 {
1572   - int src1;
1573   - int src2;
1574   - int dest;
  1615 + TCGv src1;
  1616 + TCGv src2;
  1617 + TCGv dest;
1575 1618 int val;
1576   - int addr;
  1619 + TCGv addr;
1577 1620  
1578 1621 SRC_EA(src1, OS_LONG, 0, &addr);
1579 1622 val = (insn >> 9) & 7;
1580 1623 if (val == 0)
1581 1624 val = 8;
1582   - src2 = gen_im32(val);
1583 1625 dest = gen_new_qreg(QMODE_I32);
1584   - gen_op_mov32(dest, src1);
  1626 + tcg_gen_mov_i32(dest, src1);
1585 1627 if ((insn & 0x38) == 0x08) {
1586 1628 /* Don't update condition codes if the destination is an
1587 1629 address register. */
1588 1630 if (insn & 0x0100) {
1589   - gen_op_sub32(dest, dest, src2);
  1631 + tcg_gen_subi_i32(dest, dest, val);
1590 1632 } else {
1591   - gen_op_add32(dest, dest, src2);
  1633 + tcg_gen_addi_i32(dest, dest, val);
1592 1634 }
1593 1635 } else {
  1636 + src2 = gen_im32(val);
1594 1637 if (insn & 0x0100) {
1595   - gen_op_update_xflag_lt(dest, src2);
1596   - gen_op_sub32(dest, dest, src2);
  1638 + gen_helper_xflag_lt(QREG_CC_X, dest, src2);
  1639 + tcg_gen_subi_i32(dest, dest, val);
1597 1640 s->cc_op = CC_OP_SUB;
1598 1641 } else {
1599   - gen_op_add32(dest, dest, src2);
1600   - gen_op_update_xflag_lt(dest, src2);
  1642 + tcg_gen_addi_i32(dest, dest, val);
  1643 + gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1601 1644 s->cc_op = CC_OP_ADD;
1602 1645 }
1603   - gen_op_update_cc_add(dest, src2);
  1646 + gen_update_cc_add(dest, src2);
1604 1647 }
1605 1648 DEST_EA(insn, OS_LONG, dest, &addr);
1606 1649 }
... ... @@ -1657,88 +1700,74 @@ DISAS_INSN(branch)
1657 1700  
1658 1701 DISAS_INSN(moveq)
1659 1702 {
1660   - int tmp;
  1703 + uint32_t val;
1661 1704  
1662   - tmp = gen_im32((int8_t)insn);
1663   - gen_op_mov32(DREG(insn, 9), tmp);
1664   - gen_logic_cc(s, tmp);
  1705 + val = (int8_t)insn;
  1706 + tcg_gen_movi_i32(DREG(insn, 9), val);
  1707 + gen_logic_cc(s, tcg_const_i32(val));
1665 1708 }
1666 1709  
1667 1710 DISAS_INSN(mvzs)
1668 1711 {
1669 1712 int opsize;
1670   - int src;
1671   - int reg;
  1713 + TCGv src;
  1714 + TCGv reg;
1672 1715  
1673 1716 if (insn & 0x40)
1674 1717 opsize = OS_WORD;
1675 1718 else
1676 1719 opsize = OS_BYTE;
1677   - SRC_EA(src, opsize, (insn & 0x80) ? 0 : -1, NULL);
  1720 + SRC_EA(src, opsize, (insn & 0x80) != 0, NULL);
1678 1721 reg = DREG(insn, 9);
1679   - gen_op_mov32(reg, src);
  1722 + tcg_gen_mov_i32(reg, src);
1680 1723 gen_logic_cc(s, src);
1681 1724 }
1682 1725  
1683 1726 DISAS_INSN(or)
1684 1727 {
1685   - int reg;
1686   - int dest;
1687   - int src;
1688   - int addr;
  1728 + TCGv reg;
  1729 + TCGv dest;
  1730 + TCGv src;
  1731 + TCGv addr;
1689 1732  
1690 1733 reg = DREG(insn, 9);
1691 1734 dest = gen_new_qreg(QMODE_I32);
1692 1735 if (insn & 0x100) {
1693 1736 SRC_EA(src, OS_LONG, 0, &addr);
1694   - gen_op_or32(dest, src, reg);
  1737 + tcg_gen_or_i32(dest, src, reg);
1695 1738 DEST_EA(insn, OS_LONG, dest, &addr);
1696 1739 } else {
1697 1740 SRC_EA(src, OS_LONG, 0, NULL);
1698   - gen_op_or32(dest, src, reg);
1699   - gen_op_mov32(reg, dest);
  1741 + tcg_gen_or_i32(dest, src, reg);
  1742 + tcg_gen_mov_i32(reg, dest);
1700 1743 }
1701 1744 gen_logic_cc(s, dest);
1702 1745 }
1703 1746  
1704 1747 DISAS_INSN(suba)
1705 1748 {
1706   - int src;
1707   - int reg;
  1749 + TCGv src;
  1750 + TCGv reg;
1708 1751  
1709 1752 SRC_EA(src, OS_LONG, 0, NULL);
1710 1753 reg = AREG(insn, 9);
1711   - gen_op_sub32(reg, reg, src);
  1754 + tcg_gen_sub_i32(reg, reg, src);
1712 1755 }
1713 1756  
1714 1757 DISAS_INSN(subx)
1715 1758 {
1716   - int reg;
1717   - int src;
1718   - int dest;
1719   - int tmp;
  1759 + TCGv reg;
  1760 + TCGv src;
1720 1761  
1721 1762 gen_flush_flags(s);
1722 1763 reg = DREG(insn, 9);
1723 1764 src = DREG(insn, 0);
1724   - dest = gen_new_qreg(QMODE_I32);
1725   - gen_op_mov32 (dest, reg);
1726   - gen_op_subx_cc(dest, src);
1727   - /* !Z is sticky. */
1728   - tmp = gen_new_qreg(QMODE_I32);
1729   - gen_op_mov32 (tmp, QREG_CC_DEST);
1730   - gen_op_update_cc_add(dest, src);
1731   - gen_op_mov32(reg, dest);
1732   - s->cc_op = CC_OP_DYNAMIC;
1733   - gen_flush_flags(s);
1734   - gen_op_or32(tmp, tmp, gen_im32(~CCF_Z));
1735   - gen_op_and32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1736   - s->cc_op = CC_OP_FLAGS;
  1765 + gen_helper_subx_cc(reg, cpu_env, reg, src);
1737 1766 }
1738 1767  
1739 1768 DISAS_INSN(mov3q)
1740 1769 {
1741   - int src;
  1770 + TCGv src;
1742 1771 int val;
1743 1772  
1744 1773 val = (insn >> 9) & 7;
... ... @@ -1752,9 +1781,9 @@ DISAS_INSN(mov3q)
1752 1781 DISAS_INSN(cmp)
1753 1782 {
1754 1783 int op;
1755   - int src;
1756   - int reg;
1757   - int dest;
  1784 + TCGv src;
  1785 + TCGv reg;
  1786 + TCGv dest;
1758 1787 int opsize;
1759 1788  
1760 1789 op = (insn >> 6) & 3;
... ... @@ -1774,168 +1803,154 @@ DISAS_INSN(cmp)
1774 1803 default:
1775 1804 abort();
1776 1805 }
1777   - SRC_EA(src, opsize, -1, NULL);
  1806 + SRC_EA(src, opsize, 1, NULL);
1778 1807 reg = DREG(insn, 9);
1779 1808 dest = gen_new_qreg(QMODE_I32);
1780   - gen_op_sub32(dest, reg, src);
1781   - gen_op_update_cc_add(dest, src);
  1809 + tcg_gen_sub_i32(dest, reg, src);
  1810 + gen_update_cc_add(dest, src);
1782 1811 }
1783 1812  
1784 1813 DISAS_INSN(cmpa)
1785 1814 {
1786 1815 int opsize;
1787   - int src;
1788   - int reg;
1789   - int dest;
  1816 + TCGv src;
  1817 + TCGv reg;
  1818 + TCGv dest;
1790 1819  
1791 1820 if (insn & 0x100) {
1792 1821 opsize = OS_LONG;
1793 1822 } else {
1794 1823 opsize = OS_WORD;
1795 1824 }
1796   - SRC_EA(src, opsize, -1, NULL);
  1825 + SRC_EA(src, opsize, 1, NULL);
1797 1826 reg = AREG(insn, 9);
1798 1827 dest = gen_new_qreg(QMODE_I32);
1799   - gen_op_sub32(dest, reg, src);
1800   - gen_op_update_cc_add(dest, src);
  1828 + tcg_gen_sub_i32(dest, reg, src);
  1829 + gen_update_cc_add(dest, src);
1801 1830 s->cc_op = CC_OP_SUB;
1802 1831 }
1803 1832  
1804 1833 DISAS_INSN(eor)
1805 1834 {
1806   - int src;
1807   - int reg;
1808   - int dest;
1809   - int addr;
  1835 + TCGv src;
  1836 + TCGv reg;
  1837 + TCGv dest;
  1838 + TCGv addr;
1810 1839  
1811 1840 SRC_EA(src, OS_LONG, 0, &addr);
1812 1841 reg = DREG(insn, 9);
1813 1842 dest = gen_new_qreg(QMODE_I32);
1814   - gen_op_xor32(dest, src, reg);
  1843 + tcg_gen_xor_i32(dest, src, reg);
1815 1844 gen_logic_cc(s, dest);
1816 1845 DEST_EA(insn, OS_LONG, dest, &addr);
1817 1846 }
1818 1847  
1819 1848 DISAS_INSN(and)
1820 1849 {
1821   - int src;
1822   - int reg;
1823   - int dest;
1824   - int addr;
  1850 + TCGv src;
  1851 + TCGv reg;
  1852 + TCGv dest;
  1853 + TCGv addr;
1825 1854  
1826 1855 reg = DREG(insn, 9);
1827 1856 dest = gen_new_qreg(QMODE_I32);
1828 1857 if (insn & 0x100) {
1829 1858 SRC_EA(src, OS_LONG, 0, &addr);
1830   - gen_op_and32(dest, src, reg);
  1859 + tcg_gen_and_i32(dest, src, reg);
1831 1860 DEST_EA(insn, OS_LONG, dest, &addr);
1832 1861 } else {
1833 1862 SRC_EA(src, OS_LONG, 0, NULL);
1834   - gen_op_and32(dest, src, reg);
1835   - gen_op_mov32(reg, dest);
  1863 + tcg_gen_and_i32(dest, src, reg);
  1864 + tcg_gen_mov_i32(reg, dest);
1836 1865 }
1837 1866 gen_logic_cc(s, dest);
1838 1867 }
1839 1868  
1840 1869 DISAS_INSN(adda)
1841 1870 {
1842   - int src;
1843   - int reg;
  1871 + TCGv src;
  1872 + TCGv reg;
1844 1873  
1845 1874 SRC_EA(src, OS_LONG, 0, NULL);
1846 1875 reg = AREG(insn, 9);
1847   - gen_op_add32(reg, reg, src);
  1876 + tcg_gen_add_i32(reg, reg, src);
1848 1877 }
1849 1878  
1850 1879 DISAS_INSN(addx)
1851 1880 {
1852   - int reg;
1853   - int src;
1854   - int dest;
1855   - int tmp;
  1881 + TCGv reg;
  1882 + TCGv src;
1856 1883  
1857 1884 gen_flush_flags(s);
1858 1885 reg = DREG(insn, 9);
1859 1886 src = DREG(insn, 0);
1860   - dest = gen_new_qreg(QMODE_I32);
1861   - gen_op_mov32 (dest, reg);
1862   - gen_op_addx_cc(dest, src);
1863   - /* !Z is sticky. */
1864   - tmp = gen_new_qreg(QMODE_I32);
1865   - gen_op_mov32 (tmp, QREG_CC_DEST);
1866   - gen_op_update_cc_add(dest, src);
1867   - gen_op_mov32(reg, dest);
1868   - s->cc_op = CC_OP_DYNAMIC;
1869   - gen_flush_flags(s);
1870   - gen_op_or32(tmp, tmp, gen_im32(~CCF_Z));
1871   - gen_op_and32(QREG_CC_DEST, QREG_CC_DEST, tmp);
  1887 + gen_helper_addx_cc(reg, cpu_env, reg, src);
1872 1888 s->cc_op = CC_OP_FLAGS;
1873 1889 }
1874 1890  
  1891 +/* TODO: This could be implemented without helper functions. */
1875 1892 DISAS_INSN(shift_im)
1876 1893 {
1877   - int reg;
  1894 + TCGv reg;
1878 1895 int tmp;
  1896 + TCGv shift;
1879 1897  
1880 1898 reg = DREG(insn, 0);
1881 1899 tmp = (insn >> 9) & 7;
1882 1900 if (tmp == 0)
1883   - tmp = 8;
  1901 + tmp = 8;
  1902 + shift = gen_im32(tmp);
  1903 + /* No need to flush flags becuse we know we will set C flag. */
1884 1904 if (insn & 0x100) {
1885   - gen_op_shl_im_cc(reg, tmp);
1886   - s->cc_op = CC_OP_SHL;
  1905 + gen_helper_shl_cc(reg, cpu_env, reg, shift);
1887 1906 } else {
1888 1907 if (insn & 8) {
1889   - gen_op_shr_im_cc(reg, tmp);
1890   - s->cc_op = CC_OP_SHR;
  1908 + gen_helper_shr_cc(reg, cpu_env, reg, shift);
1891 1909 } else {
1892   - gen_op_sar_im_cc(reg, tmp);
1893   - s->cc_op = CC_OP_SAR;
  1910 + gen_helper_sar_cc(reg, cpu_env, reg, shift);
1894 1911 }
1895 1912 }
  1913 + s->cc_op = CC_OP_SHIFT;
1896 1914 }
1897 1915  
1898 1916 DISAS_INSN(shift_reg)
1899 1917 {
1900   - int reg;
1901   - int src;
1902   - int tmp;
  1918 + TCGv reg;
  1919 + TCGv shift;
1903 1920  
1904 1921 reg = DREG(insn, 0);
1905   - src = DREG(insn, 9);
1906   - tmp = gen_new_qreg(QMODE_I32);
1907   - gen_op_and32(tmp, src, gen_im32(63));
  1922 + shift = DREG(insn, 9);
  1923 + /* Shift by zero leaves C flag unmodified. */
  1924 + gen_flush_flags(s);
1908 1925 if (insn & 0x100) {
1909   - gen_op_shl_cc(reg, tmp);
1910   - s->cc_op = CC_OP_SHL;
  1926 + gen_helper_shl_cc(reg, cpu_env, reg, shift);
1911 1927 } else {
1912 1928 if (insn & 8) {
1913   - gen_op_shr_cc(reg, tmp);
1914   - s->cc_op = CC_OP_SHR;
  1929 + gen_helper_shr_cc(reg, cpu_env, reg, shift);
1915 1930 } else {
1916   - gen_op_sar_cc(reg, tmp);
1917   - s->cc_op = CC_OP_SAR;
  1931 + gen_helper_sar_cc(reg, cpu_env, reg, shift);
1918 1932 }
1919 1933 }
  1934 + s->cc_op = CC_OP_SHIFT;
1920 1935 }
1921 1936  
1922 1937 DISAS_INSN(ff1)
1923 1938 {
1924   - int reg;
  1939 + TCGv reg;
1925 1940 reg = DREG(insn, 0);
1926 1941 gen_logic_cc(s, reg);
1927   - gen_op_ff1(reg, reg);
  1942 + gen_helper_ff1(reg, reg);
1928 1943 }
1929 1944  
1930   -static int gen_get_sr(DisasContext *s)
  1945 +static TCGv gen_get_sr(DisasContext *s)
1931 1946 {
1932   - int ccr;
1933   - int sr;
  1947 + TCGv ccr;
  1948 + TCGv sr;
1934 1949  
1935 1950 ccr = gen_get_ccr(s);
1936 1951 sr = gen_new_qreg(QMODE_I32);
1937   - gen_op_and32(sr, QREG_SR, gen_im32(0xffe0));
1938   - gen_op_or32(sr, sr, ccr);
  1952 + tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
  1953 + tcg_gen_or_i32(sr, sr, ccr);
1939 1954 return sr;
1940 1955 }
1941 1956  
... ... @@ -1963,8 +1978,8 @@ DISAS_INSN(strldsr)
1963 1978  
1964 1979 DISAS_INSN(move_from_sr)
1965 1980 {
1966   - int reg;
1967   - int sr;
  1981 + TCGv reg;
  1982 + TCGv sr;
1968 1983  
1969 1984 if (IS_USER(s)) {
1970 1985 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
... ... @@ -2007,8 +2022,7 @@ DISAS_INSN(move_to_usp)
2007 2022  
2008 2023 DISAS_INSN(halt)
2009 2024 {
2010   - gen_jmp(s, gen_im32(s->pc));
2011   - gen_op_halt();
  2025 + gen_exception(s, s->pc, EXCP_HALT_INSN);
2012 2026 }
2013 2027  
2014 2028 DISAS_INSN(stop)
... ... @@ -2024,8 +2038,8 @@ DISAS_INSN(stop)
2024 2038 s->pc += 2;
2025 2039  
2026 2040 gen_set_sr_im(s, ext, 0);
2027   - gen_jmp(s, gen_im32(s->pc));
2028   - gen_op_stop();
  2041 + tcg_gen_movi_i32(QREG_HALTED, 1);
  2042 + gen_exception(s, s->pc, EXCP_HLT);
2029 2043 }
2030 2044  
2031 2045 DISAS_INSN(rte)
... ... @@ -2040,7 +2054,7 @@ DISAS_INSN(rte)
2040 2054 DISAS_INSN(movec)
2041 2055 {
2042 2056 uint16_t ext;
2043   - int reg;
  2057 + TCGv reg;
2044 2058  
2045 2059 if (IS_USER(s)) {
2046 2060 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
... ... @@ -2055,7 +2069,7 @@ DISAS_INSN(movec)
2055 2069 } else {
2056 2070 reg = DREG(ext, 12);
2057 2071 }
2058   - gen_op_movec(gen_im32(ext & 0xfff), reg);
  2072 + gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2059 2073 gen_lookup_tb(s);
2060 2074 }
2061 2075  
... ... @@ -2103,9 +2117,9 @@ DISAS_INSN(fpu)
2103 2117 {
2104 2118 uint16_t ext;
2105 2119 int opmode;
2106   - int src;
2107   - int dest;
2108   - int res;
  2120 + TCGv src;
  2121 + TCGv dest;
  2122 + TCGv res;
2109 2123 int round;
2110 2124 int opsize;
2111 2125  
... ... @@ -2125,17 +2139,17 @@ DISAS_INSN(fpu)
2125 2139 case 0:
2126 2140 opsize = OS_LONG;
2127 2141 res = gen_new_qreg(QMODE_I32);
2128   - gen_op_f64_to_i32(res, src);
  2142 + gen_helper_f64_to_i32(res, cpu_env, src);
2129 2143 break;
2130 2144 case 1:
2131 2145 opsize = OS_SINGLE;
2132 2146 res = gen_new_qreg(QMODE_F32);
2133   - gen_op_f64_to_f32(res, src);
  2147 + gen_helper_f64_to_f32(res, cpu_env, src);
2134 2148 break;
2135 2149 case 4:
2136 2150 opsize = OS_WORD;
2137 2151 res = gen_new_qreg(QMODE_I32);
2138   - gen_op_f64_to_i32(res, src);
  2152 + gen_helper_f64_to_i32(res, cpu_env, src);
2139 2153 break;
2140 2154 case 5:
2141 2155 opsize = OS_DOUBLE;
... ... @@ -2144,7 +2158,7 @@ DISAS_INSN(fpu)
2144 2158 case 6:
2145 2159 opsize = OS_BYTE;
2146 2160 res = gen_new_qreg(QMODE_I32);
2147   - gen_op_f64_to_i32(res, src);
  2161 + gen_helper_f64_to_i32(res, cpu_env, src);
2148 2162 break;
2149 2163 default:
2150 2164 goto undef;
... ... @@ -2181,40 +2195,40 @@ DISAS_INSN(fpu)
2181 2195 case 6: /* fmovem */
2182 2196 case 7:
2183 2197 {
2184   - int addr;
2185   - uint16_t mask;
2186   - if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2187   - goto undef;
2188   - src = gen_lea(s, insn, OS_LONG);
2189   - if (src == -1) {
2190   - gen_addr_fault(s);
2191   - return;
2192   - }
2193   - addr = gen_new_qreg(QMODE_I32);
2194   - gen_op_mov32(addr, src);
2195   - mask = 0x80;
2196   - dest = QREG_F0;
2197   - while (mask) {
2198   - if (ext & mask) {
2199   - s->is_mem = 1;
2200   - if (ext & (1 << 13)) {
2201   - /* store */
2202   - gen_st(s, f64, addr, dest);
2203   - } else {
2204   - /* load */
2205   - gen_ld(s, f64, dest, addr);
  2198 + TCGv addr;
  2199 + uint16_t mask;
  2200 + int i;
  2201 + if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
  2202 + goto undef;
  2203 + src = gen_lea(s, insn, OS_LONG);
  2204 + if (IS_NULL_QREG(src)) {
  2205 + gen_addr_fault(s);
  2206 + return;
  2207 + }
  2208 + addr = gen_new_qreg(QMODE_I32);
  2209 + tcg_gen_mov_i32(addr, src);
  2210 + mask = 0x80;
  2211 + for (i = 0; i < 8; i++) {
  2212 + if (ext & mask) {
  2213 + s->is_mem = 1;
  2214 + dest = FREG(i, 0);
  2215 + if (ext & (1 << 13)) {
  2216 + /* store */
  2217 + tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
  2218 + } else {
  2219 + /* load */
  2220 + tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
  2221 + }
  2222 + if (ext & (mask - 1))
  2223 + tcg_gen_addi_i32(addr, addr, 8);
2206 2224 }
2207   - if (ext & (mask - 1))
2208   - gen_op_add32(addr, addr, gen_im32(8));
  2225 + mask >>= 1;
2209 2226 }
2210   - mask >>= 1;
2211   - dest++;
2212   - }
2213 2227 }
2214 2228 return;
2215 2229 }
2216 2230 if (ext & (1 << 14)) {
2217   - int tmp;
  2231 + TCGv tmp;
2218 2232  
2219 2233 /* Source effective address. */
2220 2234 switch ((ext >> 10) & 7) {
... ... @@ -2226,7 +2240,7 @@ DISAS_INSN(fpu)
2226 2240 default:
2227 2241 goto undef;
2228 2242 }
2229   - SRC_EA(tmp, opsize, -1, NULL);
  2243 + SRC_EA(tmp, opsize, 1, NULL);
2230 2244 if (opsize == OS_DOUBLE) {
2231 2245 src = tmp;
2232 2246 } else {
... ... @@ -2235,10 +2249,10 @@ DISAS_INSN(fpu)
2235 2249 case OS_LONG:
2236 2250 case OS_WORD:
2237 2251 case OS_BYTE:
2238   - gen_op_i32_to_f64(src, tmp);
  2252 + gen_helper_i32_to_f64(src, cpu_env, tmp);
2239 2253 break;
2240 2254 case OS_SINGLE:
2241   - gen_op_f32_to_f64(src, tmp);
  2255 + gen_helper_f32_to_f64(src, cpu_env, tmp);
2242 2256 break;
2243 2257 }
2244 2258 }
... ... @@ -2249,49 +2263,49 @@ DISAS_INSN(fpu)
2249 2263 dest = FREG(ext, 7);
2250 2264 res = gen_new_qreg(QMODE_F64);
2251 2265 if (opmode != 0x3a)
2252   - gen_op_movf64(res, dest);
  2266 + tcg_gen_mov_f64(res, dest);
2253 2267 round = 1;
2254 2268 switch (opmode) {
2255 2269 case 0: case 0x40: case 0x44: /* fmove */
2256   - gen_op_movf64(res, src);
  2270 + tcg_gen_mov_f64(res, src);
2257 2271 break;
2258 2272 case 1: /* fint */
2259   - gen_op_iround_f64(res, src);
  2273 + gen_helper_iround_f64(res, cpu_env, src);
2260 2274 round = 0;
2261 2275 break;
2262 2276 case 3: /* fintrz */
2263   - gen_op_itrunc_f64(res, src);
  2277 + gen_helper_itrunc_f64(res, cpu_env, src);
2264 2278 round = 0;
2265 2279 break;
2266 2280 case 4: case 0x41: case 0x45: /* fsqrt */
2267   - gen_op_sqrtf64(res, src);
  2281 + gen_helper_sqrt_f64(res, cpu_env, src);
2268 2282 break;
2269 2283 case 0x18: case 0x58: case 0x5c: /* fabs */
2270   - gen_op_absf64(res, src);
  2284 + gen_helper_abs_f64(res, src);
2271 2285 break;
2272 2286 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2273   - gen_op_chsf64(res, src);
  2287 + gen_helper_chs_f64(res, src);
2274 2288 break;
2275 2289 case 0x20: case 0x60: case 0x64: /* fdiv */
2276   - gen_op_divf64(res, res, src);
  2290 + gen_helper_div_f64(res, cpu_env, res, src);
2277 2291 break;
2278 2292 case 0x22: case 0x62: case 0x66: /* fadd */
2279   - gen_op_addf64(res, res, src);
  2293 + gen_helper_add_f64(res, cpu_env, res, src);
2280 2294 break;
2281 2295 case 0x23: case 0x63: case 0x67: /* fmul */
2282   - gen_op_mulf64(res, res, src);
  2296 + gen_helper_mul_f64(res, cpu_env, res, src);
2283 2297 break;
2284 2298 case 0x28: case 0x68: case 0x6c: /* fsub */
2285   - gen_op_subf64(res, res, src);
  2299 + gen_helper_sub_f64(res, cpu_env, res, src);
2286 2300 break;
2287 2301 case 0x38: /* fcmp */
2288   - gen_op_sub_cmpf64(res, res, src);
2289   - dest = 0;
  2302 + gen_helper_sub_cmp_f64(res, cpu_env, res, src);
  2303 + dest = NULL_QREG;
2290 2304 round = 0;
2291 2305 break;
2292 2306 case 0x3a: /* ftst */
2293   - gen_op_movf64(res, src);
2294   - dest = 0;
  2307 + tcg_gen_mov_f64(res, src);
  2308 + dest = NULL_QREG;
2295 2309 round = 0;
2296 2310 break;
2297 2311 default:
... ... @@ -2306,15 +2320,15 @@ DISAS_INSN(fpu)
2306 2320 }
2307 2321 }
2308 2322 if (round) {
2309   - int tmp;
  2323 + TCGv tmp;
2310 2324  
2311 2325 tmp = gen_new_qreg(QMODE_F32);
2312   - gen_op_f64_to_f32(tmp, res);
2313   - gen_op_f32_to_f64(res, tmp);
  2326 + gen_helper_f64_to_f32(tmp, cpu_env, res);
  2327 + gen_helper_f32_to_f64(res, cpu_env, tmp);
2314 2328 }
2315   - gen_op_fp_result(res);
2316   - if (dest) {
2317   - gen_op_movf64(dest, res);
  2329 + tcg_gen_mov_f64(QREG_FP_RESULT, res);
  2330 + if (!IS_NULL_QREG(dest)) {
  2331 + tcg_gen_mov_f64(dest, res);
2318 2332 }
2319 2333 return;
2320 2334 undef:
... ... @@ -2326,8 +2340,7 @@ DISAS_INSN(fbcc)
2326 2340 {
2327 2341 uint32_t offset;
2328 2342 uint32_t addr;
2329   - int flag;
2330   - int zero;
  2343 + TCGv flag;
2331 2344 int l1;
2332 2345  
2333 2346 addr = s->pc;
... ... @@ -2341,72 +2354,57 @@ DISAS_INSN(fbcc)
2341 2354 l1 = gen_new_label();
2342 2355 /* TODO: Raise BSUN exception. */
2343 2356 flag = gen_new_qreg(QMODE_I32);
2344   - zero = gen_new_qreg(QMODE_F64);
2345   - gen_op_zerof64(zero);
2346   - gen_op_compare_quietf64(flag, QREG_FP_RESULT, zero);
  2357 + gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2347 2358 /* Jump to l1 if condition is true. */
2348 2359 switch (insn & 0xf) {
2349 2360 case 0: /* f */
2350 2361 break;
2351 2362 case 1: /* eq (=0) */
2352   - gen_op_jmp_z32(flag, l1);
  2363 + tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2353 2364 break;
2354 2365 case 2: /* ogt (=1) */
2355   - gen_op_sub32(flag, flag, gen_im32(1));
2356   - gen_op_jmp_z32(flag, l1);
  2366 + tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2357 2367 break;
2358 2368 case 3: /* oge (=0 or =1) */
2359   - gen_op_jmp_z32(flag, l1);
2360   - gen_op_sub32(flag, flag, gen_im32(1));
2361   - gen_op_jmp_z32(flag, l1);
  2369 + tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2362 2370 break;
2363 2371 case 4: /* olt (=-1) */
2364   - gen_op_jmp_s32(flag, l1);
  2372 + tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2365 2373 break;
2366 2374 case 5: /* ole (=-1 or =0) */
2367   - gen_op_jmp_s32(flag, l1);
2368   - gen_op_jmp_z32(flag, l1);
  2375 + tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2369 2376 break;
2370 2377 case 6: /* ogl (=-1 or =1) */
2371   - gen_op_jmp_s32(flag, l1);
2372   - gen_op_sub32(flag, flag, gen_im32(1));
2373   - gen_op_jmp_z32(flag, l1);
  2378 + tcg_gen_andi_i32(flag, flag, 1);
  2379 + tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2374 2380 break;
2375 2381 case 7: /* or (=2) */
2376   - gen_op_sub32(flag, flag, gen_im32(2));
2377   - gen_op_jmp_z32(flag, l1);
  2382 + tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2378 2383 break;
2379 2384 case 8: /* un (<2) */
2380   - gen_op_sub32(flag, flag, gen_im32(2));
2381   - gen_op_jmp_s32(flag, l1);
  2385 + tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2382 2386 break;
2383 2387 case 9: /* ueq (=0 or =2) */
2384   - gen_op_jmp_z32(flag, l1);
2385   - gen_op_sub32(flag, flag, gen_im32(2));
2386   - gen_op_jmp_z32(flag, l1);
  2388 + tcg_gen_andi_i32(flag, flag, 1);
  2389 + tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2387 2390 break;
2388 2391 case 10: /* ugt (>0) */
2389   - /* ??? Add jmp_gtu. */
2390   - gen_op_sub32(flag, flag, gen_im32(1));
2391   - gen_op_jmp_ns32(flag, l1);
  2392 + tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2392 2393 break;
2393 2394 case 11: /* uge (>=0) */
2394   - gen_op_jmp_ns32(flag, l1);
  2395 + tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2395 2396 break;
2396 2397 case 12: /* ult (=-1 or =2) */
2397   - gen_op_jmp_s32(flag, l1);
2398   - gen_op_sub32(flag, flag, gen_im32(2));
2399   - gen_op_jmp_z32(flag, l1);
  2398 + tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2400 2399 break;
2401 2400 case 13: /* ule (!=1) */
2402   - gen_op_sub32(flag, flag, gen_im32(1));
2403   - gen_op_jmp_nz32(flag, l1);
  2401 + tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2404 2402 break;
2405 2403 case 14: /* ne (!=0) */
2406   - gen_op_jmp_nz32(flag, l1);
  2404 + tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2407 2405 break;
2408 2406 case 15: /* t */
2409   - gen_op_mov32(flag, gen_im32(1));
  2407 + tcg_gen_br(l1);
2410 2408 break;
2411 2409 }
2412 2410 gen_jmp_tb(s, 0, s->pc);
... ... @@ -2426,40 +2424,48 @@ DISAS_INSN(fsave)
2426 2424 qemu_assert(0, "FSAVE not implemented");
2427 2425 }
2428 2426  
2429   -static inline int gen_mac_extract_word(DisasContext *s, int val, int upper)
  2427 +static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2430 2428 {
2431   - int tmp = gen_new_qreg(QMODE_I32);
  2429 + TCGv tmp = gen_new_qreg(QMODE_I32);
2432 2430 if (s->env->macsr & MACSR_FI) {
2433 2431 if (upper)
2434   - gen_op_and32(tmp, val, gen_im32(0xffff0000));
  2432 + tcg_gen_andi_i32(tmp, val, 0xffff0000);
2435 2433 else
2436   - gen_op_shl32(tmp, val, gen_im32(16));
  2434 + tcg_gen_shli_i32(tmp, val, 16);
2437 2435 } else if (s->env->macsr & MACSR_SU) {
2438 2436 if (upper)
2439   - gen_op_sar32(tmp, val, gen_im32(16));
  2437 + tcg_gen_sari_i32(tmp, val, 16);
2440 2438 else
2441   - gen_op_ext16s32(tmp, val);
  2439 + tcg_gen_ext16s_i32(tmp, val);
2442 2440 } else {
2443 2441 if (upper)
2444   - gen_op_shr32(tmp, val, gen_im32(16));
  2442 + tcg_gen_shri_i32(tmp, val, 16);
2445 2443 else
2446   - gen_op_ext16u32(tmp, val);
  2444 + tcg_gen_ext16u_i32(tmp, val);
2447 2445 }
2448 2446 return tmp;
2449 2447 }
2450 2448  
  2449 +static void gen_mac_clear_flags(void)
  2450 +{
  2451 + tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
  2452 + ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
  2453 +}
  2454 +
2451 2455 DISAS_INSN(mac)
2452 2456 {
2453   - int rx;
2454   - int ry;
  2457 + TCGv rx;
  2458 + TCGv ry;
2455 2459 uint16_t ext;
2456 2460 int acc;
2457   - int l1;
2458   - int tmp;
2459   - int addr;
2460   - int loadval;
  2461 + TCGv tmp;
  2462 + TCGv addr;
  2463 + TCGv loadval;
2461 2464 int dual;
2462   - int saved_flags = -1;
  2465 + TCGv saved_flags;
  2466 +
  2467 + if (IS_NULL_QREG(s->mactmp))
  2468 + s->mactmp = tcg_temp_new(TCG_TYPE_I64);
2463 2469  
2464 2470 ext = lduw_code(s->pc);
2465 2471 s->pc += 2;
... ... @@ -2474,7 +2480,7 @@ DISAS_INSN(mac)
2474 2480 /* MAC with load. */
2475 2481 tmp = gen_lea(s, insn, OS_LONG);
2476 2482 addr = gen_new_qreg(QMODE_I32);
2477   - gen_op_and32(addr, tmp, QREG_MAC_MASK);
  2483 + tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2478 2484 /* Load the value now to ensure correct exception behavior.
2479 2485 Perform writeback after reading the MAC inputs. */
2480 2486 loadval = gen_load(s, OS_LONG, addr, 0);
... ... @@ -2483,20 +2489,23 @@ DISAS_INSN(mac)
2483 2489 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2484 2490 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2485 2491 } else {
2486   - loadval = addr = -1;
  2492 + loadval = addr = NULL_QREG;
2487 2493 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2488 2494 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2489 2495 }
2490 2496  
2491   - gen_op_mac_clear_flags();
  2497 + gen_mac_clear_flags();
  2498 +#if 0
2492 2499 l1 = -1;
  2500 + /* Disabled because conditional branches clobber temporary vars. */
2493 2501 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2494 2502 /* Skip the multiply if we know we will ignore it. */
2495 2503 l1 = gen_new_label();
2496 2504 tmp = gen_new_qreg(QMODE_I32);
2497   - gen_op_and32(tmp, QREG_MACSR, gen_im32(1 << (acc + 8)));
  2505 + tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2498 2506 gen_op_jmp_nz32(tmp, l1);
2499 2507 }
  2508 +#endif
2500 2509  
2501 2510 if ((ext & 0x0800) == 0) {
2502 2511 /* Word. */
... ... @@ -2504,18 +2513,18 @@ DISAS_INSN(mac)
2504 2513 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2505 2514 }
2506 2515 if (s->env->macsr & MACSR_FI) {
2507   - gen_op_macmulf(rx, ry);
  2516 + gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2508 2517 } else {
2509 2518 if (s->env->macsr & MACSR_SU)
2510   - gen_op_macmuls(rx, ry);
  2519 + gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2511 2520 else
2512   - gen_op_macmulu(rx, ry);
  2521 + gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2513 2522 switch ((ext >> 9) & 3) {
2514 2523 case 1:
2515   - gen_op_macshl();
  2524 + tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2516 2525 break;
2517 2526 case 3:
2518   - gen_op_macshr();
  2527 + tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2519 2528 break;
2520 2529 }
2521 2530 }
... ... @@ -2523,9 +2532,13 @@ DISAS_INSN(mac)
2523 2532 if (dual) {
2524 2533 /* Save the overflow flag from the multiply. */
2525 2534 saved_flags = gen_new_qreg(QMODE_I32);
2526   - gen_op_mov32(saved_flags, QREG_MACSR);
  2535 + tcg_gen_mov_i32(saved_flags, QREG_MACSR);
  2536 + } else {
  2537 + saved_flags = NULL_QREG;
2527 2538 }
2528 2539  
  2540 +#if 0
  2541 + /* Disabled because conditional branches clobber temporary vars. */
2529 2542 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2530 2543 /* Skip the accumulate if the value is already saturated. */
2531 2544 l1 = gen_new_label();
... ... @@ -2533,27 +2546,33 @@ DISAS_INSN(mac)
2533 2546 gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
2534 2547 gen_op_jmp_nz32(tmp, l1);
2535 2548 }
  2549 +#endif
2536 2550  
2537 2551 if (insn & 0x100)
2538   - gen_op_macsub(acc);
  2552 + tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2539 2553 else
2540   - gen_op_macadd(acc);
  2554 + tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2541 2555  
2542 2556 if (s->env->macsr & MACSR_FI)
2543   - gen_op_macsatf(acc);
  2557 + gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2544 2558 else if (s->env->macsr & MACSR_SU)
2545   - gen_op_macsats(acc);
  2559 + gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2546 2560 else
2547   - gen_op_macsatu(acc);
  2561 + gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2548 2562  
  2563 +#if 0
  2564 + /* Disabled because conditional branches clobber temporary vars. */
2549 2565 if (l1 != -1)
2550 2566 gen_set_label(l1);
  2567 +#endif
2551 2568  
2552 2569 if (dual) {
2553 2570 /* Dual accumulate variant. */
2554 2571 acc = (ext >> 2) & 3;
2555 2572 /* Restore the overflow flag from the multiplier. */
2556   - gen_op_mov32(QREG_MACSR, saved_flags);
  2573 + tcg_gen_mov_i32(QREG_MACSR, saved_flags);
  2574 +#if 0
  2575 + /* Disabled because conditional branches clobber temporary vars. */
2557 2576 if ((s->env->macsr & MACSR_OMC) != 0) {
2558 2577 /* Skip the accumulate if the value is already saturated. */
2559 2578 l1 = gen_new_label();
... ... @@ -2561,146 +2580,159 @@ DISAS_INSN(mac)
2561 2580 gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
2562 2581 gen_op_jmp_nz32(tmp, l1);
2563 2582 }
  2583 +#endif
2564 2584 if (ext & 2)
2565   - gen_op_macsub(acc);
  2585 + tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2566 2586 else
2567   - gen_op_macadd(acc);
  2587 + tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2568 2588 if (s->env->macsr & MACSR_FI)
2569   - gen_op_macsatf(acc);
  2589 + gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2570 2590 else if (s->env->macsr & MACSR_SU)
2571   - gen_op_macsats(acc);
  2591 + gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2572 2592 else
2573   - gen_op_macsatu(acc);
  2593 + gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
  2594 +#if 0
  2595 + /* Disabled because conditional branches clobber temporary vars. */
2574 2596 if (l1 != -1)
2575 2597 gen_set_label(l1);
  2598 +#endif
2576 2599 }
2577   - gen_op_mac_set_flags(acc);
  2600 + gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2578 2601  
2579 2602 if (insn & 0x30) {
2580   - int rw;
  2603 + TCGv rw;
2581 2604 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2582   - gen_op_mov32(rw, loadval);
  2605 + tcg_gen_mov_i32(rw, loadval);
2583 2606 /* FIXME: Should address writeback happen with the masked or
2584 2607 unmasked value? */
2585 2608 switch ((insn >> 3) & 7) {
2586 2609 case 3: /* Post-increment. */
2587   - gen_op_add32(AREG(insn, 0), addr, gen_im32(4));
  2610 + tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2588 2611 break;
2589 2612 case 4: /* Pre-decrement. */
2590   - gen_op_mov32(AREG(insn, 0), addr);
  2613 + tcg_gen_mov_i32(AREG(insn, 0), addr);
2591 2614 }
2592 2615 }
2593 2616 }
2594 2617  
2595 2618 DISAS_INSN(from_mac)
2596 2619 {
2597   - int rx;
2598   - int acc;
  2620 + TCGv rx;
  2621 + TCGv acc;
  2622 + int accnum;
2599 2623  
2600 2624 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2601   - acc = (insn >> 9) & 3;
  2625 + accnum = (insn >> 9) & 3;
  2626 + acc = MACREG(accnum);
2602 2627 if (s->env->macsr & MACSR_FI) {
2603   - gen_op_get_macf(rx, acc);
  2628 + gen_helper_get_macf(cpu_env, rx, acc);
2604 2629 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2605   - gen_op_get_maci(rx, acc);
  2630 + tcg_gen_trunc_i64_i32(rx, acc);
2606 2631 } else if (s->env->macsr & MACSR_SU) {
2607   - gen_op_get_macs(rx, acc);
  2632 + gen_helper_get_macs(rx, acc);
2608 2633 } else {
2609   - gen_op_get_macu(rx, acc);
  2634 + gen_helper_get_macu(rx, acc);
  2635 + }
  2636 + if (insn & 0x40) {
  2637 + tcg_gen_movi_i64(acc, 0);
  2638 + tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2610 2639 }
2611   - if (insn & 0x40)
2612   - gen_op_clear_mac(acc);
2613 2640 }
2614 2641  
2615 2642 DISAS_INSN(move_mac)
2616 2643 {
  2644 + /* FIXME: This can be done without a helper. */
2617 2645 int src;
2618   - int dest;
  2646 + TCGv dest;
2619 2647 src = insn & 3;
2620   - dest = (insn >> 9) & 3;
2621   - gen_op_move_mac(dest, src);
2622   - gen_op_mac_clear_flags();
2623   - gen_op_mac_set_flags(dest);
  2648 + dest = tcg_const_i32((insn >> 9) & 3);
  2649 + gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
  2650 + gen_mac_clear_flags();
  2651 + gen_helper_mac_set_flags(cpu_env, dest);
2624 2652 }
2625 2653  
2626 2654 DISAS_INSN(from_macsr)
2627 2655 {
2628   - int reg;
  2656 + TCGv reg;
2629 2657  
2630 2658 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2631   - gen_op_mov32(reg, QREG_MACSR);
  2659 + tcg_gen_mov_i32(reg, QREG_MACSR);
2632 2660 }
2633 2661  
2634 2662 DISAS_INSN(from_mask)
2635 2663 {
2636   - int reg;
  2664 + TCGv reg;
2637 2665 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2638   - gen_op_mov32(reg, QREG_MAC_MASK);
  2666 + tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2639 2667 }
2640 2668  
2641 2669 DISAS_INSN(from_mext)
2642 2670 {
2643   - int reg;
2644   - int acc;
  2671 + TCGv reg;
  2672 + TCGv acc;
2645 2673 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2646   - acc = (insn & 0x400) ? 2 : 0;
  2674 + acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2647 2675 if (s->env->macsr & MACSR_FI)
2648   - gen_op_get_mac_extf(reg, acc);
  2676 + gen_helper_get_mac_extf(reg, cpu_env, acc);
2649 2677 else
2650   - gen_op_get_mac_exti(reg, acc);
  2678 + gen_helper_get_mac_exti(reg, cpu_env, acc);
2651 2679 }
2652 2680  
2653 2681 DISAS_INSN(macsr_to_ccr)
2654 2682 {
2655   - gen_op_mov32(QREG_CC_X, gen_im32(0));
2656   - gen_op_and32(QREG_CC_DEST, QREG_MACSR, gen_im32(0xf));
  2683 + tcg_gen_movi_i32(QREG_CC_X, 0);
  2684 + tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
2657 2685 s->cc_op = CC_OP_FLAGS;
2658 2686 }
2659 2687  
2660 2688 DISAS_INSN(to_mac)
2661 2689 {
2662   - int acc;
2663   - int val;
2664   - acc = (insn >>9) & 3;
  2690 + TCGv acc;
  2691 + TCGv val;
  2692 + int accnum;
  2693 + accnum = (insn >> 9) & 3;
  2694 + acc = MACREG(accnum);
2665 2695 SRC_EA(val, OS_LONG, 0, NULL);
2666 2696 if (s->env->macsr & MACSR_FI) {
2667   - gen_op_set_macf(val, acc);
  2697 + tcg_gen_ext_i32_i64(acc, val);
  2698 + tcg_gen_shli_i64(acc, acc, 8);
2668 2699 } else if (s->env->macsr & MACSR_SU) {
2669   - gen_op_set_macs(val, acc);
  2700 + tcg_gen_ext_i32_i64(acc, val);
2670 2701 } else {
2671   - gen_op_set_macu(val, acc);
  2702 + tcg_gen_extu_i32_i64(acc, val);
2672 2703 }
2673   - gen_op_mac_clear_flags();
2674   - gen_op_mac_set_flags(acc);
  2704 + tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
  2705 + gen_mac_clear_flags();
  2706 + gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2675 2707 }
2676 2708  
2677 2709 DISAS_INSN(to_macsr)
2678 2710 {
2679   - int val;
  2711 + TCGv val;
2680 2712 SRC_EA(val, OS_LONG, 0, NULL);
2681   - gen_op_set_macsr(val);
  2713 + gen_helper_set_macsr(cpu_env, val);
2682 2714 gen_lookup_tb(s);
2683 2715 }
2684 2716  
2685 2717 DISAS_INSN(to_mask)
2686 2718 {
2687   - int val;
  2719 + TCGv val;
2688 2720 SRC_EA(val, OS_LONG, 0, NULL);
2689   - gen_op_or32(QREG_MAC_MASK, val, gen_im32(0xffff0000));
  2721 + tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2690 2722 }
2691 2723  
2692 2724 DISAS_INSN(to_mext)
2693 2725 {
2694   - int val;
2695   - int acc;
  2726 + TCGv val;
  2727 + TCGv acc;
2696 2728 SRC_EA(val, OS_LONG, 0, NULL);
2697   - acc = (insn & 0x400) ? 2 : 0;
  2729 + acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2698 2730 if (s->env->macsr & MACSR_FI)
2699   - gen_op_set_mac_extf(val, acc);
  2731 + gen_helper_set_mac_extf(cpu_env, val, acc);
2700 2732 else if (s->env->macsr & MACSR_SU)
2701   - gen_op_set_mac_exts(val, acc);
  2733 + gen_helper_set_mac_exts(cpu_env, val, acc);
2702 2734 else
2703   - gen_op_set_mac_extu(val, acc);
  2735 + gen_helper_set_mac_extu(cpu_env, val, acc);
2704 2736 }
2705 2737  
2706 2738 static disas_proc opcode_table[65536];
... ... @@ -2876,263 +2908,6 @@ static void disas_m68k_insn(CPUState * env, DisasContext *s)
2876 2908 opcode_table[insn](s, insn);
2877 2909 }
2878 2910  
2879   -#if 0
2880   -/* Save the result of a floating point operation. */
2881   -static void expand_op_fp_result(qOP *qop)
2882   -{
2883   - gen_op_movf64(QREG_FP_RESULT, qop->args[0]);
2884   -}
2885   -
2886   -/* Dummy op to indicate that the flags have been set. */
2887   -static void expand_op_flags_set(qOP *qop)
2888   -{
2889   -}
2890   -
2891   -/* Convert the confition codes into CC_OP_FLAGS format. */
2892   -static void expand_op_flush_flags(qOP *qop)
2893   -{
2894   - int cc_opreg;
2895   -
2896   - if (qop->args[0] == CC_OP_DYNAMIC)
2897   - cc_opreg = QREG_CC_OP;
2898   - else
2899   - cc_opreg = gen_im32(qop->args[0]);
2900   - gen_op_helper32(QREG_NULL, cc_opreg, HELPER_flush_flags);
2901   -}
2902   -
2903   -/* Set CC_DEST after a logical or direct flag setting operation. */
2904   -static void expand_op_logic_cc(qOP *qop)
2905   -{
2906   - gen_op_mov32(QREG_CC_DEST, qop->args[0]);
2907   -}
2908   -
2909   -/* Set CC_SRC and CC_DEST after an arithmetic operation. */
2910   -static void expand_op_update_cc_add(qOP *qop)
2911   -{
2912   - gen_op_mov32(QREG_CC_DEST, qop->args[0]);
2913   - gen_op_mov32(QREG_CC_SRC, qop->args[1]);
2914   -}
2915   -
2916   -/* Update the X flag. */
2917   -static void expand_op_update_xflag(qOP *qop)
2918   -{
2919   - int arg0;
2920   - int arg1;
2921   -
2922   - arg0 = qop->args[0];
2923   - arg1 = qop->args[1];
2924   - if (arg1 == QREG_NULL) {
2925   - /* CC_X = arg0. */
2926   - gen_op_mov32(QREG_CC_X, arg0);
2927   - } else {
2928   - /* CC_X = arg0 < (unsigned)arg1. */
2929   - gen_op_set_ltu32(QREG_CC_X, arg0, arg1);
2930   - }
2931   -}
2932   -
2933   -/* Set arg0 to the contents of the X flag. */
2934   -static void expand_op_get_xflag(qOP *qop)
2935   -{
2936   - gen_op_mov32(qop->args[0], QREG_CC_X);
2937   -}
2938   -
2939   -/* Expand a shift by immediate. The ISA only allows shifts by 1-8, so we
2940   - already know the shift is within range. */
2941   -static inline void expand_shift_im(qOP *qop, int right, int arith)
2942   -{
2943   - int val;
2944   - int reg;
2945   - int tmp;
2946   - int im;
2947   -
2948   - reg = qop->args[0];
2949   - im = qop->args[1];
2950   - tmp = gen_im32(im);
2951   - val = gen_new_qreg(QMODE_I32);
2952   - gen_op_mov32(val, reg);
2953   - gen_op_mov32(QREG_CC_DEST, val);
2954   - gen_op_mov32(QREG_CC_SRC, tmp);
2955   - if (right) {
2956   - if (arith) {
2957   - gen_op_sar32(reg, val, tmp);
2958   - } else {
2959   - gen_op_shr32(reg, val, tmp);
2960   - }
2961   - if (im == 1)
2962   - tmp = QREG_NULL;
2963   - else
2964   - tmp = gen_im32(im - 1);
2965   - } else {
2966   - gen_op_shl32(reg, val, tmp);
2967   - tmp = gen_im32(32 - im);
2968   - }
2969   - if (tmp != QREG_NULL)
2970   - gen_op_shr32(val, val, tmp);
2971   - gen_op_and32(QREG_CC_X, val, gen_im32(1));
2972   -}
2973   -
2974   -static void expand_op_shl_im_cc(qOP *qop)
2975   -{
2976   - expand_shift_im(qop, 0, 0);
2977   -}
2978   -
2979   -static void expand_op_shr_im_cc(qOP *qop)
2980   -{
2981   - expand_shift_im(qop, 1, 0);
2982   -}
2983   -
2984   -static void expand_op_sar_im_cc(qOP *qop)
2985   -{
2986   - expand_shift_im(qop, 1, 1);
2987   -}
2988   -
2989   -/* Expand a shift by register. */
2990   -/* ??? This gives incorrect answers for shifts by 0 or >= 32 */
2991   -static inline void expand_shift_reg(qOP *qop, int right, int arith)
2992   -{
2993   - int val;
2994   - int reg;
2995   - int shift;
2996   - int tmp;
2997   -
2998   - reg = qop->args[0];
2999   - shift = qop->args[1];
3000   - val = gen_new_qreg(QMODE_I32);
3001   - gen_op_mov32(val, reg);
3002   - gen_op_mov32(QREG_CC_DEST, val);
3003   - gen_op_mov32(QREG_CC_SRC, shift);
3004   - tmp = gen_new_qreg(QMODE_I32);
3005   - if (right) {
3006   - if (arith) {
3007   - gen_op_sar32(reg, val, shift);
3008   - } else {
3009   - gen_op_shr32(reg, val, shift);
3010   - }
3011   - gen_op_sub32(tmp, shift, gen_im32(1));
3012   - } else {
3013   - gen_op_shl32(reg, val, shift);
3014   - gen_op_sub32(tmp, gen_im32(31), shift);
3015   - }
3016   - gen_op_shl32(val, val, tmp);
3017   - gen_op_and32(QREG_CC_X, val, gen_im32(1));
3018   -}
3019   -
3020   -static void expand_op_shl_cc(qOP *qop)
3021   -{
3022   - expand_shift_reg(qop, 0, 0);
3023   -}
3024   -
3025   -static void expand_op_shr_cc(qOP *qop)
3026   -{
3027   - expand_shift_reg(qop, 1, 0);
3028   -}
3029   -
3030   -static void expand_op_sar_cc(qOP *qop)
3031   -{
3032   - expand_shift_reg(qop, 1, 1);
3033   -}
3034   -
3035   -/* Set the Z flag to (arg0 & arg1) == 0. */
3036   -static void expand_op_btest(qOP *qop)
3037   -{
3038   - int tmp;
3039   - int l1;
3040   -
3041   - l1 = gen_new_label();
3042   - tmp = gen_new_qreg(QMODE_I32);
3043   - gen_op_and32(tmp, qop->args[0], qop->args[1]);
3044   - gen_op_and32(QREG_CC_DEST, QREG_CC_DEST, gen_im32(~(uint32_t)CCF_Z));
3045   - gen_op_jmp_nz32(tmp, l1);
3046   - gen_op_or32(QREG_CC_DEST, QREG_CC_DEST, gen_im32(CCF_Z));
3047   - gen_op_label(l1);
3048   -}
3049   -
3050   -/* arg0 += arg1 + CC_X */
3051   -static void expand_op_addx_cc(qOP *qop)
3052   -{
3053   - int arg0 = qop->args[0];
3054   - int arg1 = qop->args[1];
3055   - int l1, l2;
3056   -
3057   - gen_op_add32 (arg0, arg0, arg1);
3058   - l1 = gen_new_label();
3059   - l2 = gen_new_label();
3060   - gen_op_jmp_z32(QREG_CC_X, l1);
3061   - gen_op_add32(arg0, arg0, gen_im32(1));
3062   - gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_ADDX));
3063   - gen_op_set_leu32(QREG_CC_X, arg0, arg1);
3064   - gen_op_jmp_im(l2);
3065   - gen_set_label(l1);
3066   - gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_ADD));
3067   - gen_op_set_ltu32(QREG_CC_X, arg0, arg1);
3068   - gen_set_label(l2);
3069   -}
3070   -
3071   -/* arg0 -= arg1 + CC_X */
3072   -static void expand_op_subx_cc(qOP *qop)
3073   -{
3074   - int arg0 = qop->args[0];
3075   - int arg1 = qop->args[1];
3076   - int l1, l2;
3077   -
3078   - l1 = gen_new_label();
3079   - l2 = gen_new_label();
3080   - gen_op_jmp_z32(QREG_CC_X, l1);
3081   - gen_op_set_leu32(QREG_CC_X, arg0, arg1);
3082   - gen_op_sub32(arg0, arg0, gen_im32(1));
3083   - gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_SUBX));
3084   - gen_op_jmp_im(l2);
3085   - gen_set_label(l1);
3086   - gen_op_set_ltu32(QREG_CC_X, arg0, arg1);
3087   - gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_SUB));
3088   - gen_set_label(l2);
3089   - gen_op_sub32 (arg0, arg0, arg1);
3090   -}
3091   -
3092   -/* Expand target specific ops to generic qops. */
3093   -static void expand_target_qops(void)
3094   -{
3095   - qOP *qop;
3096   - qOP *next;
3097   - int c;
3098   -
3099   - /* Copy the list of qops, expanding target specific ops as we go. */
3100   - qop = gen_first_qop;
3101   - gen_first_qop = NULL;
3102   - gen_last_qop = NULL;
3103   - for (; qop; qop = next) {
3104   - c = qop->opcode;
3105   - next = qop->next;
3106   - if (c < FIRST_TARGET_OP) {
3107   - qop->prev = gen_last_qop;
3108   - qop->next = NULL;
3109   - if (gen_last_qop)
3110   - gen_last_qop->next = qop;
3111   - else
3112   - gen_first_qop = qop;
3113   - gen_last_qop = qop;
3114   - continue;
3115   - }
3116   - switch (c) {
3117   -#define DEF(name, nargs, barrier) \
3118   - case INDEX_op_##name: \
3119   - expand_op_##name(qop); \
3120   - break;
3121   -#include "qop-target.def"
3122   -#undef DEF
3123   - default:
3124   - cpu_abort(NULL, "Unexpanded target qop");
3125   - }
3126   - }
3127   -}
3128   -
3129   -/* ??? Implement this. */
3130   -static void
3131   -optimize_flags(void)
3132   -{
3133   -}
3134   -#endif
3135   -
3136 2911 /* generate intermediate code for basic block 'tb'. */
3137 2912 static inline int
3138 2913 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
... ... @@ -3160,9 +2935,9 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3160 2935 dc->fpcr = env->fpcr;
3161 2936 dc->user = (env->sr & SR_S) == 0;
3162 2937 dc->is_mem = 0;
  2938 + dc->mactmp = NULL_QREG;
3163 2939 lj = -1;
3164 2940 do {
3165   - free_qreg = 0;
3166 2941 pc_offset = dc->pc - pc_start;
3167 2942 gen_throws_exception = NULL;
3168 2943 if (env->nb_breakpoints > 0) {
... ... @@ -3203,9 +2978,9 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3203 2978 /* Make sure the pc is updated, and raise a debug exception. */
3204 2979 if (!dc->is_jmp) {
3205 2980 gen_flush_cc_op(dc);
3206   - gen_op_mov32(QREG_PC, gen_im32((long)dc->pc));
  2981 + tcg_gen_movi_i32(QREG_PC, dc->pc);
3207 2982 }
3208   - gen_op_raise_exception(EXCP_DEBUG);
  2983 + gen_helper_raise_exception(tcg_const_i32(EXCP_DEBUG));
3209 2984 } else {
3210 2985 switch(dc->is_jmp) {
3211 2986 case DISAS_NEXT:
... ...