gwj / at91sam9263 · Commits

Commit e1dad5a615fb4a2d5cd43cbc0fc42f6a0d35f2e9

Authored by balrog
1 parent 749bc4bf

Better STOPINTR bit semantics in the PXA2xx DMA. 

Don't error out on reading GPCR register, just warn (Thorsten Zitterell).
Don't zero a memory that's already zeroed.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3676 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 9 additions and 3 deletions
hw/pxa2xx_dma.c
  View file @e1dad5a
@@ -348,8 +348,10 @@ static void pxa2xx_dma_write(void *opaque, @@ -348,8 +348,10 @@ static void pxa2xx_dma_write(void *opaque,
348 348
349 if (value & DCSR_NODESCFETCH) { 349 if (value & DCSR_NODESCFETCH) {
350 /* No-descriptor-fetch mode */ 350 /* No-descriptor-fetch mode */
351 - if (value & DCSR_RUN) 351 + if (value & DCSR_RUN) {
  352 + s->chan[channel].state &= ~DCSR_STOPINTR;
352 pxa2xx_dma_run(s); 353 pxa2xx_dma_run(s);
  354 + }
353 } else { 355 } else {
354 /* Descriptor-fetch mode */ 356 /* Descriptor-fetch mode */
355 if (value & DCSR_RUN) { 357 if (value & DCSR_RUN) {
hw/pxa2xx_gpio.c
  View file @e1dad5a
@@ -154,6 +154,11 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) @@ -154,6 +154,11 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
154 __FUNCTION__, offset); 154 __FUNCTION__, offset);
155 return s->gpsr[bank]; /* Return last written value. */ 155 return s->gpsr[bank]; /* Return last written value. */
156 156
  157 + case GPCR: /* GPIO Pin-Output Clear registers */
  158 + printf("%s: Read from a write-only register " REG_FMT "\n",
  159 + __FUNCTION__, offset);
  160 + return 31337; /* Specified as unpredictable in the docs. */
  161 +
157 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 162 case GRER: /* GPIO Rising-Edge Detect Enable registers */
158 return s->rising[bank]; 163 return s->rising[bank];
159 164
hw/pxa2xx_mmci.c
  View file @e1dad5a
@@ -549,5 +549,5 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, @@ -549,5 +549,5 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
549 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, 549 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
550 qemu_irq coverswitch) 550 qemu_irq coverswitch)
551 { 551 {
552 - sd_set_cb(s->card, read, coverswitch); 552 + sd_set_cb(s->card, readonly, coverswitch);
553 } 553 }
@@ -377,7 +377,6 @@ static void sd_reset(SDState *sd, BlockDriverState *bdrv) @@ -377,7 +377,6 @@ static void sd_reset(SDState *sd, BlockDriverState *bdrv)
377 qemu_free(sd->wp_groups); 377 qemu_free(sd->wp_groups);
378 sd->wp_switch = bdrv_is_read_only(bdrv); 378 sd->wp_switch = bdrv_is_read_only(bdrv);
379 sd->wp_groups = (int *) qemu_mallocz(sizeof(int) * sect); 379 sd->wp_groups = (int *) qemu_mallocz(sizeof(int) * sect);
380 - memset(sd->wp_groups, 0, sizeof(int) * sect);  
381 memset(sd->function_group, 0, sizeof(int) * 6); 380 memset(sd->function_group, 0, sizeof(int) * 6);
382 sd->erase_start = 0; 381 sd->erase_start = 0;
383 sd->erase_end = 0; 382 sd->erase_end = 0;