Commit e19e4efeaa250e269b491f3a04e04a35831d313a
1 parent
477b24ef
Fix MMU miss traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4880 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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4 additions
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4 deletions
target-sparc/cpu.h
... | ... | @@ -50,7 +50,6 @@ |
50 | 50 | #define TT_TRAP 0x80 |
51 | 51 | #else |
52 | 52 | #define TT_TFAULT 0x08 |
53 | -#define TT_TMISS 0x09 | |
54 | 53 | #define TT_CODE_ACCESS 0x0a |
55 | 54 | #define TT_ILL_INSN 0x10 |
56 | 55 | #define TT_UNIMP_FLUSH TT_ILL_INSN |
... | ... | @@ -61,12 +60,13 @@ |
61 | 60 | #define TT_CLRWIN 0x24 |
62 | 61 | #define TT_DIV_ZERO 0x28 |
63 | 62 | #define TT_DFAULT 0x30 |
64 | -#define TT_DMISS 0x31 | |
65 | 63 | #define TT_DATA_ACCESS 0x32 |
66 | 64 | #define TT_DPROT 0x33 |
67 | 65 | #define TT_UNALIGNED 0x34 |
68 | 66 | #define TT_PRIV_ACT 0x37 |
69 | 67 | #define TT_EXTINT 0x40 |
68 | +#define TT_TMISS 0x64 | |
69 | +#define TT_DMISS 0x68 | |
70 | 70 | #define TT_SPILL 0x80 |
71 | 71 | #define TT_FILL 0xc0 |
72 | 72 | #define TT_WOTHER 0x10 | ... | ... |
target-sparc/helper.c
... | ... | @@ -655,7 +655,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
655 | 655 | |
656 | 656 | #ifdef TARGET_SPARC64 |
657 | 657 | #ifdef DEBUG_PCALL |
658 | -static const char * const excp_names[0x50] = { | |
658 | +static const char * const excp_names[0x80] = { | |
659 | 659 | [TT_TFAULT] = "Instruction Access Fault", |
660 | 660 | [TT_TMISS] = "Instruction Access MMU Miss", |
661 | 661 | [TT_CODE_ACCESS] = "Instruction Access Error", |
... | ... | @@ -699,7 +699,7 @@ void do_interrupt(CPUState *env) |
699 | 699 | static int count; |
700 | 700 | const char *name; |
701 | 701 | |
702 | - if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80)) | |
702 | + if (intno < 0 || intno >= 0x180) | |
703 | 703 | name = "Unknown"; |
704 | 704 | else if (intno >= 0x100) |
705 | 705 | name = "Trap Instruction"; | ... | ... |