gwj / at91sam9263 · Commits

Commit e108dd01ce8fd3af84929ce925f791e1086a7a75

Authored by bellard
1 parent d1896336

converted sign extension ops to TCG 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4481 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 31 additions and 76 deletions
target-i386/op.c
  View file @e108dd0
@@ -263,67 +263,6 @@ void OPPROTO op_cmpxchg8b(void) @@ -263,67 +263,6 @@ void OPPROTO op_cmpxchg8b(void)
263 263
264 #endif 264 #endif
265 265
266 -/* sign extend */  
267 -  
268 -void OPPROTO op_movsbl_T0_T0(void)  
269 -{  
270 - T0 = (int8_t)T0;  
271 -}  
272 -  
273 -void OPPROTO op_movzbl_T0_T0(void)  
274 -{  
275 - T0 = (uint8_t)T0;  
276 -}  
277 -  
278 -void OPPROTO op_movswl_T0_T0(void)  
279 -{  
280 - T0 = (int16_t)T0;  
281 -}  
282 -  
283 -void OPPROTO op_movzwl_T0_T0(void)  
284 -{  
285 - T0 = (uint16_t)T0;  
286 -}  
287 -  
288 -void OPPROTO op_movswl_EAX_AX(void)  
289 -{  
290 - EAX = (uint32_t)((int16_t)EAX);  
291 -}  
292 -  
293 -#ifdef TARGET_X86_64  
294 -void OPPROTO op_movslq_T0_T0(void)  
295 -{  
296 - T0 = (int32_t)T0;  
297 -}  
298 -  
299 -void OPPROTO op_movslq_RAX_EAX(void)  
300 -{  
301 - EAX = (int32_t)EAX;  
302 -}  
303 -#endif  
304 -  
305 -void OPPROTO op_movsbw_AX_AL(void)  
306 -{  
307 - EAX = (EAX & ~0xffff) | ((int8_t)EAX & 0xffff);  
308 -}  
309 -  
310 -void OPPROTO op_movslq_EDX_EAX(void)  
311 -{  
312 - EDX = (uint32_t)((int32_t)EAX >> 31);  
313 -}  
314 -  
315 -void OPPROTO op_movswl_DX_AX(void)  
316 -{  
317 - EDX = (EDX & ~0xffff) | (((int16_t)EAX >> 15) & 0xffff);  
318 -}  
319 -  
320 -#ifdef TARGET_X86_64  
321 -void OPPROTO op_movsqo_RDX_RAX(void)  
322 -{  
323 - EDX = (int64_t)EAX >> 63;  
324 -}  
325 -#endif  
326 -  
327 /* string ops helpers */ 266 /* string ops helpers */
328 267
329 void OPPROTO op_addl_ESI_T0(void) 268 void OPPROTO op_addl_ESI_T0(void)
target-i386/translate.c
  View file @e108dd0
@@ -4109,24 +4109,40 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) @@ -4109,24 +4109,40 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4109 case 0x98: /* CWDE/CBW */ 4109 case 0x98: /* CWDE/CBW */
4110 #ifdef TARGET_X86_64 4110 #ifdef TARGET_X86_64
4111 if (dflag == 2) { 4111 if (dflag == 2) {
4112 - gen_op_movslq_RAX_EAX(); 4112 + gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
  4113 + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  4114 + gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4113 } else 4115 } else
4114 #endif 4116 #endif
4115 - if (dflag == 1)  
4116 - gen_op_movswl_EAX_AX();  
4117 - else  
4118 - gen_op_movsbw_AX_AL(); 4117 + if (dflag == 1) {
  4118 + gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
  4119 + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
  4120 + gen_op_mov_reg_T0(OT_LONG, R_EAX);
  4121 + } else {
  4122 + gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
  4123 + tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
  4124 + gen_op_mov_reg_T0(OT_WORD, R_EAX);
  4125 + }
4119 break; 4126 break;
4120 case 0x99: /* CDQ/CWD */ 4127 case 0x99: /* CDQ/CWD */
4121 #ifdef TARGET_X86_64 4128 #ifdef TARGET_X86_64
4122 if (dflag == 2) { 4129 if (dflag == 2) {
4123 - gen_op_movsqo_RDX_RAX(); 4130 + gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
  4131 + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
  4132 + gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4124 } else 4133 } else
4125 #endif 4134 #endif
4126 - if (dflag == 1)  
4127 - gen_op_movslq_EDX_EAX();  
4128 - else  
4129 - gen_op_movswl_DX_AX(); 4135 + if (dflag == 1) {
  4136 + gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
  4137 + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  4138 + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
  4139 + gen_op_mov_reg_T0(OT_LONG, R_EDX);
  4140 + } else {
  4141 + gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
  4142 + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
  4143 + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
  4144 + gen_op_mov_reg_T0(OT_WORD, R_EDX);
  4145 + }
4130 break; 4146 break;
4131 case 0x1af: /* imul Gv, Ev */ 4147 case 0x1af: /* imul Gv, Ev */
4132 case 0x69: /* imul Gv, Ev, I */ 4148 case 0x69: /* imul Gv, Ev, I */
@@ -4479,17 +4495,17 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) @@ -4479,17 +4495,17 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4479 gen_op_mov_TN_reg(ot, 0, rm); 4495 gen_op_mov_TN_reg(ot, 0, rm);
4480 switch(ot | (b & 8)) { 4496 switch(ot | (b & 8)) {
4481 case OT_BYTE: 4497 case OT_BYTE:
4482 - gen_op_movzbl_T0_T0(); 4498 + tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4483 break; 4499 break;
4484 case OT_BYTE | 8: 4500 case OT_BYTE | 8:
4485 - gen_op_movsbl_T0_T0(); 4501 + tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4486 break; 4502 break;
4487 case OT_WORD: 4503 case OT_WORD:
4488 - gen_op_movzwl_T0_T0(); 4504 + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4489 break; 4505 break;
4490 default: 4506 default:
4491 case OT_WORD | 8: 4507 case OT_WORD | 8:
4492 - gen_op_movswl_T0_T0(); 4508 + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4493 break; 4509 break;
4494 } 4510 }
4495 gen_op_mov_reg_T0(d_ot, reg); 4511 gen_op_mov_reg_T0(d_ot, reg);
@@ -6481,7 +6497,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) @@ -6481,7 +6497,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
6481 gen_op_mov_TN_reg(OT_LONG, 0, rm); 6497 gen_op_mov_TN_reg(OT_LONG, 0, rm);
6482 /* sign extend */ 6498 /* sign extend */
6483 if (d_ot == OT_QUAD) 6499 if (d_ot == OT_QUAD)
6484 - gen_op_movslq_T0_T0(); 6500 + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
6485 gen_op_mov_reg_T0(d_ot, reg); 6501 gen_op_mov_reg_T0(d_ot, reg);
6486 } else { 6502 } else {
6487 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); 6503 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);