gwj / at91sam9263 · Commits

Commit e06fcd754eb630e16c4fef62e2f899402d06cc4a

Authored by aurel32
1 parent 2a3ec4b5

target-ppc: rework exception code 

... also remove two warnings.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 7 changed files with 288 additions and 304 deletions
cpu-exec.c
  View file @e06fcd7
@@ -918,7 +918,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, @@ -918,7 +918,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
918 /* we restore the process signal mask as the sigreturn should 918 /* we restore the process signal mask as the sigreturn should
919 do it (XXX: use sigsetjmp) */ 919 do it (XXX: use sigsetjmp) */
920 sigprocmask(SIG_SETMASK, old_set, NULL); 920 sigprocmask(SIG_SETMASK, old_set, NULL);
921 - raise_exception_err(env, env->exception_index, env->error_code); 921 + cpu_loop_exit();
922 } else { 922 } else {
923 /* activate soft MMU for this block */ 923 /* activate soft MMU for this block */
924 cpu_resume_from_signal(env, puc); 924 cpu_resume_from_signal(env, puc);
target-ppc/exec.h
  View file @e06fcd7
@@ -38,9 +38,6 @@ register struct CPUPPCState *env asm(AREG0); @@ -38,9 +38,6 @@ register struct CPUPPCState *env asm(AREG0);
38 #include "softmmu_exec.h" 38 #include "softmmu_exec.h"
39 #endif /* !defined(CONFIG_USER_ONLY) */ 39 #endif /* !defined(CONFIG_USER_ONLY) */
40 40
41 -void raise_exception_err (CPUState *env, int exception, int error_code);  
42 -void raise_exception (CPUState *env, int exception);  
43 -  
44 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr, 41 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
45 int rw, int access_type); 42 int rw, int access_type);
46 43
target-ppc/helper.c
  View file @e06fcd7
@@ -40,24 +40,6 @@ @@ -40,24 +40,6 @@
40 //#define FLUSH_ALL_TLBS 40 //#define FLUSH_ALL_TLBS
41 41
42 /*****************************************************************************/ 42 /*****************************************************************************/
43 -/* Exceptions processing */  
44 -  
45 -void raise_exception_err (CPUState *env, int exception, int error_code)  
46 -{  
47 -#if 0  
48 - printf("Raise exception %3x code : %d\n", exception, error_code);  
49 -#endif  
50 - env->exception_index = exception;  
51 - env->error_code = error_code;  
52 - cpu_loop_exit();  
53 -}  
54 -  
55 -void raise_exception (CPUState *env, int exception)  
56 -{  
57 - helper_raise_exception_err(exception, 0);  
58 -}  
59 -  
60 -/*****************************************************************************/  
61 /* PowerPC MMU emulation */ 43 /* PowerPC MMU emulation */
62 44
63 #if defined(CONFIG_USER_ONLY) 45 #if defined(CONFIG_USER_ONLY)
target-ppc/helper.h
  View file @e06fcd7
1 #include "def-helper.h" 1 #include "def-helper.h"
2 2
3 DEF_HELPER_2(raise_exception_err, void, i32, i32) 3 DEF_HELPER_2(raise_exception_err, void, i32, i32)
4 -DEF_HELPER_0(raise_debug, void) 4 +DEF_HELPER_1(raise_exception, void, i32)
5 DEF_HELPER_3(tw, void, tl, tl, i32) 5 DEF_HELPER_3(tw, void, tl, tl, i32)
6 #if defined(TARGET_PPC64) 6 #if defined(TARGET_PPC64)
7 DEF_HELPER_3(td, void, tl, tl, i32) 7 DEF_HELPER_3(td, void, tl, tl, i32)
target-ppc/op_helper.c
  View file @e06fcd7
@@ -32,12 +32,17 @@ @@ -32,12 +32,17 @@
32 32
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code) 33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
34 { 34 {
35 - raise_exception_err(env, exception, error_code); 35 +#if 0
  36 + printf("Raise exception %3x code : %d\n", exception, error_code);
  37 +#endif
  38 + env->exception_index = exception;
  39 + env->error_code = error_code;
  40 + cpu_loop_exit();
36 } 41 }
37 42
38 -void helper_raise_debug (void) 43 +void helper_raise_exception (uint32_t exception)
39 { 44 {
40 - raise_exception(env, EXCP_DEBUG); 45 + helper_raise_exception_err(exception, 0);
41 } 46 }
42 47
43 /*****************************************************************************/ 48 /*****************************************************************************/
@@ -315,9 +320,9 @@ void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb) @@ -315,9 +320,9 @@ void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
315 if (likely(xer_bc != 0)) { 320 if (likely(xer_bc != 0)) {
316 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) || 321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
317 (reg < rb && (reg + xer_bc) > rb))) { 322 (reg < rb && (reg + xer_bc) > rb))) {
318 - raise_exception_err(env, POWERPC_EXCP_PROGRAM,  
319 - POWERPC_EXCP_INVAL |  
320 - POWERPC_EXCP_INVAL_LSWX); 323 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
  324 + POWERPC_EXCP_INVAL |
  325 + POWERPC_EXCP_INVAL_LSWX);
321 } else { 326 } else {
322 helper_lsw(addr, xer_bc, reg); 327 helper_lsw(addr, xer_bc, reg);
323 } 328 }
@@ -738,7 +743,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op) @@ -738,7 +743,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op)
738 /* Update the floating-point enabled exception summary */ 743 /* Update the floating-point enabled exception summary */
739 env->fpscr |= 1 << FPSCR_FEX; 744 env->fpscr |= 1 << FPSCR_FEX;
740 if (msr_fe0 != 0 || msr_fe1 != 0) 745 if (msr_fe0 != 0 || msr_fe1 != 0)
741 - raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op); 746 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
742 } 747 }
743 return ret; 748 return ret;
744 } 749 }
@@ -753,8 +758,8 @@ static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t ar @@ -753,8 +758,8 @@ static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t ar
753 /* Update the floating-point enabled exception summary */ 758 /* Update the floating-point enabled exception summary */
754 env->fpscr |= 1 << FPSCR_FEX; 759 env->fpscr |= 1 << FPSCR_FEX;
755 if (msr_fe0 != 0 || msr_fe1 != 0) { 760 if (msr_fe0 != 0 || msr_fe1 != 0) {
756 - raise_exception_err(env, POWERPC_EXCP_PROGRAM,  
757 - POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX); 761 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
  762 + POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
758 } 763 }
759 } else { 764 } else {
760 /* Set the result to infinity */ 765 /* Set the result to infinity */
@@ -994,7 +999,7 @@ void helper_float_check_status (void) @@ -994,7 +999,7 @@ void helper_float_check_status (void)
994 (env->error_code & POWERPC_EXCP_FP)) { 999 (env->error_code & POWERPC_EXCP_FP)) {
995 /* Differred floating-point exception after target FPR update */ 1000 /* Differred floating-point exception after target FPR update */
996 if (msr_fe0 != 0 || msr_fe1 != 0) 1001 if (msr_fe0 != 0 || msr_fe1 != 0)
997 - raise_exception_err(env, env->exception_index, env->error_code); 1002 + helper_raise_exception_err(env->exception_index, env->error_code);
998 } else if (env->fp_status.float_exception_flags & float_flag_overflow) { 1003 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
999 float_overflow_excp(); 1004 float_overflow_excp();
1000 } else if (env->fp_status.float_exception_flags & float_flag_underflow) { 1005 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
@@ -1007,7 +1012,7 @@ void helper_float_check_status (void) @@ -1007,7 +1012,7 @@ void helper_float_check_status (void)
1007 (env->error_code & POWERPC_EXCP_FP)) { 1012 (env->error_code & POWERPC_EXCP_FP)) {
1008 /* Differred floating-point exception after target FPR update */ 1013 /* Differred floating-point exception after target FPR update */
1009 if (msr_fe0 != 0 || msr_fe1 != 0) 1014 if (msr_fe0 != 0 || msr_fe1 != 0)
1010 - raise_exception_err(env, env->exception_index, env->error_code); 1015 + helper_raise_exception_err(env->exception_index, env->error_code);
1011 } 1016 }
1012 #endif 1017 #endif
1013 } 1018 }
@@ -1660,7 +1665,7 @@ void helper_store_msr (target_ulong val) @@ -1660,7 +1665,7 @@ void helper_store_msr (target_ulong val)
1660 val = hreg_store_msr(env, val, 0); 1665 val = hreg_store_msr(env, val, 0);
1661 if (val != 0) { 1666 if (val != 0) {
1662 env->interrupt_request |= CPU_INTERRUPT_EXITTB; 1667 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1663 - raise_exception(env, val); 1668 + helper_raise_exception(val);
1664 } 1669 }
1665 } 1670 }
1666 1671
@@ -1723,7 +1728,7 @@ void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags) @@ -1723,7 +1728,7 @@ void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1723 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || 1728 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1724 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || 1729 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1725 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { 1730 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1726 - raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 1731 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1727 } 1732 }
1728 } 1733 }
1729 1734
@@ -1735,7 +1740,7 @@ void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags) @@ -1735,7 +1740,7 @@ void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1735 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || 1740 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1736 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || 1741 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1737 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) 1742 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1738 - raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 1743 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1739 } 1744 }
1740 #endif 1745 #endif
1741 1746
@@ -1902,14 +1907,14 @@ target_ulong helper_load_dcr (target_ulong dcrn) @@ -1902,14 +1907,14 @@ target_ulong helper_load_dcr (target_ulong dcrn)
1902 if (loglevel != 0) { 1907 if (loglevel != 0) {
1903 fprintf(logfile, "No DCR environment\n"); 1908 fprintf(logfile, "No DCR environment\n");
1904 } 1909 }
1905 - raise_exception_err(env, POWERPC_EXCP_PROGRAM,  
1906 - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); 1910 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
  1911 + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1907 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) { 1912 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1908 if (loglevel != 0) { 1913 if (loglevel != 0) {
1909 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn); 1914 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1910 } 1915 }
1911 - raise_exception_err(env, POWERPC_EXCP_PROGRAM,  
1912 - POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); 1916 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
  1917 + POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1913 } 1918 }
1914 return val; 1919 return val;
1915 } 1920 }
@@ -1920,14 +1925,14 @@ void helper_store_dcr (target_ulong dcrn, target_ulong val) @@ -1920,14 +1925,14 @@ void helper_store_dcr (target_ulong dcrn, target_ulong val)
1920 if (loglevel != 0) { 1925 if (loglevel != 0) {
1921 fprintf(logfile, "No DCR environment\n"); 1926 fprintf(logfile, "No DCR environment\n");
1922 } 1927 }
1923 - raise_exception_err(env, POWERPC_EXCP_PROGRAM,  
1924 - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); 1928 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
  1929 + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1925 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) { 1930 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1926 if (loglevel != 0) { 1931 if (loglevel != 0) {
1927 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn); 1932 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1928 } 1933 }
1929 - raise_exception_err(env, POWERPC_EXCP_PROGRAM,  
1930 - POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); 1934 + helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
  1935 + POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1931 } 1936 }
1932 } 1937 }
1933 1938
@@ -2671,7 +2676,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) @@ -2671,7 +2676,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2671 cpu_restore_state(tb, env, pc, NULL); 2676 cpu_restore_state(tb, env, pc, NULL);
2672 } 2677 }
2673 } 2678 }
2674 - raise_exception_err(env, env->exception_index, env->error_code); 2679 + helper_raise_exception_err(env->exception_index, env->error_code);
2675 } 2680 }
2676 env = saved_env; 2681 env = saved_env;
2677 } 2682 }
target-ppc/translate.c
  View file @e06fcd7
@@ -264,49 +264,55 @@ static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) @@ -264,49 +264,55 @@ static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
264 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); 264 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
265 } 265 }
266 266
267 -#define GEN_EXCP(ctx, excp, error) \  
268 -do { \  
269 - TCGv_i32 t0 = tcg_const_i32(excp); \  
270 - TCGv_i32 t1 = tcg_const_i32(error); \  
271 - if ((ctx)->exception == POWERPC_EXCP_NONE) { \  
272 - gen_update_nip(ctx, (ctx)->nip); \  
273 - } \  
274 - gen_helper_raise_exception_err(t0, t1); \  
275 - tcg_temp_free_i32(t0); \  
276 - tcg_temp_free_i32(t1); \  
277 - ctx->exception = (excp); \  
278 -} while (0)  
279 -  
280 -#define GEN_EXCP_INVAL(ctx) \  
281 -GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \  
282 - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)  
283 -  
284 -#define GEN_EXCP_PRIVOPC(ctx) \  
285 -GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \  
286 - POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)  
287 -  
288 -#define GEN_EXCP_PRIVREG(ctx) \  
289 -GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \  
290 - POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG) 267 +static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
  268 +{
  269 + TCGv_i32 t0, t1;
  270 + if (ctx->exception == POWERPC_EXCP_NONE) {
  271 + gen_update_nip(ctx, ctx->nip);
  272 + }
  273 + t0 = tcg_const_i32(excp);
  274 + t1 = tcg_const_i32(error);
  275 + gen_helper_raise_exception_err(t0, t1);
  276 + tcg_temp_free_i32(t0);
  277 + tcg_temp_free_i32(t1);
  278 + ctx->exception = (excp);
  279 +}
291 280
292 -#define GEN_EXCP_NO_FP(ctx) \  
293 -GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0) 281 +static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
  282 +{
  283 + TCGv_i32 t0;
  284 + if (ctx->exception == POWERPC_EXCP_NONE) {
  285 + gen_update_nip(ctx, ctx->nip);
  286 + }
  287 + t0 = tcg_const_i32(excp);
  288 + gen_helper_raise_exception(t0);
  289 + tcg_temp_free_i32(t0);
  290 + ctx->exception = (excp);
  291 +}
294 292
295 -#define GEN_EXCP_NO_AP(ctx) \  
296 -GEN_EXCP(ctx, POWERPC_EXCP_APU, 0) 293 +static always_inline void gen_debug_exception (DisasContext *ctx)
  294 +{
  295 + TCGv_i32 t0;
  296 + gen_update_nip(ctx, ctx->nip);
  297 + t0 = tcg_const_i32(EXCP_DEBUG);
  298 + gen_helper_raise_exception(t0);
  299 + tcg_temp_free_i32(t0);
  300 +}
297 301
298 -#define GEN_EXCP_NO_VR(ctx) \  
299 -GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0) 302 +static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
  303 +{
  304 + gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
  305 +}
300 306
301 /* Stop translation */ 307 /* Stop translation */
302 -static always_inline void GEN_STOP (DisasContext *ctx) 308 +static always_inline void gen_stop_exception (DisasContext *ctx)
303 { 309 {
304 gen_update_nip(ctx, ctx->nip); 310 gen_update_nip(ctx, ctx->nip);
305 ctx->exception = POWERPC_EXCP_STOP; 311 ctx->exception = POWERPC_EXCP_STOP;
306 } 312 }
307 313
308 /* No need to update nip here, as execution flow will change */ 314 /* No need to update nip here, as execution flow will change */
309 -static always_inline void GEN_SYNC (DisasContext *ctx) 315 +static always_inline void gen_sync_exception (DisasContext *ctx)
310 { 316 {
311 ctx->exception = POWERPC_EXCP_SYNC; 317 ctx->exception = POWERPC_EXCP_SYNC;
312 } 318 }
@@ -689,7 +695,7 @@ GEN_OPCODE_MARK(start); @@ -689,7 +695,7 @@ GEN_OPCODE_MARK(start);
689 /* Invalid instruction */ 695 /* Invalid instruction */
690 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) 696 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
691 { 697 {
692 - GEN_EXCP_INVAL(ctx); 698 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
693 } 699 }
694 700
695 static opc_handler_t invalid_handler = { 701 static opc_handler_t invalid_handler = {
@@ -2083,7 +2089,7 @@ GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B) @@ -2083,7 +2089,7 @@ GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2083 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \ 2089 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2084 { \ 2090 { \
2085 if (unlikely(!ctx->fpu_enabled)) { \ 2091 if (unlikely(!ctx->fpu_enabled)) { \
2086 - GEN_EXCP_NO_FP(ctx); \ 2092 + gen_exception(ctx, POWERPC_EXCP_FPU); \
2087 return; \ 2093 return; \
2088 } \ 2094 } \
2089 gen_reset_fpstatus(); \ 2095 gen_reset_fpstatus(); \
@@ -2104,7 +2110,7 @@ _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); @@ -2104,7 +2110,7 @@ _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2104 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ 2110 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2105 { \ 2111 { \
2106 if (unlikely(!ctx->fpu_enabled)) { \ 2112 if (unlikely(!ctx->fpu_enabled)) { \
2107 - GEN_EXCP_NO_FP(ctx); \ 2113 + gen_exception(ctx, POWERPC_EXCP_FPU); \
2108 return; \ 2114 return; \
2109 } \ 2115 } \
2110 gen_reset_fpstatus(); \ 2116 gen_reset_fpstatus(); \
@@ -2124,7 +2130,7 @@ _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); @@ -2124,7 +2130,7 @@ _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2124 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ 2130 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2125 { \ 2131 { \
2126 if (unlikely(!ctx->fpu_enabled)) { \ 2132 if (unlikely(!ctx->fpu_enabled)) { \
2127 - GEN_EXCP_NO_FP(ctx); \ 2133 + gen_exception(ctx, POWERPC_EXCP_FPU); \
2128 return; \ 2134 return; \
2129 } \ 2135 } \
2130 gen_reset_fpstatus(); \ 2136 gen_reset_fpstatus(); \
@@ -2144,7 +2150,7 @@ _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); @@ -2144,7 +2150,7 @@ _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ 2150 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2145 { \ 2151 { \
2146 if (unlikely(!ctx->fpu_enabled)) { \ 2152 if (unlikely(!ctx->fpu_enabled)) { \
2147 - GEN_EXCP_NO_FP(ctx); \ 2153 + gen_exception(ctx, POWERPC_EXCP_FPU); \
2148 return; \ 2154 return; \
2149 } \ 2155 } \
2150 gen_reset_fpstatus(); \ 2156 gen_reset_fpstatus(); \
@@ -2157,7 +2163,7 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ @@ -2157,7 +2163,7 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2157 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \ 2163 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2158 { \ 2164 { \
2159 if (unlikely(!ctx->fpu_enabled)) { \ 2165 if (unlikely(!ctx->fpu_enabled)) { \
2160 - GEN_EXCP_NO_FP(ctx); \ 2166 + gen_exception(ctx, POWERPC_EXCP_FPU); \
2161 return; \ 2167 return; \
2162 } \ 2168 } \
2163 gen_reset_fpstatus(); \ 2169 gen_reset_fpstatus(); \
@@ -2186,7 +2192,7 @@ GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); @@ -2186,7 +2192,7 @@ GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2186 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES) 2192 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2187 { 2193 {
2188 if (unlikely(!ctx->fpu_enabled)) { 2194 if (unlikely(!ctx->fpu_enabled)) {
2189 - GEN_EXCP_NO_FP(ctx); 2195 + gen_exception(ctx, POWERPC_EXCP_FPU);
2190 return; 2196 return;
2191 } 2197 }
2192 gen_reset_fpstatus(); 2198 gen_reset_fpstatus();
@@ -2204,7 +2210,7 @@ GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); @@ -2204,7 +2210,7 @@ GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2204 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) 2210 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2205 { 2211 {
2206 if (unlikely(!ctx->fpu_enabled)) { 2212 if (unlikely(!ctx->fpu_enabled)) {
2207 - GEN_EXCP_NO_FP(ctx); 2213 + gen_exception(ctx, POWERPC_EXCP_FPU);
2208 return; 2214 return;
2209 } 2215 }
2210 gen_reset_fpstatus(); 2216 gen_reset_fpstatus();
@@ -2215,7 +2221,7 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) @@ -2215,7 +2221,7 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2215 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) 2221 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2216 { 2222 {
2217 if (unlikely(!ctx->fpu_enabled)) { 2223 if (unlikely(!ctx->fpu_enabled)) {
2218 - GEN_EXCP_NO_FP(ctx); 2224 + gen_exception(ctx, POWERPC_EXCP_FPU);
2219 return; 2225 return;
2220 } 2226 }
2221 gen_reset_fpstatus(); 2227 gen_reset_fpstatus();
@@ -2264,7 +2270,7 @@ GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); @@ -2264,7 +2270,7 @@ GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2264 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) 2270 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2265 { 2271 {
2266 if (unlikely(!ctx->fpu_enabled)) { 2272 if (unlikely(!ctx->fpu_enabled)) {
2267 - GEN_EXCP_NO_FP(ctx); 2273 + gen_exception(ctx, POWERPC_EXCP_FPU);
2268 return; 2274 return;
2269 } 2275 }
2270 gen_reset_fpstatus(); 2276 gen_reset_fpstatus();
@@ -2277,7 +2283,7 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) @@ -2277,7 +2283,7 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2277 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) 2283 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2278 { 2284 {
2279 if (unlikely(!ctx->fpu_enabled)) { 2285 if (unlikely(!ctx->fpu_enabled)) {
2280 - GEN_EXCP_NO_FP(ctx); 2286 + gen_exception(ctx, POWERPC_EXCP_FPU);
2281 return; 2287 return;
2282 } 2288 }
2283 gen_reset_fpstatus(); 2289 gen_reset_fpstatus();
@@ -2296,7 +2302,7 @@ GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); @@ -2296,7 +2302,7 @@ GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2296 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) 2302 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2297 { 2303 {
2298 if (unlikely(!ctx->fpu_enabled)) { 2304 if (unlikely(!ctx->fpu_enabled)) {
2299 - GEN_EXCP_NO_FP(ctx); 2305 + gen_exception(ctx, POWERPC_EXCP_FPU);
2300 return; 2306 return;
2301 } 2307 }
2302 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); 2308 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
@@ -2317,7 +2323,7 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) @@ -2317,7 +2323,7 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2317 int bfa; 2323 int bfa;
2318 2324
2319 if (unlikely(!ctx->fpu_enabled)) { 2325 if (unlikely(!ctx->fpu_enabled)) {
2320 - GEN_EXCP_NO_FP(ctx); 2326 + gen_exception(ctx, POWERPC_EXCP_FPU);
2321 return; 2327 return;
2322 } 2328 }
2323 gen_optimize_fprf(); 2329 gen_optimize_fprf();
@@ -2331,7 +2337,7 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) @@ -2331,7 +2337,7 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2331 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) 2337 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2332 { 2338 {
2333 if (unlikely(!ctx->fpu_enabled)) { 2339 if (unlikely(!ctx->fpu_enabled)) {
2334 - GEN_EXCP_NO_FP(ctx); 2340 + gen_exception(ctx, POWERPC_EXCP_FPU);
2335 return; 2341 return;
2336 } 2342 }
2337 gen_optimize_fprf(); 2343 gen_optimize_fprf();
@@ -2346,7 +2352,7 @@ GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) @@ -2346,7 +2352,7 @@ GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2346 uint8_t crb; 2352 uint8_t crb;
2347 2353
2348 if (unlikely(!ctx->fpu_enabled)) { 2354 if (unlikely(!ctx->fpu_enabled)) {
2349 - GEN_EXCP_NO_FP(ctx); 2355 + gen_exception(ctx, POWERPC_EXCP_FPU);
2350 return; 2356 return;
2351 } 2357 }
2352 crb = 32 - (crbD(ctx->opcode) >> 2); 2358 crb = 32 - (crbD(ctx->opcode) >> 2);
@@ -2365,7 +2371,7 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) @@ -2365,7 +2371,7 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2365 uint8_t crb; 2371 uint8_t crb;
2366 2372
2367 if (unlikely(!ctx->fpu_enabled)) { 2373 if (unlikely(!ctx->fpu_enabled)) {
2368 - GEN_EXCP_NO_FP(ctx); 2374 + gen_exception(ctx, POWERPC_EXCP_FPU);
2369 return; 2375 return;
2370 } 2376 }
2371 crb = 32 - (crbD(ctx->opcode) >> 2); 2377 crb = 32 - (crbD(ctx->opcode) >> 2);
@@ -2390,7 +2396,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) @@ -2390,7 +2396,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2390 TCGv_i32 t0; 2396 TCGv_i32 t0;
2391 2397
2392 if (unlikely(!ctx->fpu_enabled)) { 2398 if (unlikely(!ctx->fpu_enabled)) {
2393 - GEN_EXCP_NO_FP(ctx); 2399 + gen_exception(ctx, POWERPC_EXCP_FPU);
2394 return; 2400 return;
2395 } 2401 }
2396 gen_optimize_fprf(); 2402 gen_optimize_fprf();
@@ -2413,7 +2419,7 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) @@ -2413,7 +2419,7 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2413 TCGv_i32 t1; 2419 TCGv_i32 t1;
2414 2420
2415 if (unlikely(!ctx->fpu_enabled)) { 2421 if (unlikely(!ctx->fpu_enabled)) {
2416 - GEN_EXCP_NO_FP(ctx); 2422 + gen_exception(ctx, POWERPC_EXCP_FPU);
2417 return; 2423 return;
2418 } 2424 }
2419 bf = crbD(ctx->opcode) >> 2; 2425 bf = crbD(ctx->opcode) >> 2;
@@ -2698,7 +2704,7 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -2698,7 +2704,7 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2698 TCGv EA; \ 2704 TCGv EA; \
2699 if (unlikely(rA(ctx->opcode) == 0 || \ 2705 if (unlikely(rA(ctx->opcode) == 0 || \
2700 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2706 rA(ctx->opcode) == rD(ctx->opcode))) { \
2701 - GEN_EXCP_INVAL(ctx); \ 2707 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2702 return; \ 2708 return; \
2703 } \ 2709 } \
2704 gen_set_access_type(ctx, ACCESS_INT); \ 2710 gen_set_access_type(ctx, ACCESS_INT); \
@@ -2718,7 +2724,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -2718,7 +2724,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2718 TCGv EA; \ 2724 TCGv EA; \
2719 if (unlikely(rA(ctx->opcode) == 0 || \ 2725 if (unlikely(rA(ctx->opcode) == 0 || \
2720 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2726 rA(ctx->opcode) == rD(ctx->opcode))) { \
2721 - GEN_EXCP_INVAL(ctx); \ 2727 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2722 return; \ 2728 return; \
2723 } \ 2729 } \
2724 gen_set_access_type(ctx, ACCESS_INT); \ 2730 gen_set_access_type(ctx, ACCESS_INT); \
@@ -2769,7 +2775,7 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -2769,7 +2775,7 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2769 if (Rc(ctx->opcode)) { 2775 if (Rc(ctx->opcode)) {
2770 if (unlikely(rA(ctx->opcode) == 0 || 2776 if (unlikely(rA(ctx->opcode) == 0 ||
2771 rA(ctx->opcode) == rD(ctx->opcode))) { 2777 rA(ctx->opcode) == rD(ctx->opcode))) {
2772 - GEN_EXCP_INVAL(ctx); 2778 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2773 return; 2779 return;
2774 } 2780 }
2775 } 2781 }
@@ -2791,25 +2797,25 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -2791,25 +2797,25 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2791 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) 2797 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2792 { 2798 {
2793 #if defined(CONFIG_USER_ONLY) 2799 #if defined(CONFIG_USER_ONLY)
2794 - GEN_EXCP_PRIVOPC(ctx); 2800 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2795 #else 2801 #else
2796 int ra, rd; 2802 int ra, rd;
2797 TCGv EA; 2803 TCGv EA;
2798 2804
2799 /* Restore CPU state */ 2805 /* Restore CPU state */
2800 if (unlikely(ctx->mem_idx == 0)) { 2806 if (unlikely(ctx->mem_idx == 0)) {
2801 - GEN_EXCP_PRIVOPC(ctx); 2807 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2802 return; 2808 return;
2803 } 2809 }
2804 ra = rA(ctx->opcode); 2810 ra = rA(ctx->opcode);
2805 rd = rD(ctx->opcode); 2811 rd = rD(ctx->opcode);
2806 if (unlikely((rd & 1) || rd == ra)) { 2812 if (unlikely((rd & 1) || rd == ra)) {
2807 - GEN_EXCP_INVAL(ctx); 2813 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2808 return; 2814 return;
2809 } 2815 }
2810 if (unlikely(ctx->le_mode)) { 2816 if (unlikely(ctx->le_mode)) {
2811 /* Little-endian mode is not handled */ 2817 /* Little-endian mode is not handled */
2812 - GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); 2818 + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2813 return; 2819 return;
2814 } 2820 }
2815 gen_set_access_type(ctx, ACCESS_INT); 2821 gen_set_access_type(ctx, ACCESS_INT);
@@ -2840,7 +2846,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -2840,7 +2846,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2840 { \ 2846 { \
2841 TCGv EA; \ 2847 TCGv EA; \
2842 if (unlikely(rA(ctx->opcode) == 0)) { \ 2848 if (unlikely(rA(ctx->opcode) == 0)) { \
2843 - GEN_EXCP_INVAL(ctx); \ 2849 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2844 return; \ 2850 return; \
2845 } \ 2851 } \
2846 gen_set_access_type(ctx, ACCESS_INT); \ 2852 gen_set_access_type(ctx, ACCESS_INT); \
@@ -2859,7 +2865,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -2859,7 +2865,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2859 { \ 2865 { \
2860 TCGv EA; \ 2866 TCGv EA; \
2861 if (unlikely(rA(ctx->opcode) == 0)) { \ 2867 if (unlikely(rA(ctx->opcode) == 0)) { \
2862 - GEN_EXCP_INVAL(ctx); \ 2868 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2863 return; \ 2869 return; \
2864 } \ 2870 } \
2865 gen_set_access_type(ctx, ACCESS_INT); \ 2871 gen_set_access_type(ctx, ACCESS_INT); \
@@ -2904,20 +2910,20 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -2904,20 +2910,20 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2904 rs = rS(ctx->opcode); 2910 rs = rS(ctx->opcode);
2905 if ((ctx->opcode & 0x3) == 0x2) { 2911 if ((ctx->opcode & 0x3) == 0x2) {
2906 #if defined(CONFIG_USER_ONLY) 2912 #if defined(CONFIG_USER_ONLY)
2907 - GEN_EXCP_PRIVOPC(ctx); 2913 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2908 #else 2914 #else
2909 /* stq */ 2915 /* stq */
2910 if (unlikely(ctx->mem_idx == 0)) { 2916 if (unlikely(ctx->mem_idx == 0)) {
2911 - GEN_EXCP_PRIVOPC(ctx); 2917 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2912 return; 2918 return;
2913 } 2919 }
2914 if (unlikely(rs & 1)) { 2920 if (unlikely(rs & 1)) {
2915 - GEN_EXCP_INVAL(ctx); 2921 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2916 return; 2922 return;
2917 } 2923 }
2918 if (unlikely(ctx->le_mode)) { 2924 if (unlikely(ctx->le_mode)) {
2919 /* Little-endian mode is not handled */ 2925 /* Little-endian mode is not handled */
2920 - GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); 2926 + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2921 return; 2927 return;
2922 } 2928 }
2923 gen_set_access_type(ctx, ACCESS_INT); 2929 gen_set_access_type(ctx, ACCESS_INT);
@@ -2932,7 +2938,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -2932,7 +2938,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2932 /* std / stdu */ 2938 /* std / stdu */
2933 if (Rc(ctx->opcode)) { 2939 if (Rc(ctx->opcode)) {
2934 if (unlikely(rA(ctx->opcode) == 0)) { 2940 if (unlikely(rA(ctx->opcode) == 0)) {
2935 - GEN_EXCP_INVAL(ctx); 2941 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2936 return; 2942 return;
2937 } 2943 }
2938 } 2944 }
@@ -3094,8 +3100,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) @@ -3094,8 +3100,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3094 if (unlikely(((start + nr) > 32 && 3100 if (unlikely(((start + nr) > 32 &&
3095 start <= ra && (start + nr - 32) > ra) || 3101 start <= ra && (start + nr - 32) > ra) ||
3096 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { 3102 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3097 - GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,  
3098 - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX); 3103 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3099 return; 3104 return;
3100 } 3105 }
3101 gen_set_access_type(ctx, ACCESS_INT); 3106 gen_set_access_type(ctx, ACCESS_INT);
@@ -3181,7 +3186,7 @@ GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO) @@ -3181,7 +3186,7 @@ GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3181 /* isync */ 3186 /* isync */
3182 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM) 3187 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3183 { 3188 {
3184 - GEN_STOP(ctx); 3189 + gen_stop_exception(ctx);
3185 } 3190 }
3186 3191
3187 /* lwarx */ 3192 /* lwarx */
@@ -3266,7 +3271,7 @@ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT) @@ -3266,7 +3271,7 @@ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3266 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); 3271 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3267 tcg_temp_free_i32(t0); 3272 tcg_temp_free_i32(t0);
3268 /* Stop translation, as the CPU is supposed to sleep from now */ 3273 /* Stop translation, as the CPU is supposed to sleep from now */
3269 - GEN_EXCP(ctx, EXCP_HLT, 1); 3274 + gen_exception_err(ctx, EXCP_HLT, 1);
3270 } 3275 }
3271 3276
3272 /*** Floating-point load ***/ 3277 /*** Floating-point load ***/
@@ -3275,7 +3280,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3275,7 +3280,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3275 { \ 3280 { \
3276 TCGv EA; \ 3281 TCGv EA; \
3277 if (unlikely(!ctx->fpu_enabled)) { \ 3282 if (unlikely(!ctx->fpu_enabled)) { \
3278 - GEN_EXCP_NO_FP(ctx); \ 3283 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3279 return; \ 3284 return; \
3280 } \ 3285 } \
3281 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3286 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3290,11 +3295,11 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3290,11 +3295,11 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3290 { \ 3295 { \
3291 TCGv EA; \ 3296 TCGv EA; \
3292 if (unlikely(!ctx->fpu_enabled)) { \ 3297 if (unlikely(!ctx->fpu_enabled)) { \
3293 - GEN_EXCP_NO_FP(ctx); \ 3298 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3294 return; \ 3299 return; \
3295 } \ 3300 } \
3296 if (unlikely(rA(ctx->opcode) == 0)) { \ 3301 if (unlikely(rA(ctx->opcode) == 0)) { \
3297 - GEN_EXCP_INVAL(ctx); \ 3302 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3298 return; \ 3303 return; \
3299 } \ 3304 } \
3300 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3305 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3310,11 +3315,11 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \ @@ -3310,11 +3315,11 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3310 { \ 3315 { \
3311 TCGv EA; \ 3316 TCGv EA; \
3312 if (unlikely(!ctx->fpu_enabled)) { \ 3317 if (unlikely(!ctx->fpu_enabled)) { \
3313 - GEN_EXCP_NO_FP(ctx); \ 3318 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3314 return; \ 3319 return; \
3315 } \ 3320 } \
3316 if (unlikely(rA(ctx->opcode) == 0)) { \ 3321 if (unlikely(rA(ctx->opcode) == 0)) { \
3317 - GEN_EXCP_INVAL(ctx); \ 3322 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3318 return; \ 3323 return; \
3319 } \ 3324 } \
3320 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3325 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3330,7 +3335,7 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -3330,7 +3335,7 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3330 { \ 3335 { \
3331 TCGv EA; \ 3336 TCGv EA; \
3332 if (unlikely(!ctx->fpu_enabled)) { \ 3337 if (unlikely(!ctx->fpu_enabled)) { \
3333 - GEN_EXCP_NO_FP(ctx); \ 3338 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3334 return; \ 3339 return; \
3335 } \ 3340 } \
3336 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3341 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3368,7 +3373,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3368,7 +3373,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3368 { \ 3373 { \
3369 TCGv EA; \ 3374 TCGv EA; \
3370 if (unlikely(!ctx->fpu_enabled)) { \ 3375 if (unlikely(!ctx->fpu_enabled)) { \
3371 - GEN_EXCP_NO_FP(ctx); \ 3376 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3372 return; \ 3377 return; \
3373 } \ 3378 } \
3374 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3379 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3383,11 +3388,11 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3383,11 +3388,11 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3383 { \ 3388 { \
3384 TCGv EA; \ 3389 TCGv EA; \
3385 if (unlikely(!ctx->fpu_enabled)) { \ 3390 if (unlikely(!ctx->fpu_enabled)) { \
3386 - GEN_EXCP_NO_FP(ctx); \ 3391 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3387 return; \ 3392 return; \
3388 } \ 3393 } \
3389 if (unlikely(rA(ctx->opcode) == 0)) { \ 3394 if (unlikely(rA(ctx->opcode) == 0)) { \
3390 - GEN_EXCP_INVAL(ctx); \ 3395 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3391 return; \ 3396 return; \
3392 } \ 3397 } \
3393 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3398 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3403,11 +3408,11 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \ @@ -3403,11 +3408,11 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3403 { \ 3408 { \
3404 TCGv EA; \ 3409 TCGv EA; \
3405 if (unlikely(!ctx->fpu_enabled)) { \ 3410 if (unlikely(!ctx->fpu_enabled)) { \
3406 - GEN_EXCP_NO_FP(ctx); \ 3411 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3407 return; \ 3412 return; \
3408 } \ 3413 } \
3409 if (unlikely(rA(ctx->opcode) == 0)) { \ 3414 if (unlikely(rA(ctx->opcode) == 0)) { \
3410 - GEN_EXCP_INVAL(ctx); \ 3415 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3411 return; \ 3416 return; \
3412 } \ 3417 } \
3413 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3418 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3423,7 +3428,7 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -3423,7 +3428,7 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3423 { \ 3428 { \
3424 TCGv EA; \ 3429 TCGv EA; \
3425 if (unlikely(!ctx->fpu_enabled)) { \ 3430 if (unlikely(!ctx->fpu_enabled)) { \
3426 - GEN_EXCP_NO_FP(ctx); \ 3431 + gen_exception(ctx, POWERPC_EXCP_FPU); \
3427 return; \ 3432 return; \
3428 } \ 3433 } \
3429 gen_set_access_type(ctx, ACCESS_FLOAT); \ 3434 gen_set_access_type(ctx, ACCESS_FLOAT); \
@@ -3489,12 +3494,11 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n, @@ -3489,12 +3494,11 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3489 ctx->exception == POWERPC_EXCP_BRANCH) { 3494 ctx->exception == POWERPC_EXCP_BRANCH) {
3490 target_ulong tmp = ctx->nip; 3495 target_ulong tmp = ctx->nip;
3491 ctx->nip = dest; 3496 ctx->nip = dest;
3492 - GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0); 3497 + gen_exception(ctx, POWERPC_EXCP_TRACE);
3493 ctx->nip = tmp; 3498 ctx->nip = tmp;
3494 } 3499 }
3495 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3500 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3496 - gen_update_nip(ctx, dest);  
3497 - gen_helper_raise_debug(); 3501 + gen_debug_exception(ctx);
3498 } 3502 }
3499 } 3503 }
3500 tcg_gen_exit_tb(0); 3504 tcg_gen_exit_tb(0);
@@ -3558,7 +3562,7 @@ static always_inline void gen_bcond (DisasContext *ctx, int type) @@ -3558,7 +3562,7 @@ static always_inline void gen_bcond (DisasContext *ctx, int type)
3558 /* Decrement and test CTR */ 3562 /* Decrement and test CTR */
3559 TCGv temp = tcg_temp_new(); 3563 TCGv temp = tcg_temp_new();
3560 if (unlikely(type == BCOND_CTR)) { 3564 if (unlikely(type == BCOND_CTR)) {
3561 - GEN_EXCP_INVAL(ctx); 3565 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3562 return; 3566 return;
3563 } 3567 }
3564 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3568 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
@@ -3692,15 +3696,15 @@ GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) @@ -3692,15 +3696,15 @@ GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3692 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW) 3696 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3693 { 3697 {
3694 #if defined(CONFIG_USER_ONLY) 3698 #if defined(CONFIG_USER_ONLY)
3695 - GEN_EXCP_PRIVOPC(ctx); 3699 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3696 #else 3700 #else
3697 /* Restore CPU state */ 3701 /* Restore CPU state */
3698 if (unlikely(!ctx->mem_idx)) { 3702 if (unlikely(!ctx->mem_idx)) {
3699 - GEN_EXCP_PRIVOPC(ctx); 3703 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3700 return; 3704 return;
3701 } 3705 }
3702 gen_helper_rfi(); 3706 gen_helper_rfi();
3703 - GEN_SYNC(ctx); 3707 + gen_sync_exception(ctx);
3704 #endif 3708 #endif
3705 } 3709 }
3706 3710
@@ -3708,30 +3712,30 @@ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW) @@ -3708,30 +3712,30 @@ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3708 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B) 3712 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3709 { 3713 {
3710 #if defined(CONFIG_USER_ONLY) 3714 #if defined(CONFIG_USER_ONLY)
3711 - GEN_EXCP_PRIVOPC(ctx); 3715 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3712 #else 3716 #else
3713 /* Restore CPU state */ 3717 /* Restore CPU state */
3714 if (unlikely(!ctx->mem_idx)) { 3718 if (unlikely(!ctx->mem_idx)) {
3715 - GEN_EXCP_PRIVOPC(ctx); 3719 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3716 return; 3720 return;
3717 } 3721 }
3718 gen_helper_rfid(); 3722 gen_helper_rfid();
3719 - GEN_SYNC(ctx); 3723 + gen_sync_exception(ctx);
3720 #endif 3724 #endif
3721 } 3725 }
3722 3726
3723 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H) 3727 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3724 { 3728 {
3725 #if defined(CONFIG_USER_ONLY) 3729 #if defined(CONFIG_USER_ONLY)
3726 - GEN_EXCP_PRIVOPC(ctx); 3730 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3727 #else 3731 #else
3728 /* Restore CPU state */ 3732 /* Restore CPU state */
3729 if (unlikely(ctx->mem_idx <= 1)) { 3733 if (unlikely(ctx->mem_idx <= 1)) {
3730 - GEN_EXCP_PRIVOPC(ctx); 3734 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3731 return; 3735 return;
3732 } 3736 }
3733 gen_helper_hrfid(); 3737 gen_helper_hrfid();
3734 - GEN_SYNC(ctx); 3738 + gen_sync_exception(ctx);
3735 #endif 3739 #endif
3736 } 3740 }
3737 #endif 3741 #endif
@@ -3747,7 +3751,7 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) @@ -3747,7 +3751,7 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3747 uint32_t lev; 3751 uint32_t lev;
3748 3752
3749 lev = (ctx->opcode >> 5) & 0x7F; 3753 lev = (ctx->opcode >> 5) & 0x7F;
3750 - GEN_EXCP(ctx, POWERPC_SYSCALL, lev); 3754 + gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3751 } 3755 }
3752 3756
3753 /*** Trap ***/ 3757 /*** Trap ***/
@@ -3826,10 +3830,10 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) @@ -3826,10 +3830,10 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3826 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) 3830 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3827 { 3831 {
3828 #if defined(CONFIG_USER_ONLY) 3832 #if defined(CONFIG_USER_ONLY)
3829 - GEN_EXCP_PRIVREG(ctx); 3833 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3830 #else 3834 #else
3831 if (unlikely(!ctx->mem_idx)) { 3835 if (unlikely(!ctx->mem_idx)) {
3832 - GEN_EXCP_PRIVREG(ctx); 3836 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3833 return; 3837 return;
3834 } 3838 }
3835 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3839 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
@@ -3878,7 +3882,7 @@ static always_inline void gen_op_mfspr (DisasContext *ctx) @@ -3878,7 +3882,7 @@ static always_inline void gen_op_mfspr (DisasContext *ctx)
3878 printf("Trying to read privileged spr %d %03x at " ADDRX "\n", 3882 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3879 sprn, sprn, ctx->nip); 3883 sprn, sprn, ctx->nip);
3880 } 3884 }
3881 - GEN_EXCP_PRIVREG(ctx); 3885 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3882 } 3886 }
3883 } else { 3887 } else {
3884 /* Not defined */ 3888 /* Not defined */
@@ -3888,8 +3892,7 @@ static always_inline void gen_op_mfspr (DisasContext *ctx) @@ -3888,8 +3892,7 @@ static always_inline void gen_op_mfspr (DisasContext *ctx)
3888 } 3892 }
3889 printf("Trying to read invalid spr %d %03x at " ADDRX "\n", 3893 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3890 sprn, sprn, ctx->nip); 3894 sprn, sprn, ctx->nip);
3891 - GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,  
3892 - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); 3895 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3893 } 3896 }
3894 } 3897 }
3895 3898
@@ -3929,10 +3932,10 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) @@ -3929,10 +3932,10 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3929 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) 3932 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3930 { 3933 {
3931 #if defined(CONFIG_USER_ONLY) 3934 #if defined(CONFIG_USER_ONLY)
3932 - GEN_EXCP_PRIVREG(ctx); 3935 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3933 #else 3936 #else
3934 if (unlikely(!ctx->mem_idx)) { 3937 if (unlikely(!ctx->mem_idx)) {
3935 - GEN_EXCP_PRIVREG(ctx); 3938 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3936 return; 3939 return;
3937 } 3940 }
3938 if (ctx->opcode & 0x00010000) { 3941 if (ctx->opcode & 0x00010000) {
@@ -3951,7 +3954,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) @@ -3951,7 +3954,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3951 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); 3954 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3952 /* Must stop the translation as machine state (may have) changed */ 3955 /* Must stop the translation as machine state (may have) changed */
3953 /* Note that mtmsr is not always defined as context-synchronizing */ 3956 /* Note that mtmsr is not always defined as context-synchronizing */
3954 - ctx->exception = POWERPC_EXCP_STOP; 3957 + gen_stop_exception(ctx);
3955 } 3958 }
3956 #endif 3959 #endif
3957 } 3960 }
@@ -3960,10 +3963,10 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) @@ -3960,10 +3963,10 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3960 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) 3963 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3961 { 3964 {
3962 #if defined(CONFIG_USER_ONLY) 3965 #if defined(CONFIG_USER_ONLY)
3963 - GEN_EXCP_PRIVREG(ctx); 3966 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3964 #else 3967 #else
3965 if (unlikely(!ctx->mem_idx)) { 3968 if (unlikely(!ctx->mem_idx)) {
3966 - GEN_EXCP_PRIVREG(ctx); 3969 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3967 return; 3970 return;
3968 } 3971 }
3969 if (ctx->opcode & 0x00010000) { 3972 if (ctx->opcode & 0x00010000) {
@@ -3994,7 +3997,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) @@ -3994,7 +3997,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3994 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); 3997 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3995 /* Must stop the translation as machine state (may have) changed */ 3998 /* Must stop the translation as machine state (may have) changed */
3996 /* Note that mtmsr is not always defined as context-synchronizing */ 3999 /* Note that mtmsr is not always defined as context-synchronizing */
3997 - ctx->exception = POWERPC_EXCP_STOP; 4000 + gen_stop_exception(ctx);
3998 } 4001 }
3999 #endif 4002 #endif
4000 } 4003 }
@@ -4024,7 +4027,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) @@ -4024,7 +4027,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4024 } 4027 }
4025 printf("Trying to write privileged spr %d %03x at " ADDRX "\n", 4028 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4026 sprn, sprn, ctx->nip); 4029 sprn, sprn, ctx->nip);
4027 - GEN_EXCP_PRIVREG(ctx); 4030 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4028 } 4031 }
4029 } else { 4032 } else {
4030 /* Not defined */ 4033 /* Not defined */
@@ -4034,8 +4037,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) @@ -4034,8 +4037,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4034 } 4037 }
4035 printf("Trying to write invalid spr %d %03x at " ADDRX "\n", 4038 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4036 sprn, sprn, ctx->nip); 4039 sprn, sprn, ctx->nip);
4037 - GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,  
4038 - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); 4040 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4039 } 4041 }
4040 } 4042 }
4041 4043
@@ -4056,11 +4058,11 @@ GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) @@ -4056,11 +4058,11 @@ GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4056 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) 4058 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4057 { 4059 {
4058 #if defined(CONFIG_USER_ONLY) 4060 #if defined(CONFIG_USER_ONLY)
4059 - GEN_EXCP_PRIVOPC(ctx); 4061 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4060 #else 4062 #else
4061 TCGv EA, val; 4063 TCGv EA, val;
4062 if (unlikely(!ctx->mem_idx)) { 4064 if (unlikely(!ctx->mem_idx)) {
4063 - GEN_EXCP_PRIVOPC(ctx); 4065 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4064 return; 4066 return;
4065 } 4067 }
4066 EA = tcg_temp_new(); 4068 EA = tcg_temp_new();
@@ -4162,11 +4164,11 @@ GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA) @@ -4162,11 +4164,11 @@ GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4162 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) 4164 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4163 { 4165 {
4164 #if defined(CONFIG_USER_ONLY) 4166 #if defined(CONFIG_USER_ONLY)
4165 - GEN_EXCP_PRIVREG(ctx); 4167 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4166 #else 4168 #else
4167 TCGv t0; 4169 TCGv t0;
4168 if (unlikely(!ctx->mem_idx)) { 4170 if (unlikely(!ctx->mem_idx)) {
4169 - GEN_EXCP_PRIVREG(ctx); 4171 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4170 return; 4172 return;
4171 } 4173 }
4172 t0 = tcg_const_tl(SR(ctx->opcode)); 4174 t0 = tcg_const_tl(SR(ctx->opcode));
@@ -4179,11 +4181,11 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) @@ -4179,11 +4181,11 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4179 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) 4181 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4180 { 4182 {
4181 #if defined(CONFIG_USER_ONLY) 4183 #if defined(CONFIG_USER_ONLY)
4182 - GEN_EXCP_PRIVREG(ctx); 4184 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4183 #else 4185 #else
4184 TCGv t0; 4186 TCGv t0;
4185 if (unlikely(!ctx->mem_idx)) { 4187 if (unlikely(!ctx->mem_idx)) {
4186 - GEN_EXCP_PRIVREG(ctx); 4188 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4187 return; 4189 return;
4188 } 4190 }
4189 t0 = tcg_temp_new(); 4191 t0 = tcg_temp_new();
@@ -4198,11 +4200,11 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) @@ -4198,11 +4200,11 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4198 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) 4200 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4199 { 4201 {
4200 #if defined(CONFIG_USER_ONLY) 4202 #if defined(CONFIG_USER_ONLY)
4201 - GEN_EXCP_PRIVREG(ctx); 4203 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202 #else 4204 #else
4203 TCGv t0; 4205 TCGv t0;
4204 if (unlikely(!ctx->mem_idx)) { 4206 if (unlikely(!ctx->mem_idx)) {
4205 - GEN_EXCP_PRIVREG(ctx); 4207 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4206 return; 4208 return;
4207 } 4209 }
4208 t0 = tcg_const_tl(SR(ctx->opcode)); 4210 t0 = tcg_const_tl(SR(ctx->opcode));
@@ -4215,11 +4217,11 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) @@ -4215,11 +4217,11 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4215 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) 4217 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4216 { 4218 {
4217 #if defined(CONFIG_USER_ONLY) 4219 #if defined(CONFIG_USER_ONLY)
4218 - GEN_EXCP_PRIVREG(ctx); 4220 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4219 #else 4221 #else
4220 TCGv t0; 4222 TCGv t0;
4221 if (unlikely(!ctx->mem_idx)) { 4223 if (unlikely(!ctx->mem_idx)) {
4222 - GEN_EXCP_PRIVREG(ctx); 4224 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4223 return; 4225 return;
4224 } 4226 }
4225 t0 = tcg_temp_new(); 4227 t0 = tcg_temp_new();
@@ -4236,11 +4238,11 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) @@ -4236,11 +4238,11 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4236 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) 4238 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4237 { 4239 {
4238 #if defined(CONFIG_USER_ONLY) 4240 #if defined(CONFIG_USER_ONLY)
4239 - GEN_EXCP_PRIVREG(ctx); 4241 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4240 #else 4242 #else
4241 TCGv t0; 4243 TCGv t0;
4242 if (unlikely(!ctx->mem_idx)) { 4244 if (unlikely(!ctx->mem_idx)) {
4243 - GEN_EXCP_PRIVREG(ctx); 4245 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4244 return; 4246 return;
4245 } 4247 }
4246 t0 = tcg_const_tl(SR(ctx->opcode)); 4248 t0 = tcg_const_tl(SR(ctx->opcode));
@@ -4254,11 +4256,11 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001, @@ -4254,11 +4256,11 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001,
4254 PPC_SEGMENT_64B) 4256 PPC_SEGMENT_64B)
4255 { 4257 {
4256 #if defined(CONFIG_USER_ONLY) 4258 #if defined(CONFIG_USER_ONLY)
4257 - GEN_EXCP_PRIVREG(ctx); 4259 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4258 #else 4260 #else
4259 TCGv t0; 4261 TCGv t0;
4260 if (unlikely(!ctx->mem_idx)) { 4262 if (unlikely(!ctx->mem_idx)) {
4261 - GEN_EXCP_PRIVREG(ctx); 4263 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4262 return; 4264 return;
4263 } 4265 }
4264 t0 = tcg_temp_new(); 4266 t0 = tcg_temp_new();
@@ -4273,11 +4275,11 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001, @@ -4273,11 +4275,11 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001,
4273 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) 4275 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4274 { 4276 {
4275 #if defined(CONFIG_USER_ONLY) 4277 #if defined(CONFIG_USER_ONLY)
4276 - GEN_EXCP_PRIVREG(ctx); 4278 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4277 #else 4279 #else
4278 TCGv t0; 4280 TCGv t0;
4279 if (unlikely(!ctx->mem_idx)) { 4281 if (unlikely(!ctx->mem_idx)) {
4280 - GEN_EXCP_PRIVREG(ctx); 4282 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4281 return; 4283 return;
4282 } 4284 }
4283 t0 = tcg_const_tl(SR(ctx->opcode)); 4285 t0 = tcg_const_tl(SR(ctx->opcode));
@@ -4291,11 +4293,11 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001, @@ -4291,11 +4293,11 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001,
4291 PPC_SEGMENT_64B) 4293 PPC_SEGMENT_64B)
4292 { 4294 {
4293 #if defined(CONFIG_USER_ONLY) 4295 #if defined(CONFIG_USER_ONLY)
4294 - GEN_EXCP_PRIVREG(ctx); 4296 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4295 #else 4297 #else
4296 TCGv t0; 4298 TCGv t0;
4297 if (unlikely(!ctx->mem_idx)) { 4299 if (unlikely(!ctx->mem_idx)) {
4298 - GEN_EXCP_PRIVREG(ctx); 4300 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4299 return; 4301 return;
4300 } 4302 }
4301 t0 = tcg_temp_new(); 4303 t0 = tcg_temp_new();
@@ -4313,10 +4315,10 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001, @@ -4313,10 +4315,10 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001,
4313 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA) 4315 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4314 { 4316 {
4315 #if defined(CONFIG_USER_ONLY) 4317 #if defined(CONFIG_USER_ONLY)
4316 - GEN_EXCP_PRIVOPC(ctx); 4318 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4317 #else 4319 #else
4318 if (unlikely(!ctx->mem_idx)) { 4320 if (unlikely(!ctx->mem_idx)) {
4319 - GEN_EXCP_PRIVOPC(ctx); 4321 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4320 return; 4322 return;
4321 } 4323 }
4322 gen_helper_tlbia(); 4324 gen_helper_tlbia();
@@ -4327,10 +4329,10 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA) @@ -4327,10 +4329,10 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4327 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) 4329 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4328 { 4330 {
4329 #if defined(CONFIG_USER_ONLY) 4331 #if defined(CONFIG_USER_ONLY)
4330 - GEN_EXCP_PRIVOPC(ctx); 4332 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4331 #else 4333 #else
4332 if (unlikely(!ctx->mem_idx)) { 4334 if (unlikely(!ctx->mem_idx)) {
4333 - GEN_EXCP_PRIVOPC(ctx); 4335 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4334 return; 4336 return;
4335 } 4337 }
4336 #if defined(TARGET_PPC64) 4338 #if defined(TARGET_PPC64)
@@ -4349,16 +4351,16 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) @@ -4349,16 +4351,16 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4349 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC) 4351 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4350 { 4352 {
4351 #if defined(CONFIG_USER_ONLY) 4353 #if defined(CONFIG_USER_ONLY)
4352 - GEN_EXCP_PRIVOPC(ctx); 4354 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4353 #else 4355 #else
4354 if (unlikely(!ctx->mem_idx)) { 4356 if (unlikely(!ctx->mem_idx)) {
4355 - GEN_EXCP_PRIVOPC(ctx); 4357 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4356 return; 4358 return;
4357 } 4359 }
4358 /* This has no effect: it should ensure that all previous 4360 /* This has no effect: it should ensure that all previous
4359 * tlbie have completed 4361 * tlbie have completed
4360 */ 4362 */
4361 - GEN_STOP(ctx); 4363 + gen_stop_exception(ctx);
4362 #endif 4364 #endif
4363 } 4365 }
4364 4366
@@ -4367,10 +4369,10 @@ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC) @@ -4367,10 +4369,10 @@ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4367 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI) 4369 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4368 { 4370 {
4369 #if defined(CONFIG_USER_ONLY) 4371 #if defined(CONFIG_USER_ONLY)
4370 - GEN_EXCP_PRIVOPC(ctx); 4372 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4371 #else 4373 #else
4372 if (unlikely(!ctx->mem_idx)) { 4374 if (unlikely(!ctx->mem_idx)) {
4373 - GEN_EXCP_PRIVOPC(ctx); 4375 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4374 return; 4376 return;
4375 } 4377 }
4376 gen_helper_slbia(); 4378 gen_helper_slbia();
@@ -4381,10 +4383,10 @@ GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI) @@ -4381,10 +4383,10 @@ GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4381 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) 4383 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4382 { 4384 {
4383 #if defined(CONFIG_USER_ONLY) 4385 #if defined(CONFIG_USER_ONLY)
4384 - GEN_EXCP_PRIVOPC(ctx); 4386 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4385 #else 4387 #else
4386 if (unlikely(!ctx->mem_idx)) { 4388 if (unlikely(!ctx->mem_idx)) {
4387 - GEN_EXCP_PRIVOPC(ctx); 4389 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4388 return; 4390 return;
4389 } 4391 }
4390 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); 4392 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
@@ -5065,24 +5067,24 @@ GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) @@ -5065,24 +5067,24 @@ GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5065 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC) 5067 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5066 { 5068 {
5067 /* XXX: TODO */ 5069 /* XXX: TODO */
5068 - GEN_EXCP_INVAL(ctx); 5070 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5069 } 5071 }
5070 5072
5071 /* esa */ 5073 /* esa */
5072 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC) 5074 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5073 { 5075 {
5074 /* XXX: TODO */ 5076 /* XXX: TODO */
5075 - GEN_EXCP_INVAL(ctx); 5077 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5076 } 5078 }
5077 5079
5078 /* mfrom */ 5080 /* mfrom */
5079 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) 5081 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5080 { 5082 {
5081 #if defined(CONFIG_USER_ONLY) 5083 #if defined(CONFIG_USER_ONLY)
5082 - GEN_EXCP_PRIVOPC(ctx); 5084 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5083 #else 5085 #else
5084 if (unlikely(!ctx->mem_idx)) { 5086 if (unlikely(!ctx->mem_idx)) {
5085 - GEN_EXCP_PRIVOPC(ctx); 5087 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5086 return; 5088 return;
5087 } 5089 }
5088 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5090 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
@@ -5094,10 +5096,10 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) @@ -5094,10 +5096,10 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5094 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) 5096 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5095 { 5097 {
5096 #if defined(CONFIG_USER_ONLY) 5098 #if defined(CONFIG_USER_ONLY)
5097 - GEN_EXCP_PRIVOPC(ctx); 5099 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5098 #else 5100 #else
5099 if (unlikely(!ctx->mem_idx)) { 5101 if (unlikely(!ctx->mem_idx)) {
5100 - GEN_EXCP_PRIVOPC(ctx); 5102 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5101 return; 5103 return;
5102 } 5104 }
5103 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); 5105 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
@@ -5108,10 +5110,10 @@ GEN_HANDLER2(tlbld_6xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) @@ -5108,10 +5110,10 @@ GEN_HANDLER2(tlbld_6xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5108 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) 5110 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5109 { 5111 {
5110 #if defined(CONFIG_USER_ONLY) 5112 #if defined(CONFIG_USER_ONLY)
5111 - GEN_EXCP_PRIVOPC(ctx); 5113 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5112 #else 5114 #else
5113 if (unlikely(!ctx->mem_idx)) { 5115 if (unlikely(!ctx->mem_idx)) {
5114 - GEN_EXCP_PRIVOPC(ctx); 5116 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5115 return; 5117 return;
5116 } 5118 }
5117 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); 5119 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
@@ -5123,10 +5125,10 @@ GEN_HANDLER2(tlbli_6xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) @@ -5123,10 +5125,10 @@ GEN_HANDLER2(tlbli_6xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5123 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) 5125 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5124 { 5126 {
5125 #if defined(CONFIG_USER_ONLY) 5127 #if defined(CONFIG_USER_ONLY)
5126 - GEN_EXCP_PRIVOPC(ctx); 5128 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5127 #else 5129 #else
5128 if (unlikely(!ctx->mem_idx)) { 5130 if (unlikely(!ctx->mem_idx)) {
5129 - GEN_EXCP_PRIVOPC(ctx); 5131 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5130 return; 5132 return;
5131 } 5133 }
5132 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); 5134 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
@@ -5137,10 +5139,10 @@ GEN_HANDLER2(tlbld_74xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) @@ -5137,10 +5139,10 @@ GEN_HANDLER2(tlbld_74xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5137 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) 5139 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5138 { 5140 {
5139 #if defined(CONFIG_USER_ONLY) 5141 #if defined(CONFIG_USER_ONLY)
5140 - GEN_EXCP_PRIVOPC(ctx); 5142 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5141 #else 5143 #else
5142 if (unlikely(!ctx->mem_idx)) { 5144 if (unlikely(!ctx->mem_idx)) {
5143 - GEN_EXCP_PRIVOPC(ctx); 5145 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5144 return; 5146 return;
5145 } 5147 }
5146 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); 5148 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
@@ -5159,10 +5161,10 @@ GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER) @@ -5159,10 +5161,10 @@ GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5159 { 5161 {
5160 /* Cache line invalidate: privileged and treated as no-op */ 5162 /* Cache line invalidate: privileged and treated as no-op */
5161 #if defined(CONFIG_USER_ONLY) 5163 #if defined(CONFIG_USER_ONLY)
5162 - GEN_EXCP_PRIVOPC(ctx); 5164 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5163 #else 5165 #else
5164 if (unlikely(!ctx->mem_idx)) { 5166 if (unlikely(!ctx->mem_idx)) {
5165 - GEN_EXCP_PRIVOPC(ctx); 5167 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5166 return; 5168 return;
5167 } 5169 }
5168 #endif 5170 #endif
@@ -5177,13 +5179,13 @@ GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER) @@ -5177,13 +5179,13 @@ GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5177 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) 5179 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5178 { 5180 {
5179 #if defined(CONFIG_USER_ONLY) 5181 #if defined(CONFIG_USER_ONLY)
5180 - GEN_EXCP_PRIVOPC(ctx); 5182 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5181 #else 5183 #else
5182 int ra = rA(ctx->opcode); 5184 int ra = rA(ctx->opcode);
5183 int rd = rD(ctx->opcode); 5185 int rd = rD(ctx->opcode);
5184 TCGv t0; 5186 TCGv t0;
5185 if (unlikely(!ctx->mem_idx)) { 5187 if (unlikely(!ctx->mem_idx)) {
5186 - GEN_EXCP_PRIVOPC(ctx); 5188 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5187 return; 5189 return;
5188 } 5190 }
5189 t0 = tcg_temp_new(); 5191 t0 = tcg_temp_new();
@@ -5200,11 +5202,11 @@ GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) @@ -5200,11 +5202,11 @@ GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5200 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) 5202 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5201 { 5203 {
5202 #if defined(CONFIG_USER_ONLY) 5204 #if defined(CONFIG_USER_ONLY)
5203 - GEN_EXCP_PRIVOPC(ctx); 5205 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5204 #else 5206 #else
5205 TCGv t0; 5207 TCGv t0;
5206 if (unlikely(!ctx->mem_idx)) { 5208 if (unlikely(!ctx->mem_idx)) {
5207 - GEN_EXCP_PRIVOPC(ctx); 5209 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5208 return; 5210 return;
5209 } 5211 }
5210 t0 = tcg_temp_new(); 5212 t0 = tcg_temp_new();
@@ -5217,14 +5219,14 @@ GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) @@ -5217,14 +5219,14 @@ GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5217 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER) 5219 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5218 { 5220 {
5219 #if defined(CONFIG_USER_ONLY) 5221 #if defined(CONFIG_USER_ONLY)
5220 - GEN_EXCP_PRIVOPC(ctx); 5222 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5221 #else 5223 #else
5222 if (unlikely(!ctx->mem_idx)) { 5224 if (unlikely(!ctx->mem_idx)) {
5223 - GEN_EXCP_PRIVOPC(ctx); 5225 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5224 return; 5226 return;
5225 } 5227 }
5226 gen_helper_rfsvc(); 5228 gen_helper_rfsvc();
5227 - GEN_SYNC(ctx); 5229 + gen_sync_exception(ctx);
5228 #endif 5230 #endif
5229 } 5231 }
5230 5232
@@ -5370,18 +5372,18 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) @@ -5370,18 +5372,18 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5370 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI) 5372 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5371 { 5373 {
5372 /* XXX: TODO */ 5374 /* XXX: TODO */
5373 - GEN_EXCP_INVAL(ctx); 5375 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5374 } 5376 }
5375 5377
5376 /* XXX: not implemented on 440 ? */ 5378 /* XXX: not implemented on 440 ? */
5377 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA) 5379 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5378 { 5380 {
5379 #if defined(CONFIG_USER_ONLY) 5381 #if defined(CONFIG_USER_ONLY)
5380 - GEN_EXCP_PRIVOPC(ctx); 5382 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5381 #else 5383 #else
5382 TCGv t0; 5384 TCGv t0;
5383 if (unlikely(!ctx->mem_idx)) { 5385 if (unlikely(!ctx->mem_idx)) {
5384 - GEN_EXCP_PRIVOPC(ctx); 5386 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5385 return; 5387 return;
5386 } 5388 }
5387 t0 = tcg_temp_new(); 5389 t0 = tcg_temp_new();
@@ -5610,11 +5612,11 @@ GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); @@ -5610,11 +5612,11 @@ GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5610 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) 5612 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5611 { 5613 {
5612 #if defined(CONFIG_USER_ONLY) 5614 #if defined(CONFIG_USER_ONLY)
5613 - GEN_EXCP_PRIVREG(ctx); 5615 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5614 #else 5616 #else
5615 TCGv dcrn; 5617 TCGv dcrn;
5616 if (unlikely(!ctx->mem_idx)) { 5618 if (unlikely(!ctx->mem_idx)) {
5617 - GEN_EXCP_PRIVREG(ctx); 5619 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5618 return; 5620 return;
5619 } 5621 }
5620 /* NIP cannot be restored if the memory exception comes from an helper */ 5622 /* NIP cannot be restored if the memory exception comes from an helper */
@@ -5629,11 +5631,11 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) @@ -5629,11 +5631,11 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5629 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) 5631 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5630 { 5632 {
5631 #if defined(CONFIG_USER_ONLY) 5633 #if defined(CONFIG_USER_ONLY)
5632 - GEN_EXCP_PRIVREG(ctx); 5634 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5633 #else 5635 #else
5634 TCGv dcrn; 5636 TCGv dcrn;
5635 if (unlikely(!ctx->mem_idx)) { 5637 if (unlikely(!ctx->mem_idx)) {
5636 - GEN_EXCP_PRIVREG(ctx); 5638 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5637 return; 5639 return;
5638 } 5640 }
5639 /* NIP cannot be restored if the memory exception comes from an helper */ 5641 /* NIP cannot be restored if the memory exception comes from an helper */
@@ -5649,10 +5651,10 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) @@ -5649,10 +5651,10 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5649 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) 5651 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5650 { 5652 {
5651 #if defined(CONFIG_USER_ONLY) 5653 #if defined(CONFIG_USER_ONLY)
5652 - GEN_EXCP_PRIVREG(ctx); 5654 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5653 #else 5655 #else
5654 if (unlikely(!ctx->mem_idx)) { 5656 if (unlikely(!ctx->mem_idx)) {
5655 - GEN_EXCP_PRIVREG(ctx); 5657 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5656 return; 5658 return;
5657 } 5659 }
5658 /* NIP cannot be restored if the memory exception comes from an helper */ 5660 /* NIP cannot be restored if the memory exception comes from an helper */
@@ -5667,10 +5669,10 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) @@ -5667,10 +5669,10 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5667 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) 5669 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5668 { 5670 {
5669 #if defined(CONFIG_USER_ONLY) 5671 #if defined(CONFIG_USER_ONLY)
5670 - GEN_EXCP_PRIVREG(ctx); 5672 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5671 #else 5673 #else
5672 if (unlikely(!ctx->mem_idx)) { 5674 if (unlikely(!ctx->mem_idx)) {
5673 - GEN_EXCP_PRIVREG(ctx); 5675 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5674 return; 5676 return;
5675 } 5677 }
5676 /* NIP cannot be restored if the memory exception comes from an helper */ 5678 /* NIP cannot be restored if the memory exception comes from an helper */
@@ -5702,10 +5704,10 @@ GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) @@ -5702,10 +5704,10 @@ GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5702 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) 5704 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5703 { 5705 {
5704 #if defined(CONFIG_USER_ONLY) 5706 #if defined(CONFIG_USER_ONLY)
5705 - GEN_EXCP_PRIVOPC(ctx); 5707 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5706 #else 5708 #else
5707 if (unlikely(!ctx->mem_idx)) { 5709 if (unlikely(!ctx->mem_idx)) {
5708 - GEN_EXCP_PRIVOPC(ctx); 5710 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5709 return; 5711 return;
5710 } 5712 }
5711 /* interpreted as no-op */ 5713 /* interpreted as no-op */
@@ -5716,11 +5718,11 @@ GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) @@ -5716,11 +5718,11 @@ GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5716 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) 5718 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5717 { 5719 {
5718 #if defined(CONFIG_USER_ONLY) 5720 #if defined(CONFIG_USER_ONLY)
5719 - GEN_EXCP_PRIVOPC(ctx); 5721 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5720 #else 5722 #else
5721 TCGv EA, val; 5723 TCGv EA, val;
5722 if (unlikely(!ctx->mem_idx)) { 5724 if (unlikely(!ctx->mem_idx)) {
5723 - GEN_EXCP_PRIVOPC(ctx); 5725 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5724 return; 5726 return;
5725 } 5727 }
5726 gen_set_access_type(ctx, ACCESS_CACHE); 5728 gen_set_access_type(ctx, ACCESS_CACHE);
@@ -5747,10 +5749,10 @@ GEN_HANDLER2(icbt_40x, &quot;icbt&quot;, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT) @@ -5747,10 +5749,10 @@ GEN_HANDLER2(icbt_40x, &quot;icbt&quot;, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5747 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON) 5749 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5748 { 5750 {
5749 #if defined(CONFIG_USER_ONLY) 5751 #if defined(CONFIG_USER_ONLY)
5750 - GEN_EXCP_PRIVOPC(ctx); 5752 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5751 #else 5753 #else
5752 if (unlikely(!ctx->mem_idx)) { 5754 if (unlikely(!ctx->mem_idx)) {
5753 - GEN_EXCP_PRIVOPC(ctx); 5755 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5754 return; 5756 return;
5755 } 5757 }
5756 /* interpreted as no-op */ 5758 /* interpreted as no-op */
@@ -5761,10 +5763,10 @@ GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON) @@ -5761,10 +5763,10 @@ GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5761 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) 5763 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5762 { 5764 {
5763 #if defined(CONFIG_USER_ONLY) 5765 #if defined(CONFIG_USER_ONLY)
5764 - GEN_EXCP_PRIVOPC(ctx); 5766 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5765 #else 5767 #else
5766 if (unlikely(!ctx->mem_idx)) { 5768 if (unlikely(!ctx->mem_idx)) {
5767 - GEN_EXCP_PRIVOPC(ctx); 5769 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5768 return; 5770 return;
5769 } 5771 }
5770 /* interpreted as no-op */ 5772 /* interpreted as no-op */
@@ -5775,30 +5777,30 @@ GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) @@ -5775,30 +5777,30 @@ GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5775 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP) 5777 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5776 { 5778 {
5777 #if defined(CONFIG_USER_ONLY) 5779 #if defined(CONFIG_USER_ONLY)
5778 - GEN_EXCP_PRIVOPC(ctx); 5780 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5779 #else 5781 #else
5780 if (unlikely(!ctx->mem_idx)) { 5782 if (unlikely(!ctx->mem_idx)) {
5781 - GEN_EXCP_PRIVOPC(ctx); 5783 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5782 return; 5784 return;
5783 } 5785 }
5784 /* Restore CPU state */ 5786 /* Restore CPU state */
5785 gen_helper_40x_rfci(); 5787 gen_helper_40x_rfci();
5786 - GEN_SYNC(ctx); 5788 + gen_sync_exception(ctx);
5787 #endif 5789 #endif
5788 } 5790 }
5789 5791
5790 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) 5792 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5791 { 5793 {
5792 #if defined(CONFIG_USER_ONLY) 5794 #if defined(CONFIG_USER_ONLY)
5793 - GEN_EXCP_PRIVOPC(ctx); 5795 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5794 #else 5796 #else
5795 if (unlikely(!ctx->mem_idx)) { 5797 if (unlikely(!ctx->mem_idx)) {
5796 - GEN_EXCP_PRIVOPC(ctx); 5798 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5797 return; 5799 return;
5798 } 5800 }
5799 /* Restore CPU state */ 5801 /* Restore CPU state */
5800 gen_helper_rfci(); 5802 gen_helper_rfci();
5801 - GEN_SYNC(ctx); 5803 + gen_sync_exception(ctx);
5802 #endif 5804 #endif
5803 } 5805 }
5804 5806
@@ -5807,15 +5809,15 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) @@ -5807,15 +5809,15 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5807 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI) 5809 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5808 { 5810 {
5809 #if defined(CONFIG_USER_ONLY) 5811 #if defined(CONFIG_USER_ONLY)
5810 - GEN_EXCP_PRIVOPC(ctx); 5812 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5811 #else 5813 #else
5812 if (unlikely(!ctx->mem_idx)) { 5814 if (unlikely(!ctx->mem_idx)) {
5813 - GEN_EXCP_PRIVOPC(ctx); 5815 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5814 return; 5816 return;
5815 } 5817 }
5816 /* Restore CPU state */ 5818 /* Restore CPU state */
5817 gen_helper_rfdi(); 5819 gen_helper_rfdi();
5818 - GEN_SYNC(ctx); 5820 + gen_sync_exception(ctx);
5819 #endif 5821 #endif
5820 } 5822 }
5821 5823
@@ -5823,15 +5825,15 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI) @@ -5823,15 +5825,15 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5823 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI) 5825 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5824 { 5826 {
5825 #if defined(CONFIG_USER_ONLY) 5827 #if defined(CONFIG_USER_ONLY)
5826 - GEN_EXCP_PRIVOPC(ctx); 5828 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5827 #else 5829 #else
5828 if (unlikely(!ctx->mem_idx)) { 5830 if (unlikely(!ctx->mem_idx)) {
5829 - GEN_EXCP_PRIVOPC(ctx); 5831 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5830 return; 5832 return;
5831 } 5833 }
5832 /* Restore CPU state */ 5834 /* Restore CPU state */
5833 gen_helper_rfmci(); 5835 gen_helper_rfmci();
5834 - GEN_SYNC(ctx); 5836 + gen_sync_exception(ctx);
5835 #endif 5837 #endif
5836 } 5838 }
5837 5839
@@ -5840,10 +5842,10 @@ GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI) @@ -5840,10 +5842,10 @@ GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5840 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) 5842 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5841 { 5843 {
5842 #if defined(CONFIG_USER_ONLY) 5844 #if defined(CONFIG_USER_ONLY)
5843 - GEN_EXCP_PRIVOPC(ctx); 5845 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5844 #else 5846 #else
5845 if (unlikely(!ctx->mem_idx)) { 5847 if (unlikely(!ctx->mem_idx)) {
5846 - GEN_EXCP_PRIVOPC(ctx); 5848 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5847 return; 5849 return;
5848 } 5850 }
5849 switch (rB(ctx->opcode)) { 5851 switch (rB(ctx->opcode)) {
@@ -5854,7 +5856,7 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) @@ -5854,7 +5856,7 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5854 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5856 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5855 break; 5857 break;
5856 default: 5858 default:
5857 - GEN_EXCP_INVAL(ctx); 5859 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5858 break; 5860 break;
5859 } 5861 }
5860 #endif 5862 #endif
@@ -5864,11 +5866,11 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) @@ -5864,11 +5866,11 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5864 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) 5866 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5865 { 5867 {
5866 #if defined(CONFIG_USER_ONLY) 5868 #if defined(CONFIG_USER_ONLY)
5867 - GEN_EXCP_PRIVOPC(ctx); 5869 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5868 #else 5870 #else
5869 TCGv t0; 5871 TCGv t0;
5870 if (unlikely(!ctx->mem_idx)) { 5872 if (unlikely(!ctx->mem_idx)) {
5871 - GEN_EXCP_PRIVOPC(ctx); 5873 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5872 return; 5874 return;
5873 } 5875 }
5874 t0 = tcg_temp_new(); 5876 t0 = tcg_temp_new();
@@ -5891,10 +5893,10 @@ GEN_HANDLER2(tlbsx_40x, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) @@ -5891,10 +5893,10 @@ GEN_HANDLER2(tlbsx_40x, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5891 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) 5893 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5892 { 5894 {
5893 #if defined(CONFIG_USER_ONLY) 5895 #if defined(CONFIG_USER_ONLY)
5894 - GEN_EXCP_PRIVOPC(ctx); 5896 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 #else 5897 #else
5896 if (unlikely(!ctx->mem_idx)) { 5898 if (unlikely(!ctx->mem_idx)) {
5897 - GEN_EXCP_PRIVOPC(ctx); 5899 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5898 return; 5900 return;
5899 } 5901 }
5900 switch (rB(ctx->opcode)) { 5902 switch (rB(ctx->opcode)) {
@@ -5905,7 +5907,7 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) @@ -5905,7 +5907,7 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5905 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 5907 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5906 break; 5908 break;
5907 default: 5909 default:
5908 - GEN_EXCP_INVAL(ctx); 5910 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5909 break; 5911 break;
5910 } 5912 }
5911 #endif 5913 #endif
@@ -5916,10 +5918,10 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) @@ -5916,10 +5918,10 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5916 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) 5918 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5917 { 5919 {
5918 #if defined(CONFIG_USER_ONLY) 5920 #if defined(CONFIG_USER_ONLY)
5919 - GEN_EXCP_PRIVOPC(ctx); 5921 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5920 #else 5922 #else
5921 if (unlikely(!ctx->mem_idx)) { 5923 if (unlikely(!ctx->mem_idx)) {
5922 - GEN_EXCP_PRIVOPC(ctx); 5924 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5923 return; 5925 return;
5924 } 5926 }
5925 switch (rB(ctx->opcode)) { 5927 switch (rB(ctx->opcode)) {
@@ -5933,7 +5935,7 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) @@ -5933,7 +5935,7 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5933 } 5935 }
5934 break; 5936 break;
5935 default: 5937 default:
5936 - GEN_EXCP_INVAL(ctx); 5938 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5937 break; 5939 break;
5938 } 5940 }
5939 #endif 5941 #endif
@@ -5943,11 +5945,11 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) @@ -5943,11 +5945,11 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5943 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) 5945 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5944 { 5946 {
5945 #if defined(CONFIG_USER_ONLY) 5947 #if defined(CONFIG_USER_ONLY)
5946 - GEN_EXCP_PRIVOPC(ctx); 5948 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5947 #else 5949 #else
5948 TCGv t0; 5950 TCGv t0;
5949 if (unlikely(!ctx->mem_idx)) { 5951 if (unlikely(!ctx->mem_idx)) {
5950 - GEN_EXCP_PRIVOPC(ctx); 5952 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5951 return; 5953 return;
5952 } 5954 }
5953 t0 = tcg_temp_new(); 5955 t0 = tcg_temp_new();
@@ -5970,10 +5972,10 @@ GEN_HANDLER2(tlbsx_440, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) @@ -5970,10 +5972,10 @@ GEN_HANDLER2(tlbsx_440, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5970 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) 5972 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5971 { 5973 {
5972 #if defined(CONFIG_USER_ONLY) 5974 #if defined(CONFIG_USER_ONLY)
5973 - GEN_EXCP_PRIVOPC(ctx); 5975 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5974 #else 5976 #else
5975 if (unlikely(!ctx->mem_idx)) { 5977 if (unlikely(!ctx->mem_idx)) {
5976 - GEN_EXCP_PRIVOPC(ctx); 5978 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5977 return; 5979 return;
5978 } 5980 }
5979 switch (rB(ctx->opcode)) { 5981 switch (rB(ctx->opcode)) {
@@ -5987,7 +5989,7 @@ GEN_HANDLER2(tlbwe_440, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) @@ -5987,7 +5989,7 @@ GEN_HANDLER2(tlbwe_440, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5987 } 5989 }
5988 break; 5990 break;
5989 default: 5991 default:
5990 - GEN_EXCP_INVAL(ctx); 5992 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5991 break; 5993 break;
5992 } 5994 }
5993 #endif 5995 #endif
@@ -5997,11 +5999,11 @@ GEN_HANDLER2(tlbwe_440, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) @@ -5997,11 +5999,11 @@ GEN_HANDLER2(tlbwe_440, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5997 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) 5999 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5998 { 6000 {
5999 #if defined(CONFIG_USER_ONLY) 6001 #if defined(CONFIG_USER_ONLY)
6000 - GEN_EXCP_PRIVOPC(ctx); 6002 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6001 #else 6003 #else
6002 TCGv t0; 6004 TCGv t0;
6003 if (unlikely(!ctx->mem_idx)) { 6005 if (unlikely(!ctx->mem_idx)) {
6004 - GEN_EXCP_PRIVOPC(ctx); 6006 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6005 return; 6007 return;
6006 } 6008 }
6007 t0 = tcg_temp_new(); 6009 t0 = tcg_temp_new();
@@ -6012,7 +6014,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) @@ -6012,7 +6014,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6012 /* Stop translation to have a chance to raise an exception 6014 /* Stop translation to have a chance to raise an exception
6013 * if we just set msr_ee to 1 6015 * if we just set msr_ee to 1
6014 */ 6016 */
6015 - GEN_STOP(ctx); 6017 + gen_stop_exception(ctx);
6016 #endif 6018 #endif
6017 } 6019 }
6018 6020
@@ -6020,16 +6022,16 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) @@ -6020,16 +6022,16 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6020 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) 6022 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6021 { 6023 {
6022 #if defined(CONFIG_USER_ONLY) 6024 #if defined(CONFIG_USER_ONLY)
6023 - GEN_EXCP_PRIVOPC(ctx); 6025 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6024 #else 6026 #else
6025 if (unlikely(!ctx->mem_idx)) { 6027 if (unlikely(!ctx->mem_idx)) {
6026 - GEN_EXCP_PRIVOPC(ctx); 6028 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6027 return; 6029 return;
6028 } 6030 }
6029 if (ctx->opcode & 0x00010000) { 6031 if (ctx->opcode & 0x00010000) {
6030 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6032 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6031 /* Stop translation to have a chance to raise an exception */ 6033 /* Stop translation to have a chance to raise an exception */
6032 - GEN_STOP(ctx); 6034 + gen_stop_exception(ctx);
6033 } else { 6035 } else {
6034 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6036 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6035 } 6037 }
@@ -6075,7 +6077,7 @@ GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ @@ -6075,7 +6077,7 @@ GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6075 { \ 6077 { \
6076 TCGv EA; \ 6078 TCGv EA; \
6077 if (unlikely(!ctx->altivec_enabled)) { \ 6079 if (unlikely(!ctx->altivec_enabled)) { \
6078 - GEN_EXCP_NO_VR(ctx); \ 6080 + gen_exception(ctx, POWERPC_EXCP_VPU); \
6079 return; \ 6081 return; \
6080 } \ 6082 } \
6081 gen_set_access_type(ctx, ACCESS_INT); \ 6083 gen_set_access_type(ctx, ACCESS_INT); \
@@ -6099,7 +6101,7 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ @@ -6099,7 +6101,7 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6099 { \ 6101 { \
6100 TCGv EA; \ 6102 TCGv EA; \
6101 if (unlikely(!ctx->altivec_enabled)) { \ 6103 if (unlikely(!ctx->altivec_enabled)) { \
6102 - GEN_EXCP_NO_VR(ctx); \ 6104 + gen_exception(ctx, POWERPC_EXCP_VPU); \
6103 return; \ 6105 return; \
6104 } \ 6106 } \
6105 gen_set_access_type(ctx, ACCESS_INT); \ 6107 gen_set_access_type(ctx, ACCESS_INT); \
@@ -6161,7 +6163,7 @@ GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \ @@ -6161,7 +6163,7 @@ GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6161 /* Handler for undefined SPE opcodes */ 6163 /* Handler for undefined SPE opcodes */
6162 static always_inline void gen_speundef (DisasContext *ctx) 6164 static always_inline void gen_speundef (DisasContext *ctx)
6163 { 6165 {
6164 - GEN_EXCP_INVAL(ctx); 6166 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6165 } 6167 }
6166 6168
6167 /* SPE logic */ 6169 /* SPE logic */
@@ -6170,7 +6172,7 @@ static always_inline void gen_speundef (DisasContext *ctx) @@ -6170,7 +6172,7 @@ static always_inline void gen_speundef (DisasContext *ctx)
6170 static always_inline void gen_##name (DisasContext *ctx) \ 6172 static always_inline void gen_##name (DisasContext *ctx) \
6171 { \ 6173 { \
6172 if (unlikely(!ctx->spe_enabled)) { \ 6174 if (unlikely(!ctx->spe_enabled)) { \
6173 - GEN_EXCP_NO_AP(ctx); \ 6175 + gen_exception(ctx, POWERPC_EXCP_APU); \
6174 return; \ 6176 return; \
6175 } \ 6177 } \
6176 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 6178 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6181,7 +6183,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -6181,7 +6183,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
6181 static always_inline void gen_##name (DisasContext *ctx) \ 6183 static always_inline void gen_##name (DisasContext *ctx) \
6182 { \ 6184 { \
6183 if (unlikely(!ctx->spe_enabled)) { \ 6185 if (unlikely(!ctx->spe_enabled)) { \
6184 - GEN_EXCP_NO_AP(ctx); \ 6186 + gen_exception(ctx, POWERPC_EXCP_APU); \
6185 return; \ 6187 return; \
6186 } \ 6188 } \
6187 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 6189 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6206,7 +6208,7 @@ GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); @@ -6206,7 +6208,7 @@ GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6206 static always_inline void gen_##name (DisasContext *ctx) \ 6208 static always_inline void gen_##name (DisasContext *ctx) \
6207 { \ 6209 { \
6208 if (unlikely(!ctx->spe_enabled)) { \ 6210 if (unlikely(!ctx->spe_enabled)) { \
6209 - GEN_EXCP_NO_AP(ctx); \ 6211 + gen_exception(ctx, POWERPC_EXCP_APU); \
6210 return; \ 6212 return; \
6211 } \ 6213 } \
6212 TCGv_i32 t0 = tcg_temp_local_new_i32(); \ 6214 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6227,7 +6229,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -6227,7 +6229,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
6227 static always_inline void gen_##name (DisasContext *ctx) \ 6229 static always_inline void gen_##name (DisasContext *ctx) \
6228 { \ 6230 { \
6229 if (unlikely(!ctx->spe_enabled)) { \ 6231 if (unlikely(!ctx->spe_enabled)) { \
6230 - GEN_EXCP_NO_AP(ctx); \ 6232 + gen_exception(ctx, POWERPC_EXCP_APU); \
6231 return; \ 6233 return; \
6232 } \ 6234 } \
6233 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 6235 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6247,7 +6249,7 @@ GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); @@ -6247,7 +6249,7 @@ GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6247 static always_inline void gen_##name (DisasContext *ctx) \ 6249 static always_inline void gen_##name (DisasContext *ctx) \
6248 { \ 6250 { \
6249 if (unlikely(!ctx->spe_enabled)) { \ 6251 if (unlikely(!ctx->spe_enabled)) { \
6250 - GEN_EXCP_NO_AP(ctx); \ 6252 + gen_exception(ctx, POWERPC_EXCP_APU); \
6251 return; \ 6253 return; \
6252 } \ 6254 } \
6253 TCGv_i32 t0 = tcg_temp_local_new_i32(); \ 6255 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6268,7 +6270,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -6268,7 +6270,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
6268 static always_inline void gen_##name (DisasContext *ctx) \ 6270 static always_inline void gen_##name (DisasContext *ctx) \
6269 { \ 6271 { \
6270 if (unlikely(!ctx->spe_enabled)) { \ 6272 if (unlikely(!ctx->spe_enabled)) { \
6271 - GEN_EXCP_NO_AP(ctx); \ 6273 + gen_exception(ctx, POWERPC_EXCP_APU); \
6272 return; \ 6274 return; \
6273 } \ 6275 } \
6274 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ 6276 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
@@ -6306,7 +6308,7 @@ GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); @@ -6306,7 +6308,7 @@ GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6306 static always_inline void gen_##name (DisasContext *ctx) \ 6308 static always_inline void gen_##name (DisasContext *ctx) \
6307 { \ 6309 { \
6308 if (unlikely(!ctx->spe_enabled)) { \ 6310 if (unlikely(!ctx->spe_enabled)) { \
6309 - GEN_EXCP_NO_AP(ctx); \ 6311 + gen_exception(ctx, POWERPC_EXCP_APU); \
6310 return; \ 6312 return; \
6311 } \ 6313 } \
6312 TCGv_i32 t0 = tcg_temp_local_new_i32(); \ 6314 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6332,7 +6334,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -6332,7 +6334,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
6332 static always_inline void gen_##name (DisasContext *ctx) \ 6334 static always_inline void gen_##name (DisasContext *ctx) \
6333 { \ 6335 { \
6334 if (unlikely(!ctx->spe_enabled)) { \ 6336 if (unlikely(!ctx->spe_enabled)) { \
6335 - GEN_EXCP_NO_AP(ctx); \ 6337 + gen_exception(ctx, POWERPC_EXCP_APU); \
6336 return; \ 6338 return; \
6337 } \ 6339 } \
6338 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 6340 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6410,7 +6412,7 @@ GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); @@ -6410,7 +6412,7 @@ GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6410 static always_inline void gen_evmergehi (DisasContext *ctx) 6412 static always_inline void gen_evmergehi (DisasContext *ctx)
6411 { 6413 {
6412 if (unlikely(!ctx->spe_enabled)) { 6414 if (unlikely(!ctx->spe_enabled)) {
6413 - GEN_EXCP_NO_AP(ctx); 6415 + gen_exception(ctx, POWERPC_EXCP_APU);
6414 return; 6416 return;
6415 } 6417 }
6416 #if defined(TARGET_PPC64) 6418 #if defined(TARGET_PPC64)
@@ -6439,7 +6441,7 @@ GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); @@ -6439,7 +6441,7 @@ GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6439 static always_inline void gen_##name (DisasContext *ctx) \ 6441 static always_inline void gen_##name (DisasContext *ctx) \
6440 { \ 6442 { \
6441 if (unlikely(!ctx->spe_enabled)) { \ 6443 if (unlikely(!ctx->spe_enabled)) { \
6442 - GEN_EXCP_NO_AP(ctx); \ 6444 + gen_exception(ctx, POWERPC_EXCP_APU); \
6443 return; \ 6445 return; \
6444 } \ 6446 } \
6445 TCGv_i32 t0 = tcg_temp_local_new_i32(); \ 6447 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6449,7 +6451,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -6449,7 +6451,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
6449 tcg_op(t0, t0, rA(ctx->opcode)); \ 6451 tcg_op(t0, t0, rA(ctx->opcode)); \
6450 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ 6452 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6451 tcg_gen_trunc_i64_i32(t1, t2); \ 6453 tcg_gen_trunc_i64_i32(t1, t2); \
6452 - tcg_temp_free_i64(t2); \ 6454 + tcg_temp_free_i64(t2); \
6453 tcg_op(t1, t1, rA(ctx->opcode)); \ 6455 tcg_op(t1, t1, rA(ctx->opcode)); \
6454 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ 6456 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6455 tcg_temp_free_i32(t0); \ 6457 tcg_temp_free_i32(t0); \
@@ -6460,7 +6462,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -6460,7 +6462,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
6460 static always_inline void gen_##name (DisasContext *ctx) \ 6462 static always_inline void gen_##name (DisasContext *ctx) \
6461 { \ 6463 { \
6462 if (unlikely(!ctx->spe_enabled)) { \ 6464 if (unlikely(!ctx->spe_enabled)) { \
6463 - GEN_EXCP_NO_AP(ctx); \ 6465 + gen_exception(ctx, POWERPC_EXCP_APU); \
6464 return; \ 6466 return; \
6465 } \ 6467 } \
6466 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 6468 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
@@ -6478,7 +6480,7 @@ GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); @@ -6478,7 +6480,7 @@ GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6478 static always_inline void gen_##name (DisasContext *ctx) \ 6480 static always_inline void gen_##name (DisasContext *ctx) \
6479 { \ 6481 { \
6480 if (unlikely(!ctx->spe_enabled)) { \ 6482 if (unlikely(!ctx->spe_enabled)) { \
6481 - GEN_EXCP_NO_AP(ctx); \ 6483 + gen_exception(ctx, POWERPC_EXCP_APU); \
6482 return; \ 6484 return; \
6483 } \ 6485 } \
6484 int l1 = gen_new_label(); \ 6486 int l1 = gen_new_label(); \
@@ -6518,7 +6520,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -6518,7 +6520,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
6518 static always_inline void gen_##name (DisasContext *ctx) \ 6520 static always_inline void gen_##name (DisasContext *ctx) \
6519 { \ 6521 { \
6520 if (unlikely(!ctx->spe_enabled)) { \ 6522 if (unlikely(!ctx->spe_enabled)) { \
6521 - GEN_EXCP_NO_AP(ctx); \ 6523 + gen_exception(ctx, POWERPC_EXCP_APU); \
6522 return; \ 6524 return; \
6523 } \ 6525 } \
6524 int l1 = gen_new_label(); \ 6526 int l1 = gen_new_label(); \
@@ -6561,7 +6563,7 @@ static always_inline void gen_brinc (DisasContext *ctx) @@ -6561,7 +6563,7 @@ static always_inline void gen_brinc (DisasContext *ctx)
6561 static always_inline void gen_evmergelo (DisasContext *ctx) 6563 static always_inline void gen_evmergelo (DisasContext *ctx)
6562 { 6564 {
6563 if (unlikely(!ctx->spe_enabled)) { 6565 if (unlikely(!ctx->spe_enabled)) {
6564 - GEN_EXCP_NO_AP(ctx); 6566 + gen_exception(ctx, POWERPC_EXCP_APU);
6565 return; 6567 return;
6566 } 6568 }
6567 #if defined(TARGET_PPC64) 6569 #if defined(TARGET_PPC64)
@@ -6580,7 +6582,7 @@ static always_inline void gen_evmergelo (DisasContext *ctx) @@ -6580,7 +6582,7 @@ static always_inline void gen_evmergelo (DisasContext *ctx)
6580 static always_inline void gen_evmergehilo (DisasContext *ctx) 6582 static always_inline void gen_evmergehilo (DisasContext *ctx)
6581 { 6583 {
6582 if (unlikely(!ctx->spe_enabled)) { 6584 if (unlikely(!ctx->spe_enabled)) {
6583 - GEN_EXCP_NO_AP(ctx); 6585 + gen_exception(ctx, POWERPC_EXCP_APU);
6584 return; 6586 return;
6585 } 6587 }
6586 #if defined(TARGET_PPC64) 6588 #if defined(TARGET_PPC64)
@@ -6599,7 +6601,7 @@ static always_inline void gen_evmergehilo (DisasContext *ctx) @@ -6599,7 +6601,7 @@ static always_inline void gen_evmergehilo (DisasContext *ctx)
6599 static always_inline void gen_evmergelohi (DisasContext *ctx) 6601 static always_inline void gen_evmergelohi (DisasContext *ctx)
6600 { 6602 {
6601 if (unlikely(!ctx->spe_enabled)) { 6603 if (unlikely(!ctx->spe_enabled)) {
6602 - GEN_EXCP_NO_AP(ctx); 6604 + gen_exception(ctx, POWERPC_EXCP_APU);
6603 return; 6605 return;
6604 } 6606 }
6605 #if defined(TARGET_PPC64) 6607 #if defined(TARGET_PPC64)
@@ -7050,7 +7052,7 @@ GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \ @@ -7050,7 +7052,7 @@ GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7050 { \ 7052 { \
7051 TCGv t0; \ 7053 TCGv t0; \
7052 if (unlikely(!ctx->spe_enabled)) { \ 7054 if (unlikely(!ctx->spe_enabled)) { \
7053 - GEN_EXCP_NO_AP(ctx); \ 7055 + gen_exception(ctx, POWERPC_EXCP_APU); \
7054 return; \ 7056 return; \
7055 } \ 7057 } \
7056 gen_set_access_type(ctx, ACCESS_INT); \ 7058 gen_set_access_type(ctx, ACCESS_INT); \
@@ -7212,7 +7214,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7212,7 +7214,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7212 TCGv_i32 t0, t1; \ 7214 TCGv_i32 t0, t1; \
7213 TCGv_i64 t2; \ 7215 TCGv_i64 t2; \
7214 if (unlikely(!ctx->spe_enabled)) { \ 7216 if (unlikely(!ctx->spe_enabled)) { \
7215 - GEN_EXCP_NO_AP(ctx); \ 7217 + gen_exception(ctx, POWERPC_EXCP_APU); \
7216 return; \ 7218 return; \
7217 } \ 7219 } \
7218 t0 = tcg_temp_new_i32(); \ 7220 t0 = tcg_temp_new_i32(); \
@@ -7233,7 +7235,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7233,7 +7235,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7233 static always_inline void gen_##name (DisasContext *ctx) \ 7235 static always_inline void gen_##name (DisasContext *ctx) \
7234 { \ 7236 { \
7235 if (unlikely(!ctx->spe_enabled)) { \ 7237 if (unlikely(!ctx->spe_enabled)) { \
7236 - GEN_EXCP_NO_AP(ctx); \ 7238 + gen_exception(ctx, POWERPC_EXCP_APU); \
7237 return; \ 7239 return; \
7238 } \ 7240 } \
7239 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 7241 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -7244,7 +7246,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7244,7 +7246,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7244 { \ 7246 { \
7245 TCGv_i32 t0, t1; \ 7247 TCGv_i32 t0, t1; \
7246 if (unlikely(!ctx->spe_enabled)) { \ 7248 if (unlikely(!ctx->spe_enabled)) { \
7247 - GEN_EXCP_NO_AP(ctx); \ 7249 + gen_exception(ctx, POWERPC_EXCP_APU); \
7248 return; \ 7250 return; \
7249 } \ 7251 } \
7250 t0 = tcg_temp_new_i32(); \ 7252 t0 = tcg_temp_new_i32(); \
@@ -7259,7 +7261,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7259,7 +7261,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7259 static always_inline void gen_##name (DisasContext *ctx) \ 7261 static always_inline void gen_##name (DisasContext *ctx) \
7260 { \ 7262 { \
7261 if (unlikely(!ctx->spe_enabled)) { \ 7263 if (unlikely(!ctx->spe_enabled)) { \
7262 - GEN_EXCP_NO_AP(ctx); \ 7264 + gen_exception(ctx, POWERPC_EXCP_APU); \
7263 return; \ 7265 return; \
7264 } \ 7266 } \
7265 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ 7267 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -7300,7 +7302,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7300,7 +7302,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7300 static always_inline void gen_##name (DisasContext *ctx) \ 7302 static always_inline void gen_##name (DisasContext *ctx) \
7301 { \ 7303 { \
7302 if (unlikely(!ctx->spe_enabled)) { \ 7304 if (unlikely(!ctx->spe_enabled)) { \
7303 - GEN_EXCP_NO_AP(ctx); \ 7305 + gen_exception(ctx, POWERPC_EXCP_APU); \
7304 return; \ 7306 return; \
7305 } \ 7307 } \
7306 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ 7308 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
@@ -7311,7 +7313,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7311,7 +7313,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7311 { \ 7313 { \
7312 TCGv_i64 t0, t1; \ 7314 TCGv_i64 t0, t1; \
7313 if (unlikely(!ctx->spe_enabled)) { \ 7315 if (unlikely(!ctx->spe_enabled)) { \
7314 - GEN_EXCP_NO_AP(ctx); \ 7316 + gen_exception(ctx, POWERPC_EXCP_APU); \
7315 return; \ 7317 return; \
7316 } \ 7318 } \
7317 t0 = tcg_temp_new_i64(); \ 7319 t0 = tcg_temp_new_i64(); \
@@ -7327,7 +7329,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7327,7 +7329,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7327 static always_inline void gen_##name (DisasContext *ctx) \ 7329 static always_inline void gen_##name (DisasContext *ctx) \
7328 { \ 7330 { \
7329 if (unlikely(!ctx->spe_enabled)) { \ 7331 if (unlikely(!ctx->spe_enabled)) { \
7330 - GEN_EXCP_NO_AP(ctx); \ 7332 + gen_exception(ctx, POWERPC_EXCP_APU); \
7331 return; \ 7333 return; \
7332 } \ 7334 } \
7333 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ 7335 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -7338,7 +7340,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -7338,7 +7340,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
7338 { \ 7340 { \
7339 TCGv_i64 t0, t1; \ 7341 TCGv_i64 t0, t1; \
7340 if (unlikely(!ctx->spe_enabled)) { \ 7342 if (unlikely(!ctx->spe_enabled)) { \
7341 - GEN_EXCP_NO_AP(ctx); \ 7343 + gen_exception(ctx, POWERPC_EXCP_APU); \
7342 return; \ 7344 return; \
7343 } \ 7345 } \
7344 t0 = tcg_temp_new_i64(); \ 7346 t0 = tcg_temp_new_i64(); \
@@ -7360,7 +7362,7 @@ GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); @@ -7360,7 +7362,7 @@ GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7360 static always_inline void gen_evfsabs (DisasContext *ctx) 7362 static always_inline void gen_evfsabs (DisasContext *ctx)
7361 { 7363 {
7362 if (unlikely(!ctx->spe_enabled)) { 7364 if (unlikely(!ctx->spe_enabled)) {
7363 - GEN_EXCP_NO_AP(ctx); 7365 + gen_exception(ctx, POWERPC_EXCP_APU);
7364 return; 7366 return;
7365 } 7367 }
7366 #if defined(TARGET_PPC64) 7368 #if defined(TARGET_PPC64)
@@ -7373,7 +7375,7 @@ static always_inline void gen_evfsabs (DisasContext *ctx) @@ -7373,7 +7375,7 @@ static always_inline void gen_evfsabs (DisasContext *ctx)
7373 static always_inline void gen_evfsnabs (DisasContext *ctx) 7375 static always_inline void gen_evfsnabs (DisasContext *ctx)
7374 { 7376 {
7375 if (unlikely(!ctx->spe_enabled)) { 7377 if (unlikely(!ctx->spe_enabled)) {
7376 - GEN_EXCP_NO_AP(ctx); 7378 + gen_exception(ctx, POWERPC_EXCP_APU);
7377 return; 7379 return;
7378 } 7380 }
7379 #if defined(TARGET_PPC64) 7381 #if defined(TARGET_PPC64)
@@ -7386,7 +7388,7 @@ static always_inline void gen_evfsnabs (DisasContext *ctx) @@ -7386,7 +7388,7 @@ static always_inline void gen_evfsnabs (DisasContext *ctx)
7386 static always_inline void gen_evfsneg (DisasContext *ctx) 7388 static always_inline void gen_evfsneg (DisasContext *ctx)
7387 { 7389 {
7388 if (unlikely(!ctx->spe_enabled)) { 7390 if (unlikely(!ctx->spe_enabled)) {
7389 - GEN_EXCP_NO_AP(ctx); 7391 + gen_exception(ctx, POWERPC_EXCP_APU);
7390 return; 7392 return;
7391 } 7393 }
7392 #if defined(TARGET_PPC64) 7394 #if defined(TARGET_PPC64)
@@ -7442,7 +7444,7 @@ GEN_SPEFPUOP_ARITH2_32_32(efsdiv); @@ -7442,7 +7444,7 @@ GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7442 static always_inline void gen_efsabs (DisasContext *ctx) 7444 static always_inline void gen_efsabs (DisasContext *ctx)
7443 { 7445 {
7444 if (unlikely(!ctx->spe_enabled)) { 7446 if (unlikely(!ctx->spe_enabled)) {
7445 - GEN_EXCP_NO_AP(ctx); 7447 + gen_exception(ctx, POWERPC_EXCP_APU);
7446 return; 7448 return;
7447 } 7449 }
7448 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); 7450 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
@@ -7450,7 +7452,7 @@ static always_inline void gen_efsabs (DisasContext *ctx) @@ -7450,7 +7452,7 @@ static always_inline void gen_efsabs (DisasContext *ctx)
7450 static always_inline void gen_efsnabs (DisasContext *ctx) 7452 static always_inline void gen_efsnabs (DisasContext *ctx)
7451 { 7453 {
7452 if (unlikely(!ctx->spe_enabled)) { 7454 if (unlikely(!ctx->spe_enabled)) {
7453 - GEN_EXCP_NO_AP(ctx); 7455 + gen_exception(ctx, POWERPC_EXCP_APU);
7454 return; 7456 return;
7455 } 7457 }
7456 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); 7458 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
@@ -7458,7 +7460,7 @@ static always_inline void gen_efsnabs (DisasContext *ctx) @@ -7458,7 +7460,7 @@ static always_inline void gen_efsnabs (DisasContext *ctx)
7458 static always_inline void gen_efsneg (DisasContext *ctx) 7460 static always_inline void gen_efsneg (DisasContext *ctx)
7459 { 7461 {
7460 if (unlikely(!ctx->spe_enabled)) { 7462 if (unlikely(!ctx->spe_enabled)) {
7461 - GEN_EXCP_NO_AP(ctx); 7463 + gen_exception(ctx, POWERPC_EXCP_APU);
7462 return; 7464 return;
7463 } 7465 }
7464 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); 7466 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
@@ -7510,7 +7512,7 @@ GEN_SPEFPUOP_ARITH2_64_64(efddiv); @@ -7510,7 +7512,7 @@ GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7510 static always_inline void gen_efdabs (DisasContext *ctx) 7512 static always_inline void gen_efdabs (DisasContext *ctx)
7511 { 7513 {
7512 if (unlikely(!ctx->spe_enabled)) { 7514 if (unlikely(!ctx->spe_enabled)) {
7513 - GEN_EXCP_NO_AP(ctx); 7515 + gen_exception(ctx, POWERPC_EXCP_APU);
7514 return; 7516 return;
7515 } 7517 }
7516 #if defined(TARGET_PPC64) 7518 #if defined(TARGET_PPC64)
@@ -7522,7 +7524,7 @@ static always_inline void gen_efdabs (DisasContext *ctx) @@ -7522,7 +7524,7 @@ static always_inline void gen_efdabs (DisasContext *ctx)
7522 static always_inline void gen_efdnabs (DisasContext *ctx) 7524 static always_inline void gen_efdnabs (DisasContext *ctx)
7523 { 7525 {
7524 if (unlikely(!ctx->spe_enabled)) { 7526 if (unlikely(!ctx->spe_enabled)) {
7525 - GEN_EXCP_NO_AP(ctx); 7527 + gen_exception(ctx, POWERPC_EXCP_APU);
7526 return; 7528 return;
7527 } 7529 }
7528 #if defined(TARGET_PPC64) 7530 #if defined(TARGET_PPC64)
@@ -7534,7 +7536,7 @@ static always_inline void gen_efdnabs (DisasContext *ctx) @@ -7534,7 +7536,7 @@ static always_inline void gen_efdnabs (DisasContext *ctx)
7534 static always_inline void gen_efdneg (DisasContext *ctx) 7536 static always_inline void gen_efdneg (DisasContext *ctx)
7535 { 7537 {
7536 if (unlikely(!ctx->spe_enabled)) { 7538 if (unlikely(!ctx->spe_enabled)) {
7537 - GEN_EXCP_NO_AP(ctx); 7539 + gen_exception(ctx, POWERPC_EXCP_APU);
7538 return; 7540 return;
7539 } 7541 }
7540 #if defined(TARGET_PPC64) 7542 #if defined(TARGET_PPC64)
@@ -7766,8 +7768,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7766,8 +7768,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7766 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { 7768 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7767 TAILQ_FOREACH(bp, &env->breakpoints, entry) { 7769 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7768 if (bp->pc == ctx.nip) { 7770 if (bp->pc == ctx.nip) {
7769 - gen_update_nip(&ctx, ctx.nip);  
7770 - gen_helper_raise_debug(); 7771 + gen_debug_exception(ctxp);
7771 break; 7772 break;
7772 } 7773 }
7773 } 7774 }
@@ -7844,7 +7845,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7844,7 +7845,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7844 opc2(ctx.opcode), opc3(ctx.opcode), 7845 opc2(ctx.opcode), opc3(ctx.opcode),
7845 ctx.opcode, ctx.nip - 4); 7846 ctx.opcode, ctx.nip - 4);
7846 } 7847 }
7847 - GEN_EXCP_INVAL(ctxp); 7848 + gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7848 break; 7849 break;
7849 } 7850 }
7850 } 7851 }
@@ -7858,7 +7859,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7858,7 +7859,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7858 ctx.exception != POWERPC_SYSCALL && 7859 ctx.exception != POWERPC_SYSCALL &&
7859 ctx.exception != POWERPC_EXCP_TRAP && 7860 ctx.exception != POWERPC_EXCP_TRAP &&
7860 ctx.exception != POWERPC_EXCP_BRANCH)) { 7861 ctx.exception != POWERPC_EXCP_BRANCH)) {
7861 - GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0); 7862 + gen_exception(ctxp, POWERPC_EXCP_TRACE);
7862 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || 7863 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7863 (env->singlestep_enabled) || 7864 (env->singlestep_enabled) ||
7864 num_insns >= max_insns)) { 7865 num_insns >= max_insns)) {
@@ -7877,8 +7878,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7877,8 +7878,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7877 gen_goto_tb(&ctx, 0, ctx.nip); 7878 gen_goto_tb(&ctx, 0, ctx.nip);
7878 } else if (ctx.exception != POWERPC_EXCP_BRANCH) { 7879 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7879 if (unlikely(env->singlestep_enabled)) { 7880 if (unlikely(env->singlestep_enabled)) {
7880 - gen_update_nip(&ctx, ctx.nip);  
7881 - gen_helper_raise_debug(); 7881 + gen_debug_exception(ctxp);
7882 } 7882 }
7883 /* Generate the return instruction */ 7883 /* Generate the return instruction */
7884 tcg_gen_exit_tb(0); 7884 tcg_gen_exit_tb(0);
target-ppc/translate_init.c
  View file @e06fcd7
@@ -347,7 +347,7 @@ static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) @@ -347,7 +347,7 @@ static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
347 347
348 gen_helper_store_hid0_601(cpu_gpr[gprn]); 348 gen_helper_store_hid0_601(cpu_gpr[gprn]);
349 /* Must stop the translation as endianness may have changed */ 349 /* Must stop the translation as endianness may have changed */
350 - GEN_STOP(ctx); 350 + gen_stop_exception(ctx);
351 } 351 }
352 #endif 352 #endif
353 353
@@ -391,7 +391,7 @@ static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) @@ -391,7 +391,7 @@ static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
391 391
392 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]); 392 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
393 /* We must stop translation as we may have rebooted */ 393 /* We must stop translation as we may have rebooted */
394 - GEN_STOP(ctx); 394 + gen_stop_exception(ctx);
395 } 395 }
396 396
397 static void spr_write_40x_sler (void *opaque, int sprn, int gprn) 397 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
@@ -466,7 +466,7 @@ static void spr_write_excp_vector (void *opaque, int sprn, int gprn) @@ -466,7 +466,7 @@ static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
466 } else { 466 } else {
467 printf("Trying to write an unknown exception vector %d %03x\n", 467 printf("Trying to write an unknown exception vector %d %03x\n",
468 sprn, sprn); 468 sprn, sprn);
469 - GEN_EXCP_PRIVREG(ctx); 469 + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
470 } 470 }
471 } 471 }
472 #endif 472 #endif