Commit e0147e41385d1ec2961d1300a135cb2c859b04bc
1 parent
05b93603
target-ppc: fix fload_invalid_op_excp()
The argument is a value, not a flag. Update the tests accordingly. Also set a correct default value for NaN. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6047 c046a42c-6fe2-441c-8c8c-71466251a162
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7 additions
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9 deletions
target-ppc/op_helper.c
... | ... | @@ -671,15 +671,13 @@ static always_inline uint64_t fload_invalid_op_excp (int op) |
671 | 671 | int ve; |
672 | 672 | |
673 | 673 | ve = fpscr_ve; |
674 | - if (op & POWERPC_EXCP_FP_VXSNAN) { | |
675 | - /* Operation on signaling NaN */ | |
674 | + switch (op) { | |
675 | + case POWERPC_EXCP_FP_VXSNAN: | |
676 | 676 | env->fpscr |= 1 << FPSCR_VXSNAN; |
677 | - } | |
678 | - if (op & POWERPC_EXCP_FP_VXSOFT) { | |
679 | - /* Software-defined condition */ | |
677 | + break; | |
678 | + case POWERPC_EXCP_FP_VXSOFT: | |
680 | 679 | env->fpscr |= 1 << FPSCR_VXSOFT; |
681 | - } | |
682 | - switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) { | |
680 | + break; | |
683 | 681 | case POWERPC_EXCP_FP_VXISI: |
684 | 682 | /* Magnitude subtraction of infinities */ |
685 | 683 | env->fpscr |= 1 << FPSCR_VXISI; |
... | ... | @@ -718,7 +716,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op) |
718 | 716 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); |
719 | 717 | if (ve == 0) { |
720 | 718 | /* Set the result to quiet NaN */ |
721 | - ret = UINT64_MAX; | |
719 | + ret = 0xFFF8000000000000ULL; | |
722 | 720 | env->fpscr &= ~(0xF << FPSCR_FPCC); |
723 | 721 | env->fpscr |= 0x11 << FPSCR_FPCC; |
724 | 722 | } |
... | ... | @@ -729,7 +727,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op) |
729 | 727 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); |
730 | 728 | if (ve == 0) { |
731 | 729 | /* Set the result to quiet NaN */ |
732 | - ret = UINT64_MAX; | |
730 | + ret = 0xFFF8000000000000ULL; | |
733 | 731 | env->fpscr &= ~(0xF << FPSCR_FPCC); |
734 | 732 | env->fpscr |= 0x11 << FPSCR_FPCC; |
735 | 733 | } | ... | ... |