gwj / at91sam9263 · Commits

Commit e00fcff7106acaa0062b155524fd62684b0e0193

Authored by aurel32
1 parent ea0f49a7

target-mips: use the new rotr/rotri instructions 

Acked-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5622 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 5 additions and 43 deletions
target-mips/translate.c
  View file @e00fcff
@@ -1455,17 +1455,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1455,17 +1455,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1455 if (env->insn_flags & ISA_MIPS32R2) { 1455 if (env->insn_flags & ISA_MIPS32R2) {
1456 if (uimm != 0) { 1456 if (uimm != 0) {
1457 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); 1457 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
1458 - TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);  
1459 1458
1460 tcg_gen_trunc_tl_i32(r_tmp1, t0); 1459 tcg_gen_trunc_tl_i32(r_tmp1, t0);
1461 - tcg_gen_movi_i32(r_tmp2, 0x20);  
1462 - tcg_gen_subi_i32(r_tmp2, r_tmp2, uimm);  
1463 - tcg_gen_shl_i32(r_tmp2, r_tmp1, r_tmp2);  
1464 - tcg_gen_shri_i32(r_tmp1, r_tmp1, uimm);  
1465 - tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp2); 1460 + tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm);
1466 tcg_gen_ext_i32_tl(t0, r_tmp1); 1461 tcg_gen_ext_i32_tl(t0, r_tmp1);
1467 tcg_temp_free(r_tmp1); 1462 tcg_temp_free(r_tmp1);
1468 - tcg_temp_free(r_tmp2);  
1469 } 1463 }
1470 opn = "rotr"; 1464 opn = "rotr";
1471 } else { 1465 } else {
@@ -1500,14 +1494,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1500,14 +1494,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1500 /* drotr is decoded as dsrl on non-R2 CPUs */ 1494 /* drotr is decoded as dsrl on non-R2 CPUs */
1501 if (env->insn_flags & ISA_MIPS32R2) { 1495 if (env->insn_flags & ISA_MIPS32R2) {
1502 if (uimm != 0) { 1496 if (uimm != 0) {
1503 - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);  
1504 -  
1505 - tcg_gen_movi_tl(r_tmp1, 0x40);  
1506 - tcg_gen_subi_tl(r_tmp1, r_tmp1, uimm);  
1507 - tcg_gen_shl_tl(r_tmp1, t0, r_tmp1);  
1508 - tcg_gen_shri_tl(t0, t0, uimm);  
1509 - tcg_gen_or_tl(t0, t0, r_tmp1);  
1510 - tcg_temp_free(r_tmp1); 1497 + tcg_gen_rotri_tl(t0, t0, uimm);
1511 } 1498 }
1512 opn = "drotr"; 1499 opn = "drotr";
1513 } else { 1500 } else {
@@ -1538,18 +1525,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1538,18 +1525,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1538 case 1: 1525 case 1:
1539 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ 1526 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1540 if (env->insn_flags & ISA_MIPS32R2) { 1527 if (env->insn_flags & ISA_MIPS32R2) {
1541 - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);  
1542 - TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);  
1543 -  
1544 - tcg_gen_movi_tl(r_tmp1, 0x40);  
1545 - tcg_gen_movi_tl(r_tmp2, 32);  
1546 - tcg_gen_addi_tl(r_tmp2, r_tmp2, uimm);  
1547 - tcg_gen_sub_tl(r_tmp1, r_tmp1, r_tmp2);  
1548 - tcg_gen_shl_tl(r_tmp1, t0, r_tmp1);  
1549 - tcg_gen_shr_tl(t0, t0, r_tmp2);  
1550 - tcg_gen_or_tl(t0, t0, r_tmp1);  
1551 - tcg_temp_free(r_tmp1);  
1552 - tcg_temp_free(r_tmp2); 1528 + tcg_gen_rotri_tl(t0, t0, uimm + 32);
1553 opn = "drotr32"; 1529 opn = "drotr32";
1554 } else { 1530 } else {
1555 tcg_gen_shri_tl(t0, t0, uimm + 32); 1531 tcg_gen_shri_tl(t0, t0, uimm + 32);
@@ -1809,19 +1785,12 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1809,19 +1785,12 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1809 { 1785 {
1810 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); 1786 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
1811 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); 1787 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
1812 - TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);  
1813 1788
1814 tcg_gen_trunc_tl_i32(r_tmp1, t0); 1789 tcg_gen_trunc_tl_i32(r_tmp1, t0);
1815 tcg_gen_trunc_tl_i32(r_tmp2, t1); 1790 tcg_gen_trunc_tl_i32(r_tmp2, t1);
1816 - tcg_gen_movi_i32(r_tmp3, 0x20);  
1817 - tcg_gen_sub_i32(r_tmp3, r_tmp3, r_tmp1);  
1818 - tcg_gen_shl_i32(r_tmp3, r_tmp2, r_tmp3);  
1819 - tcg_gen_shr_i32(r_tmp1, r_tmp2, r_tmp1);  
1820 - tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp3);  
1821 - tcg_gen_ext_i32_tl(t0, r_tmp1); 1791 + tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2);
1822 tcg_temp_free(r_tmp1); 1792 tcg_temp_free(r_tmp1);
1823 tcg_temp_free(r_tmp2); 1793 tcg_temp_free(r_tmp2);
1824 - tcg_temp_free(r_tmp3);  
1825 tcg_gen_br(l2); 1794 tcg_gen_br(l2);
1826 } 1795 }
1827 gen_set_label(l1); 1796 gen_set_label(l1);
@@ -1869,14 +1838,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1869,14 +1838,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1869 tcg_gen_andi_tl(t0, t0, 0x3f); 1838 tcg_gen_andi_tl(t0, t0, 0x3f);
1870 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 1839 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1871 { 1840 {
1872 - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);  
1873 -  
1874 - tcg_gen_movi_tl(r_tmp1, 0x40);  
1875 - tcg_gen_sub_tl(r_tmp1, r_tmp1, t0);  
1876 - tcg_gen_shl_tl(r_tmp1, t1, r_tmp1);  
1877 - tcg_gen_shr_tl(t0, t1, t0);  
1878 - tcg_gen_or_tl(t0, t0, r_tmp1);  
1879 - tcg_temp_free(r_tmp1); 1841 + tcg_gen_rotr_tl(t0, t1, t0);
1880 tcg_gen_br(l2); 1842 tcg_gen_br(l2);
1881 } 1843 }
1882 gen_set_label(l1); 1844 gen_set_label(l1);