gwj / at91sam9263 · Commits

Commit dd5e6304aa93ed9e0ca197a724a90e27379a37ea

Authored by blueswir1
1 parent ab17b46d

Fix cmp/subcc/addcc op bugs reported by Vince Weaver 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4970 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 4 additions and 4 deletions
target-sparc/translate.c
  View file @dd5e630
... ... @@ -386,7 +386,7 @@ static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
386 386 tcg_gen_xori_tl(r_temp, r_temp, -1);
387 387 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
388 388 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
389   - tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
  389 + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
390 390 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
391 391 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
392 392 tcg_temp_free(r_temp);
... ... @@ -423,7 +423,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
423 423 tcg_gen_xori_tl(r_temp, r_temp, -1);
424 424 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
425 425 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
426   - tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
  426 + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
427 427 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
428 428 r_const = tcg_const_i32(TT_TOVF);
429 429 tcg_gen_helper_0_1(raise_exception, r_const);
... ... @@ -584,7 +584,7 @@ static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
584 584 tcg_gen_xor_tl(r_temp, src1, src2);
585 585 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
586 586 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
587   - tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
  587 + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
588 588 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
589 589 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
590 590 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
... ... @@ -619,7 +619,7 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
619 619 tcg_gen_xor_tl(r_temp, src1, src2);
620 620 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
621 621 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
622   - tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
  622 + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
623 623 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
624 624 r_const = tcg_const_i32(TT_TOVF);
625 625 tcg_gen_helper_0_1(raise_exception, r_const);
... ...