gwj / at91sam9263 · Commits

Commit dd53ded3f76a7810c47d66610d5c111b5e5223be

Authored by blueswir1
1 parent a745ec6d

ECC updated based on information released recently by Sun (Robert Reif) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4366 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 160 additions and 80 deletions
hw/eccmemctl.c
  View file @dd53ded
@@ -41,57 +41,87 @@ @@ -41,57 +41,87 @@
41 */ 41 */
42 42
43 /* Register offsets */ 43 /* Register offsets */
44 -#define ECC_FCR_REG 0  
45 -#define ECC_FSR_REG 8  
46 -#define ECC_FAR0_REG 16  
47 -#define ECC_FAR1_REG 20  
48 -#define ECC_DIAG_REG 24 44 +#define ECC_MER 0 /* Memory Enable Register */
  45 +#define ECC_MDR 4 /* Memory Delay Register */
  46 +#define ECC_MFSR 8 /* Memory Fault Status Register */
  47 +#define ECC_VCR 12 /* Video Configuration Register */
  48 +#define ECC_MFAR0 16 /* Memory Fault Address Register 0 */
  49 +#define ECC_MFAR1 20 /* Memory Fault Address Register 1 */
  50 +#define ECC_DR 24 /* Diagnostic Register */
  51 +#define ECC_ECR0 28 /* Event Count Register 0 */
  52 +#define ECC_ECR1 32 /* Event Count Register 1 */
49 53
50 /* ECC fault control register */ 54 /* ECC fault control register */
51 -#define ECC_FCR_EE 0x00000001 /* Enable ECC checking */  
52 -#define ECC_FCR_EI 0x00000010 /* Enable Interrupts on correctable errors */  
53 -#define ECC_FCR_VER 0x0f000000 /* Version */  
54 -#define ECC_FCR_IMPL 0xf0000000 /* Implementation */ 55 +#define ECC_MER_EE 0x00000001 /* Enable ECC checking */
  56 +#define ECC_MER_EI 0x00000002 /* Enable Interrupts on correctable errors */
  57 +#define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
  58 +#define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
  59 +#define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
  60 +#define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
  61 +#define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
  62 +#define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
  63 +#define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
  64 +#define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
  65 +#define ECC_MER_REU 0x00000200 /* Memory Refresh Enable (600MP) */
  66 +#define ECC_MER_MRR 0x000003fc /* MRR mask */
  67 +#define ECC_MEM_A 0x00000400 /* Memory controller addr map select */
  68 +#define ECC_MER_DCI 0x00000800 /* Dsiables Coherent Invalidate ACK */
  69 +#define ECC_MER_VER 0x0f000000 /* Version */
  70 +#define ECC_MER_IMPL 0xf0000000 /* Implementation */
  71 +
  72 +/* ECC memory delay register */
  73 +#define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
  74 +#define ECC_MDR_MI 0x00001c00 /* MIH Delay */
  75 +#define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
  76 +#define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
  77 +#define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
  78 +#define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
  79 +#define ECC_MDR_RSC 0x80000000 /* Refresh load control */
  80 +#define ECC_MDR_MASK 0x7fffffff
55 81
56 /* ECC fault status register */ 82 /* ECC fault status register */
57 -#define ECC_FSR_CE 0x00000001 /* Correctable error */  
58 -#define ECC_FSR_BS 0x00000002 /* C2 graphics bad slot access */  
59 -#define ECC_FSR_TO 0x00000004 /* Timeout on write */  
60 -#define ECC_FSR_UE 0x00000008 /* Uncorrectable error */  
61 -#define ECC_FSR_DW 0x000000f0 /* Index of double word in block */  
62 -#define ECC_FSR_SYND 0x0000ff00 /* Syndrome for correctable error */  
63 -#define ECC_FSR_ME 0x00010000 /* Multiple errors */  
64 -#define ECC_FSR_C2ERR 0x00020000 /* C2 graphics error */ 83 +#define ECC_MFSR_CE 0x00000001 /* Correctable error */
  84 +#define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
  85 +#define ECC_MFSR_TO 0x00000004 /* Timeout on write */
  86 +#define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
  87 +#define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
  88 +#define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
  89 +#define ECC_MFSR_ME 0x00010000 /* Multiple errors */
  90 +#define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
65 91
66 /* ECC fault address register 0 */ 92 /* ECC fault address register 0 */
67 -#define ECC_FAR0_PADDR 0x0000000f /* PA[32-35] */  
68 -#define ECC_FAR0_TYPE 0x000000f0 /* Transaction type */  
69 -#define ECC_FAR0_SIZE 0x00000700 /* Transaction size */  
70 -#define ECC_FAR0_CACHE 0x00000800 /* Mapped cacheable */  
71 -#define ECC_FAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */  
72 -#define ECC_FAR0_BMODE 0x00002000 /* Boot mode */  
73 -#define ECC_FAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */  
74 -#define ECC_FAR0_S 0x08000000 /* Supervisor mode */  
75 -#define ECC_FARO_MID 0xf0000000 /* Module ID */ 93 +#define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
  94 +#define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
  95 +#define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
  96 +#define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
  97 +#define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
  98 +#define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
  99 +#define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
  100 +#define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
  101 +#define ECC_MFARO_MID 0xf0000000 /* Module ID */
76 102
77 /* ECC diagnostic register */ 103 /* ECC diagnostic register */
78 -#define ECC_DIAG_CBX 0x00000001  
79 -#define ECC_DIAG_CB0 0x00000002  
80 -#define ECC_DIAG_CB1 0x00000004  
81 -#define ECC_DIAG_CB2 0x00000008  
82 -#define ECC_DIAG_CB4 0x00000010  
83 -#define ECC_DIAG_CB8 0x00000020  
84 -#define ECC_DIAG_CB16 0x00000040  
85 -#define ECC_DIAG_CB32 0x00000080  
86 -#define ECC_DIAG_DMODE 0x00000c00  
87 -  
88 -#define ECC_NREGS 8 104 +#define ECC_DR_CBX 0x00000001
  105 +#define ECC_DR_CB0 0x00000002
  106 +#define ECC_DR_CB1 0x00000004
  107 +#define ECC_DR_CB2 0x00000008
  108 +#define ECC_DR_CB4 0x00000010
  109 +#define ECC_DR_CB8 0x00000020
  110 +#define ECC_DR_CB16 0x00000040
  111 +#define ECC_DR_CB32 0x00000080
  112 +#define ECC_DR_DMODE 0x00000c00
  113 +
  114 +#define ECC_NREGS 9
89 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) 115 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
90 -#define ECC_ADDR_MASK (ECC_SIZE - 1) 116 +#define ECC_ADDR_MASK 0x1f
  117 +
  118 +#define ECC_DIAG_SIZE 4
  119 +#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
91 120
92 typedef struct ECCState { 121 typedef struct ECCState {
93 qemu_irq irq; 122 qemu_irq irq;
94 uint32_t regs[ECC_NREGS]; 123 uint32_t regs[ECC_NREGS];
  124 + uint8_t diag[ECC_DIAG_SIZE];
95 } ECCState; 125 } ECCState;
96 126
97 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 127 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
@@ -99,38 +129,34 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) @@ -99,38 +129,34 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
99 ECCState *s = opaque; 129 ECCState *s = opaque;
100 130
101 switch (addr & ECC_ADDR_MASK) { 131 switch (addr & ECC_ADDR_MASK) {
102 - case ECC_FCR_REG:  
103 - s->regs[0] = (s->regs[0] & (ECC_FCR_VER | ECC_FCR_IMPL)) |  
104 - (val & ~(ECC_FCR_VER | ECC_FCR_IMPL));  
105 - DPRINTF("Write fault control %08x\n", val); 132 + case ECC_MER:
  133 + s->regs[0] = (s->regs[0] & (ECC_MER_VER | ECC_MER_IMPL)) |
  134 + (val & ~(ECC_MER_VER | ECC_MER_IMPL));
  135 + DPRINTF("Write memory enable %08x\n", val);
106 break; 136 break;
107 - case 4:  
108 - s->regs[1] = val;  
109 - DPRINTF("Write reg[1] %08x\n", val); 137 + case ECC_MDR:
  138 + s->regs[1] = val & ECC_MDR_MASK;
  139 + DPRINTF("Write memory delay %08x\n", val);
110 break; 140 break;
111 - case ECC_FSR_REG: 141 + case ECC_MFSR:
112 s->regs[2] = val; 142 s->regs[2] = val;
113 - DPRINTF("Write fault status %08x\n", val); 143 + DPRINTF("Write memory fault status %08x\n", val);
114 break; 144 break;
115 - case 12: 145 + case ECC_VCR:
116 s->regs[3] = val; 146 s->regs[3] = val;
117 - DPRINTF("Write reg[3] %08x\n", val);  
118 - break;  
119 - case ECC_FAR0_REG:  
120 - s->regs[4] = val;  
121 - DPRINTF("Write fault address 0 %08x\n", val); 147 + DPRINTF("Write slot configuration %08x\n", val);
122 break; 148 break;
123 - case ECC_FAR1_REG:  
124 - s->regs[5] = val;  
125 - DPRINTF("Write fault address 1 %08x\n", val);  
126 - break;  
127 - case ECC_DIAG_REG: 149 + case ECC_DR:
128 s->regs[6] = val; 150 s->regs[6] = val;
129 - DPRINTF("Write diag %08x\n", val); 151 + DPRINTF("Write diagnosiic %08x\n", val);
  152 + break;
  153 + case ECC_ECR0:
  154 + s->regs[7] = val;
  155 + DPRINTF("Write event count 1 %08x\n", val);
130 break; 156 break;
131 - case 28: 157 + case ECC_ECR1:
132 s->regs[7] = val; 158 s->regs[7] = val;
133 - DPRINTF("Write reg[7] %08x\n", val); 159 + DPRINTF("Write event count 2 %08x\n", val);
134 break; 160 break;
135 } 161 }
136 } 162 }
@@ -141,37 +167,41 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) @@ -141,37 +167,41 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
141 uint32_t ret = 0; 167 uint32_t ret = 0;
142 168
143 switch (addr & ECC_ADDR_MASK) { 169 switch (addr & ECC_ADDR_MASK) {
144 - case ECC_FCR_REG: 170 + case ECC_MER:
145 ret = s->regs[0]; 171 ret = s->regs[0];
146 - DPRINTF("Read enable %08x\n", ret); 172 + DPRINTF("Read memory enable %08x\n", ret);
147 break; 173 break;
148 - case 4: 174 + case ECC_MDR:
149 ret = s->regs[1]; 175 ret = s->regs[1];
150 - DPRINTF("Read register[1] %08x\n", ret); 176 + DPRINTF("Read memory delay %08x\n", ret);
151 break; 177 break;
152 - case ECC_FSR_REG: 178 + case ECC_MFSR:
153 ret = s->regs[2]; 179 ret = s->regs[2];
154 - DPRINTF("Read fault status %08x\n", ret); 180 + DPRINTF("Read memory fault status %08x\n", ret);
155 break; 181 break;
156 - case 12: 182 + case ECC_VCR:
157 ret = s->regs[3]; 183 ret = s->regs[3];
158 - DPRINTF("Read reg[3] %08x\n", ret); 184 + DPRINTF("Read slot configuration %08x\n", ret);
159 break; 185 break;
160 - case ECC_FAR0_REG: 186 + case ECC_MFAR0:
161 ret = s->regs[4]; 187 ret = s->regs[4];
162 - DPRINTF("Read fault address 0 %08x\n", ret); 188 + DPRINTF("Read memory fault address 0 %08x\n", ret);
163 break; 189 break;
164 - case ECC_FAR1_REG: 190 + case ECC_MFAR1:
165 ret = s->regs[5]; 191 ret = s->regs[5];
166 - DPRINTF("Read fault address 1 %08x\n", ret); 192 + DPRINTF("Read memory fault address 1 %08x\n", ret);
167 break; 193 break;
168 - case ECC_DIAG_REG: 194 + case ECC_DR:
169 ret = s->regs[6]; 195 ret = s->regs[6];
170 - DPRINTF("Read diag %08x\n", ret); 196 + DPRINTF("Read diagnostic %08x\n", ret);
171 break; 197 break;
172 - case 28: 198 + case ECC_ECR0:
173 ret = s->regs[7]; 199 ret = s->regs[7];
174 - DPRINTF("Read reg[7] %08x\n", ret); 200 + DPRINTF("Read event count 1 %08x\n", ret);
  201 + break;
  202 + case ECC_ECR1:
  203 + ret = s->regs[7];
  204 + DPRINTF("Read event count 2 %08x\n", ret);
175 break; 205 break;
176 } 206 }
177 return ret; 207 return ret;
@@ -189,17 +219,49 @@ static CPUWriteMemoryFunc *ecc_mem_write[3] = { @@ -189,17 +219,49 @@ static CPUWriteMemoryFunc *ecc_mem_write[3] = {
189 ecc_mem_writel, 219 ecc_mem_writel,
190 }; 220 };
191 221
  222 +static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
  223 + uint32_t val)
  224 +{
  225 + ECCState *s = opaque;
  226 +
  227 + DPRINTF("Write diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), val);
  228 + s->diag[addr & ECC_DIAG_MASK] = val;
  229 +}
  230 +
  231 +static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
  232 +{
  233 + ECCState *s = opaque;
  234 + uint32_t ret = s->diag[addr & ECC_DIAG_MASK];
  235 + DPRINTF("Read diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), ret);
  236 + return ret;
  237 +}
  238 +
  239 +static CPUReadMemoryFunc *ecc_diag_mem_read[3] = {
  240 + ecc_diag_mem_readb,
  241 + NULL,
  242 + NULL,
  243 +};
  244 +
  245 +static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = {
  246 + ecc_diag_mem_writeb,
  247 + NULL,
  248 + NULL,
  249 +};
  250 +
192 static int ecc_load(QEMUFile *f, void *opaque, int version_id) 251 static int ecc_load(QEMUFile *f, void *opaque, int version_id)
193 { 252 {
194 ECCState *s = opaque; 253 ECCState *s = opaque;
195 int i; 254 int i;
196 255
197 - if (version_id != 1) 256 + if (version_id != 2)
198 return -EINVAL; 257 return -EINVAL;
199 258
200 for (i = 0; i < ECC_NREGS; i++) 259 for (i = 0; i < ECC_NREGS; i++)
201 qemu_get_be32s(f, &s->regs[i]); 260 qemu_get_be32s(f, &s->regs[i]);
202 261
  262 + for (i = 0; i < ECC_DIAG_SIZE; i++)
  263 + qemu_get_8s(f, &s->diag[i]);
  264 +
203 return 0; 265 return 0;
204 } 266 }
205 267
@@ -210,6 +272,9 @@ static void ecc_save(QEMUFile *f, void *opaque) @@ -210,6 +272,9 @@ static void ecc_save(QEMUFile *f, void *opaque)
210 272
211 for (i = 0; i < ECC_NREGS; i++) 273 for (i = 0; i < ECC_NREGS; i++)
212 qemu_put_be32s(f, &s->regs[i]); 274 qemu_put_be32s(f, &s->regs[i]);
  275 +
  276 + for (i = 0; i < ECC_DIAG_SIZE; i++)
  277 + qemu_put_8s(f, &s->diag[i]);
213 } 278 }
214 279
215 static void ecc_reset(void *opaque) 280 static void ecc_reset(void *opaque)
@@ -217,7 +282,16 @@ static void ecc_reset(void *opaque) @@ -217,7 +282,16 @@ static void ecc_reset(void *opaque)
217 ECCState *s = opaque; 282 ECCState *s = opaque;
218 int i; 283 int i;
219 284
220 - s->regs[ECC_FCR_REG] &= (ECC_FCR_VER | ECC_FCR_IMPL); 285 + s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL);
  286 + s->regs[ECC_MER] |= ECC_MER_MRR;
  287 + s->regs[ECC_MDR] = 0x20;
  288 + s->regs[ECC_MFSR] = 0;
  289 + s->regs[ECC_VCR] = 0;
  290 + s->regs[ECC_MFAR0] = 0x07c00000;
  291 + s->regs[ECC_MFAR1] = 0;
  292 + s->regs[ECC_DR] = 0;
  293 + s->regs[ECC_ECR0] = 0;
  294 + s->regs[ECC_ECR1] = 0;
221 295
222 for (i = 1; i < ECC_NREGS; i++) 296 for (i = 1; i < ECC_NREGS; i++)
223 s->regs[i] = 0; 297 s->regs[i] = 0;
@@ -237,7 +311,13 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) @@ -237,7 +311,13 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
237 311
238 ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s); 312 ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
239 cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory); 313 cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
240 - register_savevm("ECC", base, 1, ecc_save, ecc_load, s); 314 + if (version == 0) { // SS-600MP only
  315 + ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
  316 + ecc_diag_mem_write, s);
  317 + cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
  318 + ecc_io_memory);
  319 + }
  320 + register_savevm("ECC", base, 2, ecc_save, ecc_load, s);
241 qemu_register_reset(ecc_reset, s); 321 qemu_register_reset(ecc_reset, s);
242 ecc_reset(s); 322 ecc_reset(s);
243 return s; 323 return s;