gwj / at91sam9263 · Commits

Commit dcf2490568c4515e9431abc7d61389f86e065b52

Authored by blueswir1
1 parent 9664d928

Convert fmovr to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4013 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 27 additions and 15 deletions
target-sparc/translate.c
  View file @dcf2490
@@ -1711,38 +1711,50 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1711,38 +1711,50 @@ static void disas_sparc_insn(DisasContext * dc)
1711 xop = GET_FIELD(insn, 18, 26); 1711 xop = GET_FIELD(insn, 18, 26);
1712 #ifdef TARGET_SPARC64 1712 #ifdef TARGET_SPARC64
1713 if ((xop & 0x11f) == 0x005) { // V9 fmovsr 1713 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
  1714 + TCGv r_zero;
  1715 + int l1;
  1716 +
  1717 + l1 = gen_new_label();
  1718 + r_zero = tcg_temp_new(TCG_TYPE_TL);
1714 cond = GET_FIELD_SP(insn, 14, 17); 1719 cond = GET_FIELD_SP(insn, 14, 17);
1715 - gen_op_load_fpr_FT0(rd);  
1716 - gen_op_load_fpr_FT1(rs2);  
1717 rs1 = GET_FIELD(insn, 13, 17); 1720 rs1 = GET_FIELD(insn, 13, 17);
1718 gen_movl_reg_T0(rs1); 1721 gen_movl_reg_T0(rs1);
1719 - flush_T2(dc);  
1720 - gen_cond_reg(cond);  
1721 - gen_op_fmovs_cc(); 1722 + tcg_gen_movi_tl(r_zero, 0);
  1723 + tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
  1724 + gen_op_load_fpr_FT1(rs2);
1722 gen_op_store_FT0_fpr(rd); 1725 gen_op_store_FT0_fpr(rd);
  1726 + gen_set_label(l1);
1723 break; 1727 break;
1724 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr 1728 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
  1729 + TCGv r_zero;
  1730 + int l1;
  1731 +
  1732 + l1 = gen_new_label();
  1733 + r_zero = tcg_temp_new(TCG_TYPE_TL);
1725 cond = GET_FIELD_SP(insn, 14, 17); 1734 cond = GET_FIELD_SP(insn, 14, 17);
1726 - gen_op_load_fpr_DT0(DFPREG(rd));  
1727 - gen_op_load_fpr_DT1(DFPREG(rs2));  
1728 - flush_T2(dc);  
1729 rs1 = GET_FIELD(insn, 13, 17); 1735 rs1 = GET_FIELD(insn, 13, 17);
1730 gen_movl_reg_T0(rs1); 1736 gen_movl_reg_T0(rs1);
1731 - gen_cond_reg(cond);  
1732 - gen_op_fmovs_cc(); 1737 + tcg_gen_movi_tl(r_zero, 0);
  1738 + tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
  1739 + gen_op_load_fpr_DT1(DFPREG(rs2));
1733 gen_op_store_DT0_fpr(DFPREG(rd)); 1740 gen_op_store_DT0_fpr(DFPREG(rd));
  1741 + gen_set_label(l1);
1734 break; 1742 break;
1735 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr 1743 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1736 #if defined(CONFIG_USER_ONLY) 1744 #if defined(CONFIG_USER_ONLY)
  1745 + TCGv r_zero;
  1746 + int l1;
  1747 +
  1748 + l1 = gen_new_label();
  1749 + r_zero = tcg_temp_new(TCG_TYPE_TL);
1737 cond = GET_FIELD_SP(insn, 14, 17); 1750 cond = GET_FIELD_SP(insn, 14, 17);
1738 - gen_op_load_fpr_QT0(QFPREG(rd));  
1739 - gen_op_load_fpr_QT1(QFPREG(rs2));  
1740 - flush_T2(dc);  
1741 rs1 = GET_FIELD(insn, 13, 17); 1751 rs1 = GET_FIELD(insn, 13, 17);
1742 gen_movl_reg_T0(rs1); 1752 gen_movl_reg_T0(rs1);
1743 - gen_cond_reg(cond);  
1744 - gen_op_fmovq_cc(); 1753 + tcg_gen_movi_tl(r_zero, 0);
  1754 + tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
  1755 + gen_op_load_fpr_QT1(QFPREG(rs2));
1745 gen_op_store_QT0_fpr(QFPREG(rd)); 1756 gen_op_store_QT0_fpr(QFPREG(rd));
  1757 + gen_set_label(l1);
1746 break; 1758 break;
1747 #else 1759 #else
1748 goto nfpu_insn; 1760 goto nfpu_insn;