gwj / at91sam9263 · Commits

Commit dc99a3f2e856e6d2c2142538b756eb72de0af51a

Authored by blueswir1
1 parent 02cb1585

Convert condition code changing versions of add, sub, logic, and div to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4052 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 427 additions and 453 deletions
target-sparc/cpu.h
  View file @dc99a3f
... ... @@ -184,6 +184,11 @@ typedef struct CPUSPARCState {
184 184 target_ulong pc; /* program counter */
185 185 target_ulong npc; /* next program counter */
186 186 target_ulong y; /* multiply/divide register */
  187 +
  188 + /* emulator internal flags handling */
  189 + target_ulong cc_src;
  190 + target_ulong cc_dst;
  191 +
187 192 uint32_t psr; /* processor state register */
188 193 target_ulong fsr; /* FPU state register */
189 194 uint32_t cwp; /* index of current register window (extracted
... ...
target-sparc/op.c
  View file @dc99a3f
... ... @@ -171,389 +171,6 @@
171 171  
172 172 #define FLAG_SET(x) ((env->psr&x)?1:0)
173 173  
174   -void OPPROTO op_add_T1_T0_cc(void)
175   -{
176   - target_ulong src1;
177   -
178   - src1 = T0;
179   - T0 += T1;
180   - env->psr = 0;
181   -#ifdef TARGET_SPARC64
182   - if (!(T0 & 0xffffffff))
183   - env->psr |= PSR_ZERO;
184   - if ((int32_t) T0 < 0)
185   - env->psr |= PSR_NEG;
186   - if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
187   - env->psr |= PSR_CARRY;
188   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
189   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
190   - env->psr |= PSR_OVF;
191   -
192   - env->xcc = 0;
193   - if (!T0)
194   - env->xcc |= PSR_ZERO;
195   - if ((int64_t) T0 < 0)
196   - env->xcc |= PSR_NEG;
197   - if (T0 < src1)
198   - env->xcc |= PSR_CARRY;
199   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
200   - env->xcc |= PSR_OVF;
201   -#else
202   - if (!T0)
203   - env->psr |= PSR_ZERO;
204   - if ((int32_t) T0 < 0)
205   - env->psr |= PSR_NEG;
206   - if (T0 < src1)
207   - env->psr |= PSR_CARRY;
208   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
209   - env->psr |= PSR_OVF;
210   -#endif
211   - FORCE_RET();
212   -}
213   -
214   -void OPPROTO op_addx_T1_T0_cc(void)
215   -{
216   - target_ulong src1;
217   - src1 = T0;
218   - if (FLAG_SET(PSR_CARRY))
219   - {
220   - T0 += T1 + 1;
221   - env->psr = 0;
222   -#ifdef TARGET_SPARC64
223   - if ((T0 & 0xffffffff) <= (src1 & 0xffffffff))
224   - env->psr |= PSR_CARRY;
225   - env->xcc = 0;
226   - if (T0 <= src1)
227   - env->xcc |= PSR_CARRY;
228   -#else
229   - if (T0 <= src1)
230   - env->psr |= PSR_CARRY;
231   -#endif
232   - }
233   - else
234   - {
235   - T0 += T1;
236   - env->psr = 0;
237   -#ifdef TARGET_SPARC64
238   - if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
239   - env->psr |= PSR_CARRY;
240   - env->xcc = 0;
241   - if (T0 < src1)
242   - env->xcc |= PSR_CARRY;
243   -#else
244   - if (T0 < src1)
245   - env->psr |= PSR_CARRY;
246   -#endif
247   - }
248   -#ifdef TARGET_SPARC64
249   - if (!(T0 & 0xffffffff))
250   - env->psr |= PSR_ZERO;
251   - if ((int32_t) T0 < 0)
252   - env->psr |= PSR_NEG;
253   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
254   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
255   - env->psr |= PSR_OVF;
256   -
257   - if (!T0)
258   - env->xcc |= PSR_ZERO;
259   - if ((int64_t) T0 < 0)
260   - env->xcc |= PSR_NEG;
261   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
262   - env->xcc |= PSR_OVF;
263   -#else
264   - if (!T0)
265   - env->psr |= PSR_ZERO;
266   - if ((int32_t) T0 < 0)
267   - env->psr |= PSR_NEG;
268   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
269   - env->psr |= PSR_OVF;
270   -#endif
271   - FORCE_RET();
272   -}
273   -
274   -void OPPROTO op_tadd_T1_T0_cc(void)
275   -{
276   - target_ulong src1;
277   -
278   - src1 = T0;
279   - T0 += T1;
280   - env->psr = 0;
281   -#ifdef TARGET_SPARC64
282   - if (!(T0 & 0xffffffff))
283   - env->psr |= PSR_ZERO;
284   - if ((int32_t) T0 < 0)
285   - env->psr |= PSR_NEG;
286   - if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
287   - env->psr |= PSR_CARRY;
288   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
289   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
290   - env->psr |= PSR_OVF;
291   - if ((src1 & 0x03) || (T1 & 0x03))
292   - env->psr |= PSR_OVF;
293   -
294   - env->xcc = 0;
295   - if (!T0)
296   - env->xcc |= PSR_ZERO;
297   - if ((int64_t) T0 < 0)
298   - env->xcc |= PSR_NEG;
299   - if (T0 < src1)
300   - env->xcc |= PSR_CARRY;
301   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
302   - env->xcc |= PSR_OVF;
303   -#else
304   - if (!T0)
305   - env->psr |= PSR_ZERO;
306   - if ((int32_t) T0 < 0)
307   - env->psr |= PSR_NEG;
308   - if (T0 < src1)
309   - env->psr |= PSR_CARRY;
310   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
311   - env->psr |= PSR_OVF;
312   - if ((src1 & 0x03) || (T1 & 0x03))
313   - env->psr |= PSR_OVF;
314   -#endif
315   - FORCE_RET();
316   -}
317   -
318   -void OPPROTO op_tadd_T1_T0_ccTV(void)
319   -{
320   - target_ulong src1;
321   -
322   - if ((T0 & 0x03) || (T1 & 0x03)) {
323   - raise_exception(TT_TOVF);
324   - FORCE_RET();
325   - return;
326   - }
327   -
328   - src1 = T0;
329   - T0 += T1;
330   -
331   -#ifdef TARGET_SPARC64
332   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
333   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
334   - raise_exception(TT_TOVF);
335   -#else
336   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
337   - raise_exception(TT_TOVF);
338   -#endif
339   -
340   - env->psr = 0;
341   -#ifdef TARGET_SPARC64
342   - if (!(T0 & 0xffffffff))
343   - env->psr |= PSR_ZERO;
344   - if ((int32_t) T0 < 0)
345   - env->psr |= PSR_NEG;
346   - if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
347   - env->psr |= PSR_CARRY;
348   -
349   - env->xcc = 0;
350   - if (!T0)
351   - env->xcc |= PSR_ZERO;
352   - if ((int64_t) T0 < 0)
353   - env->xcc |= PSR_NEG;
354   - if (T0 < src1)
355   - env->xcc |= PSR_CARRY;
356   -#else
357   - if (!T0)
358   - env->psr |= PSR_ZERO;
359   - if ((int32_t) T0 < 0)
360   - env->psr |= PSR_NEG;
361   - if (T0 < src1)
362   - env->psr |= PSR_CARRY;
363   -#endif
364   - FORCE_RET();
365   -}
366   -
367   -void OPPROTO op_sub_T1_T0_cc(void)
368   -{
369   - target_ulong src1;
370   -
371   - src1 = T0;
372   - T0 -= T1;
373   - env->psr = 0;
374   -#ifdef TARGET_SPARC64
375   - if (!(T0 & 0xffffffff))
376   - env->psr |= PSR_ZERO;
377   - if ((int32_t) T0 < 0)
378   - env->psr |= PSR_NEG;
379   - if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
380   - env->psr |= PSR_CARRY;
381   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
382   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
383   - env->psr |= PSR_OVF;
384   -
385   - env->xcc = 0;
386   - if (!T0)
387   - env->xcc |= PSR_ZERO;
388   - if ((int64_t) T0 < 0)
389   - env->xcc |= PSR_NEG;
390   - if (src1 < T1)
391   - env->xcc |= PSR_CARRY;
392   - if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
393   - env->xcc |= PSR_OVF;
394   -#else
395   - if (!T0)
396   - env->psr |= PSR_ZERO;
397   - if ((int32_t) T0 < 0)
398   - env->psr |= PSR_NEG;
399   - if (src1 < T1)
400   - env->psr |= PSR_CARRY;
401   - if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
402   - env->psr |= PSR_OVF;
403   -#endif
404   - FORCE_RET();
405   -}
406   -
407   -void OPPROTO op_subx_T1_T0_cc(void)
408   -{
409   - target_ulong src1;
410   - src1 = T0;
411   - if (FLAG_SET(PSR_CARRY))
412   - {
413   - T0 -= T1 + 1;
414   - env->psr = 0;
415   -#ifdef TARGET_SPARC64
416   - if ((src1 & 0xffffffff) <= (T1 & 0xffffffff))
417   - env->psr |= PSR_CARRY;
418   - env->xcc = 0;
419   - if (src1 <= T1)
420   - env->xcc |= PSR_CARRY;
421   -#else
422   - if (src1 <= T1)
423   - env->psr |= PSR_CARRY;
424   -#endif
425   - }
426   - else
427   - {
428   - T0 -= T1;
429   - env->psr = 0;
430   -#ifdef TARGET_SPARC64
431   - if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
432   - env->psr |= PSR_CARRY;
433   - env->xcc = 0;
434   - if (src1 < T1)
435   - env->xcc |= PSR_CARRY;
436   -#else
437   - if (src1 < T1)
438   - env->psr |= PSR_CARRY;
439   -#endif
440   - }
441   -#ifdef TARGET_SPARC64
442   - if (!(T0 & 0xffffffff))
443   - env->psr |= PSR_ZERO;
444   - if ((int32_t) T0 < 0)
445   - env->psr |= PSR_NEG;
446   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
447   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
448   - env->psr |= PSR_OVF;
449   -
450   - if (!T0)
451   - env->xcc |= PSR_ZERO;
452   - if ((int64_t) T0 < 0)
453   - env->xcc |= PSR_NEG;
454   - if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
455   - env->xcc |= PSR_OVF;
456   -#else
457   - if (!T0)
458   - env->psr |= PSR_ZERO;
459   - if ((int32_t) T0 < 0)
460   - env->psr |= PSR_NEG;
461   - if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
462   - env->psr |= PSR_OVF;
463   -#endif
464   - FORCE_RET();
465   -}
466   -
467   -void OPPROTO op_tsub_T1_T0_cc(void)
468   -{
469   - target_ulong src1;
470   -
471   - src1 = T0;
472   - T0 -= T1;
473   - env->psr = 0;
474   -#ifdef TARGET_SPARC64
475   - if (!(T0 & 0xffffffff))
476   - env->psr |= PSR_ZERO;
477   - if ((int32_t) T0 < 0)
478   - env->psr |= PSR_NEG;
479   - if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
480   - env->psr |= PSR_CARRY;
481   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
482   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
483   - env->psr |= PSR_OVF;
484   - if ((src1 & 0x03) || (T1 & 0x03))
485   - env->psr |= PSR_OVF;
486   -
487   - env->xcc = 0;
488   - if (!T0)
489   - env->xcc |= PSR_ZERO;
490   - if ((int64_t) T0 < 0)
491   - env->xcc |= PSR_NEG;
492   - if (src1 < T1)
493   - env->xcc |= PSR_CARRY;
494   - if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
495   - env->xcc |= PSR_OVF;
496   -#else
497   - if (!T0)
498   - env->psr |= PSR_ZERO;
499   - if ((int32_t) T0 < 0)
500   - env->psr |= PSR_NEG;
501   - if (src1 < T1)
502   - env->psr |= PSR_CARRY;
503   - if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
504   - env->psr |= PSR_OVF;
505   - if ((src1 & 0x03) || (T1 & 0x03))
506   - env->psr |= PSR_OVF;
507   -#endif
508   - FORCE_RET();
509   -}
510   -
511   -void OPPROTO op_tsub_T1_T0_ccTV(void)
512   -{
513   - target_ulong src1;
514   -
515   - if ((T0 & 0x03) || (T1 & 0x03))
516   - raise_exception(TT_TOVF);
517   -
518   - src1 = T0;
519   - T0 -= T1;
520   -
521   -#ifdef TARGET_SPARC64
522   - if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
523   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
524   - raise_exception(TT_TOVF);
525   -#else
526   - if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
527   - raise_exception(TT_TOVF);
528   -#endif
529   -
530   - env->psr = 0;
531   -#ifdef TARGET_SPARC64
532   - if (!(T0 & 0xffffffff))
533   - env->psr |= PSR_ZERO;
534   - if ((int32_t) T0 < 0)
535   - env->psr |= PSR_NEG;
536   - if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
537   - env->psr |= PSR_CARRY;
538   -
539   - env->xcc = 0;
540   - if (!T0)
541   - env->xcc |= PSR_ZERO;
542   - if ((int64_t) T0 < 0)
543   - env->xcc |= PSR_NEG;
544   - if (src1 < T1)
545   - env->xcc |= PSR_CARRY;
546   -#else
547   - if (!T0)
548   - env->psr |= PSR_ZERO;
549   - if ((int32_t) T0 < 0)
550   - env->psr |= PSR_NEG;
551   - if (src1 < T1)
552   - env->psr |= PSR_CARRY;
553   -#endif
554   - FORCE_RET();
555   -}
556   -
557 174 void OPPROTO op_umul_T1_T0(void)
558 175 {
559 176 uint64_t res;
... ... @@ -652,33 +269,6 @@ void OPPROTO op_sdiv_T1_T0(void)
652 269 FORCE_RET();
653 270 }
654 271  
655   -void OPPROTO op_div_cc(void)
656   -{
657   - env->psr = 0;
658   -#ifdef TARGET_SPARC64
659   - if (!T0)
660   - env->psr |= PSR_ZERO;
661   - if ((int32_t) T0 < 0)
662   - env->psr |= PSR_NEG;
663   - if (T1)
664   - env->psr |= PSR_OVF;
665   -
666   - env->xcc = 0;
667   - if (!T0)
668   - env->xcc |= PSR_ZERO;
669   - if ((int64_t) T0 < 0)
670   - env->xcc |= PSR_NEG;
671   -#else
672   - if (!T0)
673   - env->psr |= PSR_ZERO;
674   - if ((int32_t) T0 < 0)
675   - env->psr |= PSR_NEG;
676   - if (T1)
677   - env->psr |= PSR_OVF;
678   -#endif
679   - FORCE_RET();
680   -}
681   -
682 272 #ifdef TARGET_SPARC64
683 273 void OPPROTO op_udivx_T1_T0(void)
684 274 {
... ... @@ -702,29 +292,6 @@ void OPPROTO op_sdivx_T1_T0(void)
702 292 }
703 293 #endif
704 294  
705   -void OPPROTO op_logic_T0_cc(void)
706   -{
707   - env->psr = 0;
708   -#ifdef TARGET_SPARC64
709   - if (!(T0 & 0xffffffff))
710   - env->psr |= PSR_ZERO;
711   - if ((int32_t) T0 < 0)
712   - env->psr |= PSR_NEG;
713   -
714   - env->xcc = 0;
715   - if (!T0)
716   - env->xcc |= PSR_ZERO;
717   - if ((int64_t) T0 < 0)
718   - env->xcc |= PSR_NEG;
719   -#else
720   - if (!T0)
721   - env->psr |= PSR_ZERO;
722   - if ((int32_t) T0 < 0)
723   - env->psr |= PSR_NEG;
724   -#endif
725   - FORCE_RET();
726   -}
727   -
728 295 /* Load and store */
729 296 #define MEMSUFFIX _raw
730 297 #include "op_mem.h"
... ...
target-sparc/translate.c
  View file @dc99a3f
... ... @@ -46,7 +46,10 @@
46 46 according to jump_pc[T2] */
47 47  
48 48 /* global register indexes */
49   -static TCGv cpu_env, cpu_T[3], cpu_regwptr;
  49 +static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst, cpu_psr;
  50 +#ifdef TARGET_SPARC64
  51 +static TCGv cpu_xcc;
  52 +#endif
50 53 /* local register indexes (only used inside old micro ops) */
51 54 static TCGv cpu_tmp0;
52 55  
... ... @@ -356,6 +359,407 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv src)
356 359 tcg_gen_andi_tl(reg, reg, 0x1);
357 360 }
358 361  
  362 +static inline void gen_op_exception(int exception)
  363 +{
  364 + TCGv r_except;
  365 +
  366 + r_except = tcg_temp_new(TCG_TYPE_I32);
  367 + tcg_gen_movi_i32(r_except, exception);
  368 + tcg_gen_helper_0_1(raise_exception, r_except);
  369 +}
  370 +
  371 +static inline void gen_cc_clear(void)
  372 +{
  373 + tcg_gen_movi_i32(cpu_psr, 0);
  374 +#ifdef TARGET_SPARC64
  375 + tcg_gen_movi_i32(cpu_xcc, 0);
  376 +#endif
  377 +}
  378 +
  379 +/* old op:
  380 + if (!T0)
  381 + env->psr |= PSR_ZERO;
  382 + if ((int32_t) T0 < 0)
  383 + env->psr |= PSR_NEG;
  384 +*/
  385 +static inline void gen_cc_NZ(TCGv dst)
  386 +{
  387 + int l1, l2;
  388 + TCGv r_zero;
  389 +
  390 + l1 = gen_new_label();
  391 + l2 = gen_new_label();
  392 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  393 + tcg_gen_movi_tl(r_zero, 0);
  394 + tcg_gen_brcond_i32(TCG_COND_NE, dst, r_zero, l1);
  395 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
  396 + gen_set_label(l1);
  397 + tcg_gen_brcond_i32(TCG_COND_GE, dst, r_zero, l2);
  398 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
  399 + gen_set_label(l2);
  400 +#ifdef TARGET_SPARC64
  401 + {
  402 + int l3, l4;
  403 +
  404 + l3 = gen_new_label();
  405 + l4 = gen_new_label();
  406 + tcg_gen_brcond_tl(TCG_COND_NE, dst, r_zero, l3);
  407 + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
  408 + gen_set_label(l3);
  409 + tcg_gen_brcond_tl(TCG_COND_GE, dst, r_zero, l4);
  410 + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
  411 + gen_set_label(l4);
  412 + }
  413 +#endif
  414 +}
  415 +
  416 +/* old op:
  417 + if (T0 < src1)
  418 + env->psr |= PSR_CARRY;
  419 +*/
  420 +static inline void gen_cc_C_add(TCGv dst, TCGv src1)
  421 +{
  422 + int l1;
  423 +
  424 + l1 = gen_new_label();
  425 + tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
  426 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
  427 + gen_set_label(l1);
  428 +#ifdef TARGET_SPARC64
  429 + {
  430 + int l2;
  431 +
  432 + l2 = gen_new_label();
  433 + tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
  434 + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
  435 + gen_set_label(l2);
  436 + }
  437 +#endif
  438 +}
  439 +
  440 +/* old op:
  441 + if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
  442 + env->psr |= PSR_OVF;
  443 +*/
  444 +static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
  445 +{
  446 + TCGv r_temp, r_temp2, r_temp3, r_zero;
  447 + int l1;
  448 +
  449 + l1 = gen_new_label();
  450 +
  451 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  452 + r_temp2 = tcg_temp_new(TCG_TYPE_TL);
  453 + r_temp3 = tcg_temp_new(TCG_TYPE_TL);
  454 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  455 + tcg_gen_movi_tl(r_zero, 0);
  456 + tcg_gen_xor_tl(r_temp, src1, src2);
  457 + tcg_gen_xori_tl(r_temp, r_temp, -1);
  458 + tcg_gen_xor_tl(r_temp2, src1, dst);
  459 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  460 + tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
  461 + tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
  462 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
  463 + gen_set_label(l1);
  464 +#ifdef TARGET_SPARC64
  465 + {
  466 + int l2;
  467 +
  468 + l2 = gen_new_label();
  469 + tcg_gen_movi_tl(r_zero, 0);
  470 + tcg_gen_xor_tl(r_temp, src1, src2);
  471 + tcg_gen_xori_tl(r_temp, r_temp, -1);
  472 + tcg_gen_xor_tl(r_temp2, src1, dst);
  473 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  474 + tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
  475 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
  476 + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
  477 + gen_set_label(l2);
  478 + }
  479 +#endif
  480 +}
  481 +
  482 +static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
  483 +{
  484 + TCGv r_temp, r_temp2, r_temp3, r_zero;
  485 + int l1;
  486 +
  487 + l1 = gen_new_label();
  488 +
  489 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  490 + r_temp2 = tcg_temp_new(TCG_TYPE_TL);
  491 + r_temp3 = tcg_temp_new(TCG_TYPE_TL);
  492 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  493 + tcg_gen_movi_tl(r_zero, 0);
  494 + tcg_gen_xor_tl(r_temp, src1, src2);
  495 + tcg_gen_xori_tl(r_temp, r_temp, -1);
  496 + tcg_gen_xor_tl(r_temp2, src1, dst);
  497 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  498 + tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
  499 + tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
  500 + gen_op_exception(TT_TOVF);
  501 + gen_set_label(l1);
  502 +#ifdef TARGET_SPARC64
  503 + {
  504 + int l2;
  505 +
  506 + l2 = gen_new_label();
  507 + tcg_gen_movi_tl(r_zero, 0);
  508 + tcg_gen_xor_tl(r_temp, src1, src2);
  509 + tcg_gen_xori_tl(r_temp, r_temp, -1);
  510 + tcg_gen_xor_tl(r_temp2, src1, dst);
  511 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  512 + tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
  513 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
  514 + gen_op_exception(TT_TOVF);
  515 + gen_set_label(l2);
  516 + }
  517 +#endif
  518 +}
  519 +
  520 +static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
  521 +{
  522 + int l1;
  523 + TCGv r_zero, r_temp;
  524 +
  525 + l1 = gen_new_label();
  526 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  527 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  528 + tcg_gen_movi_tl(r_zero, 0);
  529 + tcg_gen_or_tl(r_temp, src1, src2);
  530 + tcg_gen_andi_tl(r_temp, r_temp, 0x3);
  531 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
  532 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
  533 + gen_set_label(l1);
  534 +}
  535 +
  536 +static inline void gen_tag_tv(TCGv src1, TCGv src2)
  537 +{
  538 + int l1;
  539 + TCGv r_zero, r_temp;
  540 +
  541 + l1 = gen_new_label();
  542 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  543 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  544 + tcg_gen_movi_tl(r_zero, 0);
  545 + tcg_gen_or_tl(r_temp, src1, src2);
  546 + tcg_gen_andi_tl(r_temp, r_temp, 0x3);
  547 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
  548 + gen_op_exception(TT_TOVF);
  549 + gen_set_label(l1);
  550 +}
  551 +
  552 +static inline void gen_op_add_T1_T0_cc(void)
  553 +{
  554 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  555 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  556 + gen_cc_clear();
  557 + gen_cc_NZ(cpu_T[0]);
  558 + gen_cc_C_add(cpu_T[0], cpu_cc_src);
  559 + gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
  560 +}
  561 +
  562 +static inline void gen_op_addx_T1_T0_cc(void)
  563 +{
  564 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  565 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  566 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
  567 + gen_cc_clear();
  568 + gen_cc_C_add(cpu_T[0], cpu_cc_src);
  569 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  570 + gen_cc_C_add(cpu_T[0], cpu_cc_src);
  571 + gen_cc_NZ(cpu_T[0]);
  572 + gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
  573 +}
  574 +
  575 +static inline void gen_op_tadd_T1_T0_cc(void)
  576 +{
  577 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  578 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  579 + gen_cc_clear();
  580 + gen_cc_NZ(cpu_T[0]);
  581 + gen_cc_C_add(cpu_T[0], cpu_cc_src);
  582 + gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
  583 + gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
  584 +}
  585 +
  586 +static inline void gen_op_tadd_T1_T0_ccTV(void)
  587 +{
  588 + gen_tag_tv(cpu_T[0], cpu_T[1]);
  589 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  590 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  591 + gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
  592 + gen_cc_clear();
  593 + gen_cc_NZ(cpu_T[0]);
  594 + gen_cc_C_add(cpu_T[0], cpu_cc_src);
  595 +}
  596 +
  597 +/* old op:
  598 + if (src1 < T1)
  599 + env->psr |= PSR_CARRY;
  600 +*/
  601 +static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
  602 +{
  603 + int l1;
  604 +
  605 + l1 = gen_new_label();
  606 + tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
  607 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
  608 + gen_set_label(l1);
  609 +#ifdef TARGET_SPARC64
  610 + {
  611 + int l2;
  612 +
  613 + l2 = gen_new_label();
  614 + tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
  615 + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
  616 + gen_set_label(l2);
  617 + }
  618 +#endif
  619 +}
  620 +
  621 +/* old op:
  622 + if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
  623 + env->psr |= PSR_OVF;
  624 +*/
  625 +static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
  626 +{
  627 + TCGv r_temp, r_temp2, r_temp3, r_zero;
  628 + int l1;
  629 +
  630 + l1 = gen_new_label();
  631 +
  632 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  633 + r_temp2 = tcg_temp_new(TCG_TYPE_TL);
  634 + r_temp3 = tcg_temp_new(TCG_TYPE_TL);
  635 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  636 + tcg_gen_movi_tl(r_zero, 0);
  637 + tcg_gen_xor_tl(r_temp, src1, src2);
  638 + tcg_gen_xor_tl(r_temp2, src1, dst);
  639 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  640 + tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
  641 + tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
  642 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
  643 + gen_set_label(l1);
  644 +#ifdef TARGET_SPARC64
  645 + {
  646 + int l2;
  647 +
  648 + l2 = gen_new_label();
  649 + tcg_gen_movi_tl(r_zero, 0);
  650 + tcg_gen_xor_tl(r_temp, src1, src2);
  651 + tcg_gen_xor_tl(r_temp2, src1, dst);
  652 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  653 + tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
  654 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
  655 + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
  656 + gen_set_label(l2);
  657 + }
  658 +#endif
  659 +}
  660 +
  661 +static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
  662 +{
  663 + TCGv r_temp, r_temp2, r_temp3, r_zero;
  664 + int l1;
  665 +
  666 + l1 = gen_new_label();
  667 +
  668 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  669 + r_temp2 = tcg_temp_new(TCG_TYPE_TL);
  670 + r_temp3 = tcg_temp_new(TCG_TYPE_TL);
  671 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  672 + tcg_gen_movi_tl(r_zero, 0);
  673 + tcg_gen_xor_tl(r_temp, src1, src2);
  674 + tcg_gen_xor_tl(r_temp2, src1, dst);
  675 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  676 + tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
  677 + tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
  678 + gen_op_exception(TT_TOVF);
  679 + gen_set_label(l1);
  680 +#ifdef TARGET_SPARC64
  681 + {
  682 + int l2;
  683 +
  684 + l2 = gen_new_label();
  685 + tcg_gen_movi_tl(r_zero, 0);
  686 + tcg_gen_xor_tl(r_temp, src1, src2);
  687 + tcg_gen_xor_tl(r_temp2, src1, dst);
  688 + tcg_gen_and_tl(r_temp, r_temp, r_temp2);
  689 + tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
  690 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
  691 + gen_op_exception(TT_TOVF);
  692 + gen_set_label(l2);
  693 + }
  694 +#endif
  695 +}
  696 +
  697 +static inline void gen_op_sub_T1_T0_cc(void)
  698 +{
  699 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  700 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  701 + gen_cc_clear();
  702 + gen_cc_NZ(cpu_T[0]);
  703 + gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
  704 + gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
  705 +}
  706 +
  707 +static inline void gen_op_subx_T1_T0_cc(void)
  708 +{
  709 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  710 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  711 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
  712 + gen_cc_clear();
  713 + gen_cc_C_sub(cpu_T[0], cpu_cc_src);
  714 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  715 + gen_cc_C_sub(cpu_T[0], cpu_cc_src);
  716 + gen_cc_NZ(cpu_T[0]);
  717 + gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
  718 +}
  719 +
  720 +static inline void gen_op_tsub_T1_T0_cc(void)
  721 +{
  722 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  723 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  724 + gen_cc_clear();
  725 + gen_cc_NZ(cpu_T[0]);
  726 + gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
  727 + gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
  728 + gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
  729 +}
  730 +
  731 +static inline void gen_op_tsub_T1_T0_ccTV(void)
  732 +{
  733 + gen_tag_tv(cpu_T[0], cpu_T[1]);
  734 + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  735 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  736 + gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
  737 + gen_cc_clear();
  738 + gen_cc_NZ(cpu_T[0]);
  739 + gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
  740 +}
  741 +
  742 +static inline void gen_op_div_cc(void)
  743 +{
  744 + int l1;
  745 + TCGv r_zero;
  746 +
  747 + gen_cc_clear();
  748 + gen_cc_NZ(cpu_T[0]);
  749 + l1 = gen_new_label();
  750 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  751 + tcg_gen_movi_tl(r_zero, 0);
  752 + tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], r_zero, l1);
  753 + tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
  754 + gen_set_label(l1);
  755 +}
  756 +
  757 +static inline void gen_op_logic_T0_cc(void)
  758 +{
  759 + gen_cc_clear();
  760 + gen_cc_NZ(cpu_T[0]);
  761 +}
  762 +
359 763 // 1
360 764 static inline void gen_op_eval_ba(TCGv dst)
361 765 {
... ... @@ -789,14 +1193,13 @@ static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
789 1193 {
790 1194 TCGv r_src;
791 1195  
792   - r_src = tcg_temp_new(TCG_TYPE_TL);
793 1196 #ifdef TARGET_SPARC64
794 1197 if (cc)
795   - tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, xcc));
  1198 + r_src = cpu_xcc;
796 1199 else
797   - tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr));
  1200 + r_src = cpu_psr;
798 1201 #else
799   - tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr));
  1202 + r_src = cpu_psr;
800 1203 #endif
801 1204 switch (cond) {
802 1205 case 0x0:
... ... @@ -1170,15 +1573,6 @@ static inline void gen_op_fcmpeq(int fccno)
1170 1573  
1171 1574 #endif
1172 1575  
1173   -static inline void gen_op_exception(int exception)
1174   -{
1175   - TCGv r_except;
1176   -
1177   - r_except = tcg_temp_new(TCG_TYPE_I32);
1178   - tcg_gen_movi_i32(r_except, exception);
1179   - tcg_gen_helper_0_1(raise_exception, r_except);
1180   -}
1181   -
1182 1576 static inline void gen_op_fpexception_im(int fsr_flags)
1183 1577 {
1184 1578 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
... ... @@ -2632,9 +3026,7 @@ static void disas_sparc_insn(DisasContext * dc)
2632 3026 if (xop & 0x10)
2633 3027 gen_op_addx_T1_T0_cc();
2634 3028 else {
2635   - tcg_gen_ld_i32(cpu_tmp0, cpu_env,
2636   - offsetof(CPUSPARCState, psr));
2637   - gen_mov_reg_C(cpu_tmp0, cpu_tmp0);
  3029 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
2638 3030 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2639 3031 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2640 3032 }
... ... @@ -2658,9 +3050,7 @@ static void disas_sparc_insn(DisasContext * dc)
2658 3050 if (xop & 0x10)
2659 3051 gen_op_subx_T1_T0_cc();
2660 3052 else {
2661   - tcg_gen_ld_i32(cpu_tmp0, cpu_env,
2662   - offsetof(CPUSPARCState, psr));
2663   - gen_mov_reg_C(cpu_tmp0, cpu_tmp0);
  3053 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
2664 3054 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2665 3055 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2666 3056 }
... ... @@ -4345,11 +4735,23 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model)
4345 4735 TCG_AREG0, offsetof(CPUState, t1), "T1");
4346 4736 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4347 4737 TCG_AREG0, offsetof(CPUState, t2), "T2");
  4738 + cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
  4739 + TCG_AREG0, offsetof(CPUState, xcc),
  4740 + "xcc");
4348 4741 #else
4349 4742 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4350 4743 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4351 4744 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4352 4745 #endif
  4746 + cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
  4747 + TCG_AREG0, offsetof(CPUState, cc_src),
  4748 + "cc_src");
  4749 + cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
  4750 + TCG_AREG0, offsetof(CPUState, cc_dst),
  4751 + "cc_dst");
  4752 + cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
  4753 + TCG_AREG0, offsetof(CPUState, psr),
  4754 + "psr");
4353 4755 }
4354 4756  
4355 4757 cpu_reset(env);
... ...