gwj / at91sam9263 · Commits

Commit dc485d282faa0a791514b2c7211db6a594601f4b

Authored by Filip Navara
1 parent d2efb32f

Convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T. 

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Inline Side-by-side
Showing 1 changed file with 56 additions and 41 deletions
target-arm/translate.c
  View file @dc485d2
@@ -6451,10 +6451,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) @@ -6451,10 +6451,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6451 ARCH(6K); 6451 ARCH(6K);
6452 else 6452 else
6453 ARCH(6); 6453 ARCH(6);
6454 - gen_movl_T1_reg(s, rn);  
6455 - addr = cpu_T[1]; 6454 + addr = tcg_temp_local_new_i32();
  6455 + tcg_gen_mov_i32(addr, cpu_R[rn]);
6456 if (insn & (1 << 20)) { 6456 if (insn & (1 << 20)) {
6457 - gen_helper_mark_exclusive(cpu_env, cpu_T[1]); 6457 + gen_helper_mark_exclusive(cpu_env, addr);
6458 switch (op1) { 6458 switch (op1) {
6459 case 0: /* ldrex */ 6459 case 0: /* ldrex */
6460 tmp = gen_ld32(addr, IS_USER(s)); 6460 tmp = gen_ld32(addr, IS_USER(s));
@@ -6479,9 +6479,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) @@ -6479,9 +6479,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6479 } else { 6479 } else {
6480 int label = gen_new_label(); 6480 int label = gen_new_label();
6481 rm = insn & 0xf; 6481 rm = insn & 0xf;
6482 - gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);  
6483 - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],  
6484 - 0, label); 6482 + tmp2 = tcg_temp_local_new_i32();
  6483 + gen_helper_test_exclusive(tmp2, cpu_env, addr);
  6484 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
6485 tmp = load_reg(s,rm); 6485 tmp = load_reg(s,rm);
6486 switch (op1) { 6486 switch (op1) {
6487 case 0: /* strex */ 6487 case 0: /* strex */
@@ -6503,8 +6503,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) @@ -6503,8 +6503,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6503 abort(); 6503 abort();
6504 } 6504 }
6505 gen_set_label(label); 6505 gen_set_label(label);
6506 - gen_movl_reg_T0(s, rd); 6506 + tcg_gen_mov_i32(cpu_R[rd], tmp2);
  6507 + tcg_temp_free(tmp2);
6507 } 6508 }
  6509 + tcg_temp_free(addr);
6508 } else { 6510 } else {
6509 /* SWP instruction */ 6511 /* SWP instruction */
6510 rm = (insn) & 0xf; 6512 rm = (insn) & 0xf;
@@ -7267,22 +7269,24 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) @@ -7267,22 +7269,24 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7267 } 7269 }
7268 } else if ((insn & (1 << 23)) == 0) { 7270 } else if ((insn & (1 << 23)) == 0) {
7269 /* Load/store exclusive word. */ 7271 /* Load/store exclusive word. */
7270 - gen_movl_T1_reg(s, rn);  
7271 - addr = cpu_T[1]; 7272 + addr = tcg_temp_local_new();
  7273 + tcg_gen_mov_i32(addr, cpu_R[rn]);
7272 if (insn & (1 << 20)) { 7274 if (insn & (1 << 20)) {
7273 - gen_helper_mark_exclusive(cpu_env, cpu_T[1]); 7275 + gen_helper_mark_exclusive(cpu_env, addr);
7274 tmp = gen_ld32(addr, IS_USER(s)); 7276 tmp = gen_ld32(addr, IS_USER(s));
7275 store_reg(s, rd, tmp); 7277 store_reg(s, rd, tmp);
7276 } else { 7278 } else {
7277 int label = gen_new_label(); 7279 int label = gen_new_label();
7278 - gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);  
7279 - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],  
7280 - 0, label); 7280 + tmp2 = tcg_temp_local_new();
  7281 + gen_helper_test_exclusive(tmp2, cpu_env, addr);
  7282 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
7281 tmp = load_reg(s, rs); 7283 tmp = load_reg(s, rs);
7282 - gen_st32(tmp, cpu_T[1], IS_USER(s)); 7284 + gen_st32(tmp, addr, IS_USER(s));
7283 gen_set_label(label); 7285 gen_set_label(label);
7284 - gen_movl_reg_T0(s, rd); 7286 + tcg_gen_mov_i32(cpu_R[rd], tmp2);
  7287 + tcg_temp_free(tmp2);
7285 } 7288 }
  7289 + tcg_temp_free(addr);
7286 } else if ((insn & (1 << 6)) == 0) { 7290 } else if ((insn & (1 << 6)) == 0) {
7287 /* Table Branch. */ 7291 /* Table Branch. */
7288 if (rn == 15) { 7292 if (rn == 15) {
@@ -7312,10 +7316,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) @@ -7312,10 +7316,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7312 we never have multiple CPUs running in parallel, 7316 we never have multiple CPUs running in parallel,
7313 so it is good enough. */ 7317 so it is good enough. */
7314 op = (insn >> 4) & 0x3; 7318 op = (insn >> 4) & 0x3;
7315 - /* Must use a global reg for the address because we have  
7316 - a conditional branch in the store instruction. */  
7317 - gen_movl_T1_reg(s, rn);  
7318 - addr = cpu_T[1]; 7319 + addr = tcg_temp_local_new();
  7320 + tcg_gen_mov_i32(addr, cpu_R[rn]);
7319 if (insn & (1 << 20)) { 7321 if (insn & (1 << 20)) {
7320 gen_helper_mark_exclusive(cpu_env, addr); 7322 gen_helper_mark_exclusive(cpu_env, addr);
7321 switch (op) { 7323 switch (op) {
@@ -7337,9 +7339,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) @@ -7337,9 +7339,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7337 store_reg(s, rs, tmp); 7339 store_reg(s, rs, tmp);
7338 } else { 7340 } else {
7339 int label = gen_new_label(); 7341 int label = gen_new_label();
7340 - /* Must use a global that is not killed by the branch. */  
7341 - gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);  
7342 - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], 0, label); 7342 + tmp2 = tcg_temp_local_new();
  7343 + gen_helper_test_exclusive(tmp2, cpu_env, addr);
  7344 + tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
7343 tmp = load_reg(s, rs); 7345 tmp = load_reg(s, rs);
7344 switch (op) { 7346 switch (op) {
7345 case 0: 7347 case 0:
@@ -7358,8 +7360,10 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) @@ -7358,8 +7360,10 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7358 goto illegal_op; 7360 goto illegal_op;
7359 } 7361 }
7360 gen_set_label(label); 7362 gen_set_label(label);
7361 - gen_movl_reg_T0(s, rm); 7363 + tcg_gen_mov_i32(cpu_R[rm], tmp2);
  7364 + tcg_temp_free(tmp2);
7362 } 7365 }
  7366 + tcg_temp_free(addr);
7363 } 7367 }
7364 } else { 7368 } else {
7365 /* Load/store multiple, RFE, SRS. */ 7369 /* Load/store multiple, RFE, SRS. */
@@ -7469,21 +7473,27 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) @@ -7469,21 +7473,27 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7469 } 7473 }
7470 break; 7474 break;
7471 case 5: /* Data processing register constant shift. */ 7475 case 5: /* Data processing register constant shift. */
7472 - if (rn == 15)  
7473 - gen_op_movl_T0_im(0);  
7474 - else  
7475 - gen_movl_T0_reg(s, rn);  
7476 - gen_movl_T1_reg(s, rm); 7476 + if (rn == 15) {
  7477 + tmp = new_tmp();
  7478 + tcg_gen_movi_i32(tmp, 0);
  7479 + } else {
  7480 + tmp = load_reg(s, rn);
  7481 + }
  7482 + tmp2 = load_reg(s, rm);
7477 op = (insn >> 21) & 0xf; 7483 op = (insn >> 21) & 0xf;
7478 shiftop = (insn >> 4) & 3; 7484 shiftop = (insn >> 4) & 3;
7479 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); 7485 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7480 conds = (insn & (1 << 20)) != 0; 7486 conds = (insn & (1 << 20)) != 0;
7481 logic_cc = (conds && thumb2_logic_op(op)); 7487 logic_cc = (conds && thumb2_logic_op(op));
7482 - gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);  
7483 - if (gen_thumb2_data_op(s, op, conds, 0, cpu_T[0], cpu_T[1])) 7488 + gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
  7489 + if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7484 goto illegal_op; 7490 goto illegal_op;
7485 - if (rd != 15)  
7486 - gen_movl_reg_T0(s, rd); 7491 + dead_tmp(tmp2);
  7492 + if (rd != 15) {
  7493 + store_reg(s, rd, tmp);
  7494 + } else {
  7495 + dead_tmp(tmp);
  7496 + }
7487 break; 7497 break;
7488 case 13: /* Misc data processing. */ 7498 case 13: /* Misc data processing. */
7489 op = ((insn >> 22) & 6) | ((insn >> 7) & 1); 7499 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
@@ -7770,8 +7780,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) @@ -7770,8 +7780,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7770 7780
7771 if (insn & (1 << 14)) { 7781 if (insn & (1 << 14)) {
7772 /* Branch and link. */ 7782 /* Branch and link. */
7773 - gen_op_movl_T1_im(s->pc | 1);  
7774 - gen_movl_reg_T1(s, 14); 7783 + tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
7775 } 7784 }
7776 7785
7777 offset += s->pc; 7786 offset += s->pc;
@@ -8035,19 +8044,25 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) @@ -8035,19 +8044,25 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
8035 shifter_out = 1; 8044 shifter_out = 1;
8036 break; 8045 break;
8037 } 8046 }
8038 - gen_op_movl_T1_im(imm); 8047 + tmp2 = new_tmp();
  8048 + tcg_gen_movi_i32(tmp2, imm);
8039 rn = (insn >> 16) & 0xf; 8049 rn = (insn >> 16) & 0xf;
8040 - if (rn == 15)  
8041 - gen_op_movl_T0_im(0);  
8042 - else  
8043 - gen_movl_T0_reg(s, rn); 8050 + if (rn == 15) {
  8051 + tmp = new_tmp();
  8052 + tcg_gen_movi_i32(tmp, 0);
  8053 + } else {
  8054 + tmp = load_reg(s, rn);
  8055 + }
8044 op = (insn >> 21) & 0xf; 8056 op = (insn >> 21) & 0xf;
8045 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, 8057 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8046 - shifter_out, cpu_T[0], cpu_T[1])) 8058 + shifter_out, tmp, tmp2))
8047 goto illegal_op; 8059 goto illegal_op;
  8060 + dead_tmp(tmp2);
8048 rd = (insn >> 8) & 0xf; 8061 rd = (insn >> 8) & 0xf;
8049 if (rd != 15) { 8062 if (rd != 15) {
8050 - gen_movl_reg_T0(s, rd); 8063 + store_reg(s, rd, tmp);
  8064 + } else {
  8065 + dead_tmp(tmp);
8051 } 8066 }
8052 } 8067 }
8053 } 8068 }