gwj / at91sam9263 · Commits

Commit dc1a6971e34feb15543134df8bcd9e393ed66c86

Authored by Blue Swirl
1 parent 03f311ed

Reindent 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 1 changed file with 312 additions and 319 deletions
target-sparc/translate.c
  View file @dc1a697
@@ -81,11 +81,11 @@ typedef struct DisasContext { @@ -81,11 +81,11 @@ typedef struct DisasContext {
81 } DisasContext; 81 } DisasContext;
82 82
83 // This function uses non-native bit order 83 // This function uses non-native bit order
84 -#define GET_FIELD(X, FROM, TO) \  
85 - ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) 84 +#define GET_FIELD(X, FROM, TO) \
  85 + ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
86 86
87 // This function uses the order in the manuals, i.e. bit 0 is 2^0 87 // This function uses the order in the manuals, i.e. bit 0 is 2^0
88 -#define GET_FIELD_SP(X, FROM, TO) \ 88 +#define GET_FIELD_SP(X, FROM, TO) \
89 GET_FIELD(X, 31 - (TO), 31 - (FROM)) 89 GET_FIELD(X, 31 - (TO), 31 - (FROM))
90 90
91 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) 91 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
@@ -2098,8 +2098,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2098,8 +2098,8 @@ static void disas_sparc_insn(DisasContext * dc)
2098 break; 2098 break;
2099 } 2099 }
2100 break; 2100 break;
2101 - case 1:  
2102 - /*CALL*/ { 2101 + case 1: /*CALL*/
  2102 + {
2103 target_long target = GET_FIELDs(insn, 2, 31) << 2; 2103 target_long target = GET_FIELDs(insn, 2, 31) << 2;
2104 TCGv r_const; 2104 TCGv r_const;
2105 2105
@@ -2457,313 +2457,307 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2457,313 +2457,307 @@ static void disas_sparc_insn(DisasContext * dc)
2457 rs2 = GET_FIELD(insn, 27, 31); 2457 rs2 = GET_FIELD(insn, 27, 31);
2458 xop = GET_FIELD(insn, 18, 26); 2458 xop = GET_FIELD(insn, 18, 26);
2459 switch (xop) { 2459 switch (xop) {
2460 - case 0x1: /* fmovs */  
2461 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);  
2462 - break;  
2463 - case 0x5: /* fnegs */  
2464 - gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]);  
2465 - break;  
2466 - case 0x9: /* fabss */  
2467 - gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]);  
2468 - break;  
2469 - case 0x29: /* fsqrts */  
2470 - CHECK_FPU_FEATURE(dc, FSQRT);  
2471 - gen_clear_float_exceptions();  
2472 - gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]);  
2473 - gen_helper_check_ieee_exceptions();  
2474 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2475 - break;  
2476 - case 0x2a: /* fsqrtd */  
2477 - CHECK_FPU_FEATURE(dc, FSQRT);  
2478 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2479 - gen_clear_float_exceptions();  
2480 - gen_helper_fsqrtd();  
2481 - gen_helper_check_ieee_exceptions();  
2482 - gen_op_store_DT0_fpr(DFPREG(rd));  
2483 - break;  
2484 - case 0x2b: /* fsqrtq */  
2485 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2486 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2487 - gen_clear_float_exceptions();  
2488 - gen_helper_fsqrtq();  
2489 - gen_helper_check_ieee_exceptions();  
2490 - gen_op_store_QT0_fpr(QFPREG(rd));  
2491 - break;  
2492 - case 0x41: /* fadds */  
2493 - gen_clear_float_exceptions();  
2494 - gen_helper_fadds(cpu_tmp32,  
2495 - cpu_fpr[rs1], cpu_fpr[rs2]);  
2496 - gen_helper_check_ieee_exceptions();  
2497 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2498 - break;  
2499 - case 0x42: /* faddd */  
2500 - gen_op_load_fpr_DT0(DFPREG(rs1));  
2501 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2502 - gen_clear_float_exceptions();  
2503 - gen_helper_faddd();  
2504 - gen_helper_check_ieee_exceptions();  
2505 - gen_op_store_DT0_fpr(DFPREG(rd));  
2506 - break;  
2507 - case 0x43: /* faddq */  
2508 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2509 - gen_op_load_fpr_QT0(QFPREG(rs1));  
2510 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2511 - gen_clear_float_exceptions();  
2512 - gen_helper_faddq();  
2513 - gen_helper_check_ieee_exceptions();  
2514 - gen_op_store_QT0_fpr(QFPREG(rd));  
2515 - break;  
2516 - case 0x45: /* fsubs */  
2517 - gen_clear_float_exceptions();  
2518 - gen_helper_fsubs(cpu_tmp32,  
2519 - cpu_fpr[rs1], cpu_fpr[rs2]);  
2520 - gen_helper_check_ieee_exceptions();  
2521 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2522 - break;  
2523 - case 0x46: /* fsubd */  
2524 - gen_op_load_fpr_DT0(DFPREG(rs1));  
2525 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2526 - gen_clear_float_exceptions();  
2527 - gen_helper_fsubd();  
2528 - gen_helper_check_ieee_exceptions();  
2529 - gen_op_store_DT0_fpr(DFPREG(rd));  
2530 - break;  
2531 - case 0x47: /* fsubq */  
2532 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2533 - gen_op_load_fpr_QT0(QFPREG(rs1));  
2534 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2535 - gen_clear_float_exceptions();  
2536 - gen_helper_fsubq();  
2537 - gen_helper_check_ieee_exceptions();  
2538 - gen_op_store_QT0_fpr(QFPREG(rd));  
2539 - break;  
2540 - case 0x49: /* fmuls */  
2541 - CHECK_FPU_FEATURE(dc, FMUL);  
2542 - gen_clear_float_exceptions();  
2543 - gen_helper_fmuls(cpu_tmp32,  
2544 - cpu_fpr[rs1], cpu_fpr[rs2]);  
2545 - gen_helper_check_ieee_exceptions();  
2546 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2547 - break;  
2548 - case 0x4a: /* fmuld */  
2549 - CHECK_FPU_FEATURE(dc, FMUL);  
2550 - gen_op_load_fpr_DT0(DFPREG(rs1));  
2551 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2552 - gen_clear_float_exceptions();  
2553 - gen_helper_fmuld();  
2554 - gen_helper_check_ieee_exceptions();  
2555 - gen_op_store_DT0_fpr(DFPREG(rd));  
2556 - break;  
2557 - case 0x4b: /* fmulq */  
2558 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2559 - CHECK_FPU_FEATURE(dc, FMUL);  
2560 - gen_op_load_fpr_QT0(QFPREG(rs1));  
2561 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2562 - gen_clear_float_exceptions();  
2563 - gen_helper_fmulq();  
2564 - gen_helper_check_ieee_exceptions();  
2565 - gen_op_store_QT0_fpr(QFPREG(rd));  
2566 - break;  
2567 - case 0x4d: /* fdivs */  
2568 - gen_clear_float_exceptions();  
2569 - gen_helper_fdivs(cpu_tmp32,  
2570 - cpu_fpr[rs1], cpu_fpr[rs2]);  
2571 - gen_helper_check_ieee_exceptions();  
2572 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2573 - break;  
2574 - case 0x4e: /* fdivd */  
2575 - gen_op_load_fpr_DT0(DFPREG(rs1));  
2576 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2577 - gen_clear_float_exceptions();  
2578 - gen_helper_fdivd();  
2579 - gen_helper_check_ieee_exceptions();  
2580 - gen_op_store_DT0_fpr(DFPREG(rd));  
2581 - break;  
2582 - case 0x4f: /* fdivq */  
2583 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2584 - gen_op_load_fpr_QT0(QFPREG(rs1));  
2585 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2586 - gen_clear_float_exceptions();  
2587 - gen_helper_fdivq();  
2588 - gen_helper_check_ieee_exceptions();  
2589 - gen_op_store_QT0_fpr(QFPREG(rd));  
2590 - break;  
2591 - case 0x69: /* fsmuld */  
2592 - CHECK_FPU_FEATURE(dc, FSMULD);  
2593 - gen_clear_float_exceptions();  
2594 - gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]);  
2595 - gen_helper_check_ieee_exceptions();  
2596 - gen_op_store_DT0_fpr(DFPREG(rd));  
2597 - break;  
2598 - case 0x6e: /* fdmulq */  
2599 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2600 - gen_op_load_fpr_DT0(DFPREG(rs1));  
2601 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2602 - gen_clear_float_exceptions();  
2603 - gen_helper_fdmulq();  
2604 - gen_helper_check_ieee_exceptions();  
2605 - gen_op_store_QT0_fpr(QFPREG(rd));  
2606 - break;  
2607 - case 0xc4: /* fitos */  
2608 - gen_clear_float_exceptions();  
2609 - gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]);  
2610 - gen_helper_check_ieee_exceptions();  
2611 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2612 - break;  
2613 - case 0xc6: /* fdtos */  
2614 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2615 - gen_clear_float_exceptions();  
2616 - gen_helper_fdtos(cpu_tmp32);  
2617 - gen_helper_check_ieee_exceptions();  
2618 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2619 - break;  
2620 - case 0xc7: /* fqtos */  
2621 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2622 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2623 - gen_clear_float_exceptions();  
2624 - gen_helper_fqtos(cpu_tmp32);  
2625 - gen_helper_check_ieee_exceptions();  
2626 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2627 - break;  
2628 - case 0xc8: /* fitod */  
2629 - gen_helper_fitod(cpu_fpr[rs2]);  
2630 - gen_op_store_DT0_fpr(DFPREG(rd));  
2631 - break;  
2632 - case 0xc9: /* fstod */  
2633 - gen_helper_fstod(cpu_fpr[rs2]);  
2634 - gen_op_store_DT0_fpr(DFPREG(rd));  
2635 - break;  
2636 - case 0xcb: /* fqtod */  
2637 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2638 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2639 - gen_clear_float_exceptions();  
2640 - gen_helper_fqtod();  
2641 - gen_helper_check_ieee_exceptions();  
2642 - gen_op_store_DT0_fpr(DFPREG(rd));  
2643 - break;  
2644 - case 0xcc: /* fitoq */  
2645 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2646 - gen_helper_fitoq(cpu_fpr[rs2]);  
2647 - gen_op_store_QT0_fpr(QFPREG(rd));  
2648 - break;  
2649 - case 0xcd: /* fstoq */  
2650 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2651 - gen_helper_fstoq(cpu_fpr[rs2]);  
2652 - gen_op_store_QT0_fpr(QFPREG(rd));  
2653 - break;  
2654 - case 0xce: /* fdtoq */  
2655 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2656 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2657 - gen_helper_fdtoq();  
2658 - gen_op_store_QT0_fpr(QFPREG(rd));  
2659 - break;  
2660 - case 0xd1: /* fstoi */  
2661 - gen_clear_float_exceptions();  
2662 - gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]);  
2663 - gen_helper_check_ieee_exceptions();  
2664 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2665 - break;  
2666 - case 0xd2: /* fdtoi */  
2667 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2668 - gen_clear_float_exceptions();  
2669 - gen_helper_fdtoi(cpu_tmp32);  
2670 - gen_helper_check_ieee_exceptions();  
2671 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2672 - break;  
2673 - case 0xd3: /* fqtoi */  
2674 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2675 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2676 - gen_clear_float_exceptions();  
2677 - gen_helper_fqtoi(cpu_tmp32);  
2678 - gen_helper_check_ieee_exceptions();  
2679 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2680 - break; 2460 + case 0x1: /* fmovs */
  2461 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
  2462 + break;
  2463 + case 0x5: /* fnegs */
  2464 + gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]);
  2465 + break;
  2466 + case 0x9: /* fabss */
  2467 + gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]);
  2468 + break;
  2469 + case 0x29: /* fsqrts */
  2470 + CHECK_FPU_FEATURE(dc, FSQRT);
  2471 + gen_clear_float_exceptions();
  2472 + gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]);
  2473 + gen_helper_check_ieee_exceptions();
  2474 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2475 + break;
  2476 + case 0x2a: /* fsqrtd */
  2477 + CHECK_FPU_FEATURE(dc, FSQRT);
  2478 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2479 + gen_clear_float_exceptions();
  2480 + gen_helper_fsqrtd();
  2481 + gen_helper_check_ieee_exceptions();
  2482 + gen_op_store_DT0_fpr(DFPREG(rd));
  2483 + break;
  2484 + case 0x2b: /* fsqrtq */
  2485 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2486 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2487 + gen_clear_float_exceptions();
  2488 + gen_helper_fsqrtq();
  2489 + gen_helper_check_ieee_exceptions();
  2490 + gen_op_store_QT0_fpr(QFPREG(rd));
  2491 + break;
  2492 + case 0x41: /* fadds */
  2493 + gen_clear_float_exceptions();
  2494 + gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
  2495 + gen_helper_check_ieee_exceptions();
  2496 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2497 + break;
  2498 + case 0x42: /* faddd */
  2499 + gen_op_load_fpr_DT0(DFPREG(rs1));
  2500 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2501 + gen_clear_float_exceptions();
  2502 + gen_helper_faddd();
  2503 + gen_helper_check_ieee_exceptions();
  2504 + gen_op_store_DT0_fpr(DFPREG(rd));
  2505 + break;
  2506 + case 0x43: /* faddq */
  2507 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2508 + gen_op_load_fpr_QT0(QFPREG(rs1));
  2509 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2510 + gen_clear_float_exceptions();
  2511 + gen_helper_faddq();
  2512 + gen_helper_check_ieee_exceptions();
  2513 + gen_op_store_QT0_fpr(QFPREG(rd));
  2514 + break;
  2515 + case 0x45: /* fsubs */
  2516 + gen_clear_float_exceptions();
  2517 + gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
  2518 + gen_helper_check_ieee_exceptions();
  2519 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2520 + break;
  2521 + case 0x46: /* fsubd */
  2522 + gen_op_load_fpr_DT0(DFPREG(rs1));
  2523 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2524 + gen_clear_float_exceptions();
  2525 + gen_helper_fsubd();
  2526 + gen_helper_check_ieee_exceptions();
  2527 + gen_op_store_DT0_fpr(DFPREG(rd));
  2528 + break;
  2529 + case 0x47: /* fsubq */
  2530 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2531 + gen_op_load_fpr_QT0(QFPREG(rs1));
  2532 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2533 + gen_clear_float_exceptions();
  2534 + gen_helper_fsubq();
  2535 + gen_helper_check_ieee_exceptions();
  2536 + gen_op_store_QT0_fpr(QFPREG(rd));
  2537 + break;
  2538 + case 0x49: /* fmuls */
  2539 + CHECK_FPU_FEATURE(dc, FMUL);
  2540 + gen_clear_float_exceptions();
  2541 + gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
  2542 + gen_helper_check_ieee_exceptions();
  2543 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2544 + break;
  2545 + case 0x4a: /* fmuld */
  2546 + CHECK_FPU_FEATURE(dc, FMUL);
  2547 + gen_op_load_fpr_DT0(DFPREG(rs1));
  2548 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2549 + gen_clear_float_exceptions();
  2550 + gen_helper_fmuld();
  2551 + gen_helper_check_ieee_exceptions();
  2552 + gen_op_store_DT0_fpr(DFPREG(rd));
  2553 + break;
  2554 + case 0x4b: /* fmulq */
  2555 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2556 + CHECK_FPU_FEATURE(dc, FMUL);
  2557 + gen_op_load_fpr_QT0(QFPREG(rs1));
  2558 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2559 + gen_clear_float_exceptions();
  2560 + gen_helper_fmulq();
  2561 + gen_helper_check_ieee_exceptions();
  2562 + gen_op_store_QT0_fpr(QFPREG(rd));
  2563 + break;
  2564 + case 0x4d: /* fdivs */
  2565 + gen_clear_float_exceptions();
  2566 + gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
  2567 + gen_helper_check_ieee_exceptions();
  2568 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2569 + break;
  2570 + case 0x4e: /* fdivd */
  2571 + gen_op_load_fpr_DT0(DFPREG(rs1));
  2572 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2573 + gen_clear_float_exceptions();
  2574 + gen_helper_fdivd();
  2575 + gen_helper_check_ieee_exceptions();
  2576 + gen_op_store_DT0_fpr(DFPREG(rd));
  2577 + break;
  2578 + case 0x4f: /* fdivq */
  2579 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2580 + gen_op_load_fpr_QT0(QFPREG(rs1));
  2581 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2582 + gen_clear_float_exceptions();
  2583 + gen_helper_fdivq();
  2584 + gen_helper_check_ieee_exceptions();
  2585 + gen_op_store_QT0_fpr(QFPREG(rd));
  2586 + break;
  2587 + case 0x69: /* fsmuld */
  2588 + CHECK_FPU_FEATURE(dc, FSMULD);
  2589 + gen_clear_float_exceptions();
  2590 + gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]);
  2591 + gen_helper_check_ieee_exceptions();
  2592 + gen_op_store_DT0_fpr(DFPREG(rd));
  2593 + break;
  2594 + case 0x6e: /* fdmulq */
  2595 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2596 + gen_op_load_fpr_DT0(DFPREG(rs1));
  2597 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2598 + gen_clear_float_exceptions();
  2599 + gen_helper_fdmulq();
  2600 + gen_helper_check_ieee_exceptions();
  2601 + gen_op_store_QT0_fpr(QFPREG(rd));
  2602 + break;
  2603 + case 0xc4: /* fitos */
  2604 + gen_clear_float_exceptions();
  2605 + gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]);
  2606 + gen_helper_check_ieee_exceptions();
  2607 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2608 + break;
  2609 + case 0xc6: /* fdtos */
  2610 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2611 + gen_clear_float_exceptions();
  2612 + gen_helper_fdtos(cpu_tmp32);
  2613 + gen_helper_check_ieee_exceptions();
  2614 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2615 + break;
  2616 + case 0xc7: /* fqtos */
  2617 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2618 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2619 + gen_clear_float_exceptions();
  2620 + gen_helper_fqtos(cpu_tmp32);
  2621 + gen_helper_check_ieee_exceptions();
  2622 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2623 + break;
  2624 + case 0xc8: /* fitod */
  2625 + gen_helper_fitod(cpu_fpr[rs2]);
  2626 + gen_op_store_DT0_fpr(DFPREG(rd));
  2627 + break;
  2628 + case 0xc9: /* fstod */
  2629 + gen_helper_fstod(cpu_fpr[rs2]);
  2630 + gen_op_store_DT0_fpr(DFPREG(rd));
  2631 + break;
  2632 + case 0xcb: /* fqtod */
  2633 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2634 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2635 + gen_clear_float_exceptions();
  2636 + gen_helper_fqtod();
  2637 + gen_helper_check_ieee_exceptions();
  2638 + gen_op_store_DT0_fpr(DFPREG(rd));
  2639 + break;
  2640 + case 0xcc: /* fitoq */
  2641 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2642 + gen_helper_fitoq(cpu_fpr[rs2]);
  2643 + gen_op_store_QT0_fpr(QFPREG(rd));
  2644 + break;
  2645 + case 0xcd: /* fstoq */
  2646 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2647 + gen_helper_fstoq(cpu_fpr[rs2]);
  2648 + gen_op_store_QT0_fpr(QFPREG(rd));
  2649 + break;
  2650 + case 0xce: /* fdtoq */
  2651 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2652 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2653 + gen_helper_fdtoq();
  2654 + gen_op_store_QT0_fpr(QFPREG(rd));
  2655 + break;
  2656 + case 0xd1: /* fstoi */
  2657 + gen_clear_float_exceptions();
  2658 + gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]);
  2659 + gen_helper_check_ieee_exceptions();
  2660 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2661 + break;
  2662 + case 0xd2: /* fdtoi */
  2663 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2664 + gen_clear_float_exceptions();
  2665 + gen_helper_fdtoi(cpu_tmp32);
  2666 + gen_helper_check_ieee_exceptions();
  2667 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2668 + break;
  2669 + case 0xd3: /* fqtoi */
  2670 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2671 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2672 + gen_clear_float_exceptions();
  2673 + gen_helper_fqtoi(cpu_tmp32);
  2674 + gen_helper_check_ieee_exceptions();
  2675 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2676 + break;
2681 #ifdef TARGET_SPARC64 2677 #ifdef TARGET_SPARC64
2682 - case 0x2: /* V9 fmovd */  
2683 - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],  
2684 - cpu_fpr[DFPREG(rs2)]);  
2685 - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],  
2686 - cpu_fpr[DFPREG(rs2) + 1]);  
2687 - break;  
2688 - case 0x3: /* V9 fmovq */  
2689 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2690 - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],  
2691 - cpu_fpr[QFPREG(rs2)]);  
2692 - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],  
2693 - cpu_fpr[QFPREG(rs2) + 1]);  
2694 - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],  
2695 - cpu_fpr[QFPREG(rs2) + 2]);  
2696 - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],  
2697 - cpu_fpr[QFPREG(rs2) + 3]);  
2698 - break;  
2699 - case 0x6: /* V9 fnegd */  
2700 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2701 - gen_helper_fnegd();  
2702 - gen_op_store_DT0_fpr(DFPREG(rd));  
2703 - break;  
2704 - case 0x7: /* V9 fnegq */  
2705 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2706 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2707 - gen_helper_fnegq();  
2708 - gen_op_store_QT0_fpr(QFPREG(rd));  
2709 - break;  
2710 - case 0xa: /* V9 fabsd */  
2711 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2712 - gen_helper_fabsd();  
2713 - gen_op_store_DT0_fpr(DFPREG(rd));  
2714 - break;  
2715 - case 0xb: /* V9 fabsq */  
2716 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2717 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2718 - gen_helper_fabsq();  
2719 - gen_op_store_QT0_fpr(QFPREG(rd));  
2720 - break;  
2721 - case 0x81: /* V9 fstox */  
2722 - gen_clear_float_exceptions();  
2723 - gen_helper_fstox(cpu_fpr[rs2]);  
2724 - gen_helper_check_ieee_exceptions();  
2725 - gen_op_store_DT0_fpr(DFPREG(rd));  
2726 - break;  
2727 - case 0x82: /* V9 fdtox */  
2728 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2729 - gen_clear_float_exceptions();  
2730 - gen_helper_fdtox();  
2731 - gen_helper_check_ieee_exceptions();  
2732 - gen_op_store_DT0_fpr(DFPREG(rd));  
2733 - break;  
2734 - case 0x83: /* V9 fqtox */  
2735 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2736 - gen_op_load_fpr_QT1(QFPREG(rs2));  
2737 - gen_clear_float_exceptions();  
2738 - gen_helper_fqtox();  
2739 - gen_helper_check_ieee_exceptions();  
2740 - gen_op_store_DT0_fpr(DFPREG(rd));  
2741 - break;  
2742 - case 0x84: /* V9 fxtos */  
2743 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2744 - gen_clear_float_exceptions();  
2745 - gen_helper_fxtos(cpu_tmp32);  
2746 - gen_helper_check_ieee_exceptions();  
2747 - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);  
2748 - break;  
2749 - case 0x88: /* V9 fxtod */  
2750 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2751 - gen_clear_float_exceptions();  
2752 - gen_helper_fxtod();  
2753 - gen_helper_check_ieee_exceptions();  
2754 - gen_op_store_DT0_fpr(DFPREG(rd));  
2755 - break;  
2756 - case 0x8c: /* V9 fxtoq */  
2757 - CHECK_FPU_FEATURE(dc, FLOAT128);  
2758 - gen_op_load_fpr_DT1(DFPREG(rs2));  
2759 - gen_clear_float_exceptions();  
2760 - gen_helper_fxtoq();  
2761 - gen_helper_check_ieee_exceptions();  
2762 - gen_op_store_QT0_fpr(QFPREG(rd));  
2763 - break; 2678 + case 0x2: /* V9 fmovd */
  2679 + tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
  2680 + tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
  2681 + cpu_fpr[DFPREG(rs2) + 1]);
  2682 + break;
  2683 + case 0x3: /* V9 fmovq */
  2684 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2685 + tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]);
  2686 + tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
  2687 + cpu_fpr[QFPREG(rs2) + 1]);
  2688 + tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
  2689 + cpu_fpr[QFPREG(rs2) + 2]);
  2690 + tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
  2691 + cpu_fpr[QFPREG(rs2) + 3]);
  2692 + break;
  2693 + case 0x6: /* V9 fnegd */
  2694 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2695 + gen_helper_fnegd();
  2696 + gen_op_store_DT0_fpr(DFPREG(rd));
  2697 + break;
  2698 + case 0x7: /* V9 fnegq */
  2699 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2700 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2701 + gen_helper_fnegq();
  2702 + gen_op_store_QT0_fpr(QFPREG(rd));
  2703 + break;
  2704 + case 0xa: /* V9 fabsd */
  2705 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2706 + gen_helper_fabsd();
  2707 + gen_op_store_DT0_fpr(DFPREG(rd));
  2708 + break;
  2709 + case 0xb: /* V9 fabsq */
  2710 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2711 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2712 + gen_helper_fabsq();
  2713 + gen_op_store_QT0_fpr(QFPREG(rd));
  2714 + break;
  2715 + case 0x81: /* V9 fstox */
  2716 + gen_clear_float_exceptions();
  2717 + gen_helper_fstox(cpu_fpr[rs2]);
  2718 + gen_helper_check_ieee_exceptions();
  2719 + gen_op_store_DT0_fpr(DFPREG(rd));
  2720 + break;
  2721 + case 0x82: /* V9 fdtox */
  2722 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2723 + gen_clear_float_exceptions();
  2724 + gen_helper_fdtox();
  2725 + gen_helper_check_ieee_exceptions();
  2726 + gen_op_store_DT0_fpr(DFPREG(rd));
  2727 + break;
  2728 + case 0x83: /* V9 fqtox */
  2729 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2730 + gen_op_load_fpr_QT1(QFPREG(rs2));
  2731 + gen_clear_float_exceptions();
  2732 + gen_helper_fqtox();
  2733 + gen_helper_check_ieee_exceptions();
  2734 + gen_op_store_DT0_fpr(DFPREG(rd));
  2735 + break;
  2736 + case 0x84: /* V9 fxtos */
  2737 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2738 + gen_clear_float_exceptions();
  2739 + gen_helper_fxtos(cpu_tmp32);
  2740 + gen_helper_check_ieee_exceptions();
  2741 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
  2742 + break;
  2743 + case 0x88: /* V9 fxtod */
  2744 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2745 + gen_clear_float_exceptions();
  2746 + gen_helper_fxtod();
  2747 + gen_helper_check_ieee_exceptions();
  2748 + gen_op_store_DT0_fpr(DFPREG(rd));
  2749 + break;
  2750 + case 0x8c: /* V9 fxtoq */
  2751 + CHECK_FPU_FEATURE(dc, FLOAT128);
  2752 + gen_op_load_fpr_DT1(DFPREG(rs2));
  2753 + gen_clear_float_exceptions();
  2754 + gen_helper_fxtoq();
  2755 + gen_helper_check_ieee_exceptions();
  2756 + gen_op_store_QT0_fpr(QFPREG(rd));
  2757 + break;
2764 #endif 2758 #endif
2765 - default:  
2766 - goto illegal_insn; 2759 + default:
  2760 + goto illegal_insn;
2767 } 2761 }
2768 } else if (xop == 0x35) { /* FPU Operations */ 2762 } else if (xop == 0x35) { /* FPU Operations */
2769 #ifdef TARGET_SPARC64 2763 #ifdef TARGET_SPARC64
@@ -2824,7 +2818,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2824,7 +2818,7 @@ static void disas_sparc_insn(DisasContext * dc)
2824 int l1; \ 2818 int l1; \
2825 \ 2819 \
2826 l1 = gen_new_label(); \ 2820 l1 = gen_new_label(); \
2827 - r_cond = tcg_temp_new(); \ 2821 + r_cond = tcg_temp_new(); \
2828 cond = GET_FIELD_SP(insn, 14, 17); \ 2822 cond = GET_FIELD_SP(insn, 14, 17); \
2829 gen_fcond(r_cond, fcc, cond); \ 2823 gen_fcond(r_cond, fcc, cond); \
2830 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 2824 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
@@ -2839,7 +2833,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2839,7 +2833,7 @@ static void disas_sparc_insn(DisasContext * dc)
2839 int l1; \ 2833 int l1; \
2840 \ 2834 \
2841 l1 = gen_new_label(); \ 2835 l1 = gen_new_label(); \
2842 - r_cond = tcg_temp_new(); \ 2836 + r_cond = tcg_temp_new(); \
2843 cond = GET_FIELD_SP(insn, 14, 17); \ 2837 cond = GET_FIELD_SP(insn, 14, 17); \
2844 gen_fcond(r_cond, fcc, cond); \ 2838 gen_fcond(r_cond, fcc, cond); \
2845 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 2839 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
@@ -2857,7 +2851,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2857,7 +2851,7 @@ static void disas_sparc_insn(DisasContext * dc)
2857 int l1; \ 2851 int l1; \
2858 \ 2852 \
2859 l1 = gen_new_label(); \ 2853 l1 = gen_new_label(); \
2860 - r_cond = tcg_temp_new(); \ 2854 + r_cond = tcg_temp_new(); \
2861 cond = GET_FIELD_SP(insn, 14, 17); \ 2855 cond = GET_FIELD_SP(insn, 14, 17); \
2862 gen_fcond(r_cond, fcc, cond); \ 2856 gen_fcond(r_cond, fcc, cond); \
2863 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 2857 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
@@ -2922,7 +2916,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2922,7 +2916,7 @@ static void disas_sparc_insn(DisasContext * dc)
2922 int l1; \ 2916 int l1; \
2923 \ 2917 \
2924 l1 = gen_new_label(); \ 2918 l1 = gen_new_label(); \
2925 - r_cond = tcg_temp_new(); \ 2919 + r_cond = tcg_temp_new(); \
2926 cond = GET_FIELD_SP(insn, 14, 17); \ 2920 cond = GET_FIELD_SP(insn, 14, 17); \
2927 gen_cond(r_cond, icc, cond); \ 2921 gen_cond(r_cond, icc, cond); \
2928 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 2922 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
@@ -2937,7 +2931,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2937,7 +2931,7 @@ static void disas_sparc_insn(DisasContext * dc)
2937 int l1; \ 2931 int l1; \
2938 \ 2932 \
2939 l1 = gen_new_label(); \ 2933 l1 = gen_new_label(); \
2940 - r_cond = tcg_temp_new(); \ 2934 + r_cond = tcg_temp_new(); \
2941 cond = GET_FIELD_SP(insn, 14, 17); \ 2935 cond = GET_FIELD_SP(insn, 14, 17); \
2942 gen_cond(r_cond, icc, cond); \ 2936 gen_cond(r_cond, icc, cond); \
2943 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 2937 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
@@ -2955,7 +2949,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2955,7 +2949,7 @@ static void disas_sparc_insn(DisasContext * dc)
2955 int l1; \ 2949 int l1; \
2956 \ 2950 \
2957 l1 = gen_new_label(); \ 2951 l1 = gen_new_label(); \
2958 - r_cond = tcg_temp_new(); \ 2952 + r_cond = tcg_temp_new(); \
2959 cond = GET_FIELD_SP(insn, 14, 17); \ 2953 cond = GET_FIELD_SP(insn, 14, 17); \
2960 gen_cond(r_cond, icc, cond); \ 2954 gen_cond(r_cond, icc, cond); \
2961 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 2955 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
@@ -4629,7 +4623,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4629,7 +4623,7 @@ static void disas_sparc_insn(DisasContext * dc)
4629 default: 4623 default:
4630 goto illegal_insn; 4624 goto illegal_insn;
4631 } 4625 }
4632 - } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ 4626 + } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
4633 xop == 0xe || xop == 0x1e) { 4627 xop == 0xe || xop == 0x1e) {
4634 gen_movl_reg_TN(rd, cpu_val); 4628 gen_movl_reg_TN(rd, cpu_val);
4635 switch (xop) { 4629 switch (xop) {
@@ -4822,8 +4816,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4822,8 +4816,7 @@ static void disas_sparc_insn(DisasContext * dc)
4822 default: 4816 default:
4823 goto illegal_insn; 4817 goto illegal_insn;
4824 } 4818 }
4825 - }  
4826 - else 4819 + } else
4827 goto illegal_insn; 4820 goto illegal_insn;
4828 } 4821 }
4829 break; 4822 break;