gwj / at91sam9263 · Commits

Commit d9bea114849319e2dd31f027411089575f1d23a1

Authored by aurel32
1 parent f8393946

target-mips: variable names consistency 

Use a consistent naming of arguments and TCG variables across the whole
file, the same as in tcg/tcg-op.h:
- arg1, arg2, ... for arguments
- t0, t1, t2, ... for variables

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7106 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 768 additions and 766 deletions
target-mips/op_helper.c
  View file @d9bea11
... ... @@ -67,25 +67,25 @@ static void do_restore_state (void *pc_ptr)
67 67 }
68 68 #endif
69 69  
70   -target_ulong helper_clo (target_ulong t0)
  70 +target_ulong helper_clo (target_ulong arg1)
71 71 {
72   - return clo32(t0);
  72 + return clo32(arg1);
73 73 }
74 74  
75   -target_ulong helper_clz (target_ulong t0)
  75 +target_ulong helper_clz (target_ulong arg1)
76 76 {
77   - return clz32(t0);
  77 + return clz32(arg1);
78 78 }
79 79  
80 80 #if defined(TARGET_MIPS64)
81   -target_ulong helper_dclo (target_ulong t0)
  81 +target_ulong helper_dclo (target_ulong arg1)
82 82 {
83   - return clo64(t0);
  83 + return clo64(arg1);
84 84 }
85 85  
86   -target_ulong helper_dclz (target_ulong t0)
  86 +target_ulong helper_dclz (target_ulong arg1)
87 87 {
88   - return clz64(t0);
  88 + return clz64(arg1);
89 89 }
90 90 #endif /* TARGET_MIPS64 */
91 91  
... ... @@ -101,126 +101,126 @@ static inline void set_HILO (uint64_t HILO)
101 101 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
102 102 }
103 103  
104   -static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
  104 +static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
105 105 {
106 106 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
107   - t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
  107 + arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
108 108 }
109 109  
110   -static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
  110 +static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
111 111 {
112   - t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
  112 + arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
113 113 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
114 114 }
115 115  
116 116 /* Multiplication variants of the vr54xx. */
117   -target_ulong helper_muls (target_ulong t0, target_ulong t1)
  117 +target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
118 118 {
119   - set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  119 + set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
120 120  
121   - return t0;
  121 + return arg1;
122 122 }
123 123  
124   -target_ulong helper_mulsu (target_ulong t0, target_ulong t1)
  124 +target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
125 125 {
126   - set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  126 + set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
127 127  
128   - return t0;
  128 + return arg1;
129 129 }
130 130  
131   -target_ulong helper_macc (target_ulong t0, target_ulong t1)
  131 +target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
132 132 {
133   - set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  133 + set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
134 134  
135   - return t0;
  135 + return arg1;
136 136 }
137 137  
138   -target_ulong helper_macchi (target_ulong t0, target_ulong t1)
  138 +target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
139 139 {
140   - set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  140 + set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
141 141  
142   - return t0;
  142 + return arg1;
143 143 }
144 144  
145   -target_ulong helper_maccu (target_ulong t0, target_ulong t1)
  145 +target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
146 146 {
147   - set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  147 + set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
148 148  
149   - return t0;
  149 + return arg1;
150 150 }
151 151  
152   -target_ulong helper_macchiu (target_ulong t0, target_ulong t1)
  152 +target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
153 153 {
154   - set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  154 + set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
155 155  
156   - return t0;
  156 + return arg1;
157 157 }
158 158  
159   -target_ulong helper_msac (target_ulong t0, target_ulong t1)
  159 +target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
160 160 {
161   - set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  161 + set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
162 162  
163   - return t0;
  163 + return arg1;
164 164 }
165 165  
166   -target_ulong helper_msachi (target_ulong t0, target_ulong t1)
  166 +target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
167 167 {
168   - set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  168 + set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
169 169  
170   - return t0;
  170 + return arg1;
171 171 }
172 172  
173   -target_ulong helper_msacu (target_ulong t0, target_ulong t1)
  173 +target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
174 174 {
175   - set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  175 + set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
176 176  
177   - return t0;
  177 + return arg1;
178 178 }
179 179  
180   -target_ulong helper_msachiu (target_ulong t0, target_ulong t1)
  180 +target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
181 181 {
182   - set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  182 + set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
183 183  
184   - return t0;
  184 + return arg1;
185 185 }
186 186  
187   -target_ulong helper_mulhi (target_ulong t0, target_ulong t1)
  187 +target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
188 188 {
189   - set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
  189 + set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
190 190  
191   - return t0;
  191 + return arg1;
192 192 }
193 193  
194   -target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)
  194 +target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
195 195 {
196   - set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
  196 + set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
197 197  
198   - return t0;
  198 + return arg1;
199 199 }
200 200  
201   -target_ulong helper_mulshi (target_ulong t0, target_ulong t1)
  201 +target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
202 202 {
203   - set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  203 + set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
204 204  
205   - return t0;
  205 + return arg1;
206 206 }
207 207  
208   -target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)
  208 +target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
209 209 {
210   - set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  210 + set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
211 211  
212   - return t0;
  212 + return arg1;
213 213 }
214 214  
215 215 #ifdef TARGET_MIPS64
216   -void helper_dmult (target_ulong t0, target_ulong t1)
  216 +void helper_dmult (target_ulong arg1, target_ulong arg2)
217 217 {
218   - muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
  218 + muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
219 219 }
220 220  
221   -void helper_dmultu (target_ulong t0, target_ulong t1)
  221 +void helper_dmultu (target_ulong arg1, target_ulong arg2)
222 222 {
223   - mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
  223 + mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
224 224 }
225 225 #endif
226 226  
... ... @@ -232,7 +232,7 @@ void helper_dmultu (target_ulong t0, target_ulong t1)
232 232 #define GET_OFFSET(addr, offset) (addr - (offset))
233 233 #endif
234 234  
235   -target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
  235 +target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
236 236 {
237 237 target_ulong tmp;
238 238  
... ... @@ -249,27 +249,27 @@ target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
249 249 case 2: ldfun = ldub_user; break;
250 250 }
251 251 #endif
252   - tmp = ldfun(t0);
253   - t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
  252 + tmp = ldfun(arg2);
  253 + arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
254 254  
255   - if (GET_LMASK(t0) <= 2) {
256   - tmp = ldfun(GET_OFFSET(t0, 1));
257   - t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
  255 + if (GET_LMASK(arg2) <= 2) {
  256 + tmp = ldfun(GET_OFFSET(arg2, 1));
  257 + arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
258 258 }
259 259  
260   - if (GET_LMASK(t0) <= 1) {
261   - tmp = ldfun(GET_OFFSET(t0, 2));
262   - t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
  260 + if (GET_LMASK(arg2) <= 1) {
  261 + tmp = ldfun(GET_OFFSET(arg2, 2));
  262 + arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
263 263 }
264 264  
265   - if (GET_LMASK(t0) == 0) {
266   - tmp = ldfun(GET_OFFSET(t0, 3));
267   - t1 = (t1 & 0xFFFFFF00) | tmp;
  265 + if (GET_LMASK(arg2) == 0) {
  266 + tmp = ldfun(GET_OFFSET(arg2, 3));
  267 + arg1 = (arg1 & 0xFFFFFF00) | tmp;
268 268 }
269   - return (int32_t)t1;
  269 + return (int32_t)arg1;
270 270 }
271 271  
272   -target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
  272 +target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
273 273 {
274 274 target_ulong tmp;
275 275  
... ... @@ -286,27 +286,27 @@ target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
286 286 case 2: ldfun = ldub_user; break;
287 287 }
288 288 #endif
289   - tmp = ldfun(t0);
290   - t1 = (t1 & 0xFFFFFF00) | tmp;
  289 + tmp = ldfun(arg2);
  290 + arg1 = (arg1 & 0xFFFFFF00) | tmp;
291 291  
292   - if (GET_LMASK(t0) >= 1) {
293   - tmp = ldfun(GET_OFFSET(t0, -1));
294   - t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
  292 + if (GET_LMASK(arg2) >= 1) {
  293 + tmp = ldfun(GET_OFFSET(arg2, -1));
  294 + arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
295 295 }
296 296  
297   - if (GET_LMASK(t0) >= 2) {
298   - tmp = ldfun(GET_OFFSET(t0, -2));
299   - t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
  297 + if (GET_LMASK(arg2) >= 2) {
  298 + tmp = ldfun(GET_OFFSET(arg2, -2));
  299 + arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
300 300 }
301 301  
302   - if (GET_LMASK(t0) == 3) {
303   - tmp = ldfun(GET_OFFSET(t0, -3));
304   - t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
  302 + if (GET_LMASK(arg2) == 3) {
  303 + tmp = ldfun(GET_OFFSET(arg2, -3));
  304 + arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
305 305 }
306   - return (int32_t)t1;
  306 + return (int32_t)arg1;
307 307 }
308 308  
309   -void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
  309 +void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
310 310 {
311 311 #ifdef CONFIG_USER_ONLY
312 312 #define stfun stb_raw
... ... @@ -321,19 +321,19 @@ void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
321 321 case 2: stfun = stb_user; break;
322 322 }
323 323 #endif
324   - stfun(t0, (uint8_t)(t1 >> 24));
  324 + stfun(arg2, (uint8_t)(arg1 >> 24));
325 325  
326   - if (GET_LMASK(t0) <= 2)
327   - stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
  326 + if (GET_LMASK(arg2) <= 2)
  327 + stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16));
328 328  
329   - if (GET_LMASK(t0) <= 1)
330   - stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
  329 + if (GET_LMASK(arg2) <= 1)
  330 + stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8));
331 331  
332   - if (GET_LMASK(t0) == 0)
333   - stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
  332 + if (GET_LMASK(arg2) == 0)
  333 + stfun(GET_OFFSET(arg2, 3), (uint8_t)arg1);
334 334 }
335 335  
336   -void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
  336 +void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
337 337 {
338 338 #ifdef CONFIG_USER_ONLY
339 339 #define stfun stb_raw
... ... @@ -348,16 +348,16 @@ void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
348 348 case 2: stfun = stb_user; break;
349 349 }
350 350 #endif
351   - stfun(t0, (uint8_t)t1);
  351 + stfun(arg2, (uint8_t)arg1);
352 352  
353   - if (GET_LMASK(t0) >= 1)
354   - stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
  353 + if (GET_LMASK(arg2) >= 1)
  354 + stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
355 355  
356   - if (GET_LMASK(t0) >= 2)
357   - stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
  356 + if (GET_LMASK(arg2) >= 2)
  357 + stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
358 358  
359   - if (GET_LMASK(t0) == 3)
360   - stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
  359 + if (GET_LMASK(arg2) == 3)
  360 + stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
361 361 }
362 362  
363 363 #if defined(TARGET_MIPS64)
... ... @@ -370,7 +370,7 @@ void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
370 370 #define GET_LMASK64(v) (((v) & 7) ^ 7)
371 371 #endif
372 372  
373   -target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
  373 +target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
374 374 {
375 375 uint64_t tmp;
376 376  
... ... @@ -387,48 +387,48 @@ target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
387 387 case 2: ldfun = ldub_user; break;
388 388 }
389 389 #endif
390   - tmp = ldfun(t0);
391   - t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
  390 + tmp = ldfun(arg2);
  391 + arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
392 392  
393   - if (GET_LMASK64(t0) <= 6) {
394   - tmp = ldfun(GET_OFFSET(t0, 1));
395   - t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
  393 + if (GET_LMASK64(arg2) <= 6) {
  394 + tmp = ldfun(GET_OFFSET(arg2, 1));
  395 + arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
396 396 }
397 397  
398   - if (GET_LMASK64(t0) <= 5) {
399   - tmp = ldfun(GET_OFFSET(t0, 2));
400   - t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
  398 + if (GET_LMASK64(arg2) <= 5) {
  399 + tmp = ldfun(GET_OFFSET(arg2, 2));
  400 + arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
401 401 }
402 402  
403   - if (GET_LMASK64(t0) <= 4) {
404   - tmp = ldfun(GET_OFFSET(t0, 3));
405   - t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
  403 + if (GET_LMASK64(arg2) <= 4) {
  404 + tmp = ldfun(GET_OFFSET(arg2, 3));
  405 + arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
406 406 }
407 407  
408   - if (GET_LMASK64(t0) <= 3) {
409   - tmp = ldfun(GET_OFFSET(t0, 4));
410   - t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
  408 + if (GET_LMASK64(arg2) <= 3) {
  409 + tmp = ldfun(GET_OFFSET(arg2, 4));
  410 + arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
411 411 }
412 412  
413   - if (GET_LMASK64(t0) <= 2) {
414   - tmp = ldfun(GET_OFFSET(t0, 5));
415   - t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
  413 + if (GET_LMASK64(arg2) <= 2) {
  414 + tmp = ldfun(GET_OFFSET(arg2, 5));
  415 + arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
416 416 }
417 417  
418   - if (GET_LMASK64(t0) <= 1) {
419   - tmp = ldfun(GET_OFFSET(t0, 6));
420   - t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
  418 + if (GET_LMASK64(arg2) <= 1) {
  419 + tmp = ldfun(GET_OFFSET(arg2, 6));
  420 + arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
421 421 }
422 422  
423   - if (GET_LMASK64(t0) == 0) {
424   - tmp = ldfun(GET_OFFSET(t0, 7));
425   - t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
  423 + if (GET_LMASK64(arg2) == 0) {
  424 + tmp = ldfun(GET_OFFSET(arg2, 7));
  425 + arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
426 426 }
427 427  
428   - return t1;
  428 + return arg1;
429 429 }
430 430  
431   -target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
  431 +target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
432 432 {
433 433 uint64_t tmp;
434 434  
... ... @@ -445,48 +445,48 @@ target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
445 445 case 2: ldfun = ldub_user; break;
446 446 }
447 447 #endif
448   - tmp = ldfun(t0);
449   - t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
  448 + tmp = ldfun(arg2);
  449 + arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
450 450  
451   - if (GET_LMASK64(t0) >= 1) {
452   - tmp = ldfun(GET_OFFSET(t0, -1));
453   - t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
  451 + if (GET_LMASK64(arg2) >= 1) {
  452 + tmp = ldfun(GET_OFFSET(arg2, -1));
  453 + arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
454 454 }
455 455  
456   - if (GET_LMASK64(t0) >= 2) {
457   - tmp = ldfun(GET_OFFSET(t0, -2));
458   - t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
  456 + if (GET_LMASK64(arg2) >= 2) {
  457 + tmp = ldfun(GET_OFFSET(arg2, -2));
  458 + arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
459 459 }
460 460  
461   - if (GET_LMASK64(t0) >= 3) {
462   - tmp = ldfun(GET_OFFSET(t0, -3));
463   - t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
  461 + if (GET_LMASK64(arg2) >= 3) {
  462 + tmp = ldfun(GET_OFFSET(arg2, -3));
  463 + arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
464 464 }
465 465  
466   - if (GET_LMASK64(t0) >= 4) {
467   - tmp = ldfun(GET_OFFSET(t0, -4));
468   - t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
  466 + if (GET_LMASK64(arg2) >= 4) {
  467 + tmp = ldfun(GET_OFFSET(arg2, -4));
  468 + arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
469 469 }
470 470  
471   - if (GET_LMASK64(t0) >= 5) {
472   - tmp = ldfun(GET_OFFSET(t0, -5));
473   - t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
  471 + if (GET_LMASK64(arg2) >= 5) {
  472 + tmp = ldfun(GET_OFFSET(arg2, -5));
  473 + arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
474 474 }
475 475  
476   - if (GET_LMASK64(t0) >= 6) {
477   - tmp = ldfun(GET_OFFSET(t0, -6));
478   - t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
  476 + if (GET_LMASK64(arg2) >= 6) {
  477 + tmp = ldfun(GET_OFFSET(arg2, -6));
  478 + arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
479 479 }
480 480  
481   - if (GET_LMASK64(t0) == 7) {
482   - tmp = ldfun(GET_OFFSET(t0, -7));
483   - t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
  481 + if (GET_LMASK64(arg2) == 7) {
  482 + tmp = ldfun(GET_OFFSET(arg2, -7));
  483 + arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
484 484 }
485 485  
486   - return t1;
  486 + return arg1;
487 487 }
488 488  
489   -void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
  489 +void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
490 490 {
491 491 #ifdef CONFIG_USER_ONLY
492 492 #define stfun stb_raw
... ... @@ -501,31 +501,31 @@ void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
501 501 case 2: stfun = stb_user; break;
502 502 }
503 503 #endif
504   - stfun(t0, (uint8_t)(t1 >> 56));
  504 + stfun(arg2, (uint8_t)(arg1 >> 56));
505 505  
506   - if (GET_LMASK64(t0) <= 6)
507   - stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
  506 + if (GET_LMASK64(arg2) <= 6)
  507 + stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48));
508 508  
509   - if (GET_LMASK64(t0) <= 5)
510   - stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
  509 + if (GET_LMASK64(arg2) <= 5)
  510 + stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40));
511 511  
512   - if (GET_LMASK64(t0) <= 4)
513   - stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
  512 + if (GET_LMASK64(arg2) <= 4)
  513 + stfun(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32));
514 514  
515   - if (GET_LMASK64(t0) <= 3)
516   - stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
  515 + if (GET_LMASK64(arg2) <= 3)
  516 + stfun(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24));
517 517  
518   - if (GET_LMASK64(t0) <= 2)
519   - stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
  518 + if (GET_LMASK64(arg2) <= 2)
  519 + stfun(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16));
520 520  
521   - if (GET_LMASK64(t0) <= 1)
522   - stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
  521 + if (GET_LMASK64(arg2) <= 1)
  522 + stfun(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8));
523 523  
524   - if (GET_LMASK64(t0) <= 0)
525   - stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
  524 + if (GET_LMASK64(arg2) <= 0)
  525 + stfun(GET_OFFSET(arg2, 7), (uint8_t)arg1);
526 526 }
527 527  
528   -void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
  528 +void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
529 529 {
530 530 #ifdef CONFIG_USER_ONLY
531 531 #define stfun stb_raw
... ... @@ -540,28 +540,28 @@ void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
540 540 case 2: stfun = stb_user; break;
541 541 }
542 542 #endif
543   - stfun(t0, (uint8_t)t1);
  543 + stfun(arg2, (uint8_t)arg1);
544 544  
545   - if (GET_LMASK64(t0) >= 1)
546   - stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
  545 + if (GET_LMASK64(arg2) >= 1)
  546 + stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
547 547  
548   - if (GET_LMASK64(t0) >= 2)
549   - stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
  548 + if (GET_LMASK64(arg2) >= 2)
  549 + stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
550 550  
551   - if (GET_LMASK64(t0) >= 3)
552   - stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
  551 + if (GET_LMASK64(arg2) >= 3)
  552 + stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
553 553  
554   - if (GET_LMASK64(t0) >= 4)
555   - stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
  554 + if (GET_LMASK64(arg2) >= 4)
  555 + stfun(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32));
556 556  
557   - if (GET_LMASK64(t0) >= 5)
558   - stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
  557 + if (GET_LMASK64(arg2) >= 5)
  558 + stfun(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40));
559 559  
560   - if (GET_LMASK64(t0) >= 6)
561   - stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
  560 + if (GET_LMASK64(arg2) >= 6)
  561 + stfun(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48));
562 562  
563   - if (GET_LMASK64(t0) == 7)
564   - stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
  563 + if (GET_LMASK64(arg2) == 7)
  564 + stfun(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56));
565 565 }
566 566 #endif /* TARGET_MIPS64 */
567 567  
... ... @@ -805,7 +805,7 @@ target_ulong helper_dmfc0_watchlo (uint32_t sel)
805 805 }
806 806 #endif /* TARGET_MIPS64 */
807 807  
808   -void helper_mtc0_index (target_ulong t0)
  808 +void helper_mtc0_index (target_ulong arg1)
809 809 {
810 810 int num = 1;
811 811 unsigned int tmp = env->tlb->nb_tlb;
... ... @@ -814,10 +814,10 @@ void helper_mtc0_index (target_ulong t0)
814 814 tmp >>= 1;
815 815 num <<= 1;
816 816 } while (tmp);
817   - env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
  817 + env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
818 818 }
819 819  
820   -void helper_mtc0_mvpcontrol (target_ulong t0)
  820 +void helper_mtc0_mvpcontrol (target_ulong arg1)
821 821 {
822 822 uint32_t mask = 0;
823 823 uint32_t newval;
... ... @@ -827,21 +827,21 @@ void helper_mtc0_mvpcontrol (target_ulong t0)
827 827 (1 << CP0MVPCo_EVP);
828 828 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
829 829 mask |= (1 << CP0MVPCo_STLB);
830   - newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
  830 + newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
831 831  
832 832 // TODO: Enable/disable shared TLB, enable/disable VPEs.
833 833  
834 834 env->mvp->CP0_MVPControl = newval;
835 835 }
836 836  
837   -void helper_mtc0_vpecontrol (target_ulong t0)
  837 +void helper_mtc0_vpecontrol (target_ulong arg1)
838 838 {
839 839 uint32_t mask;
840 840 uint32_t newval;
841 841  
842 842 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
843 843 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
844   - newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
  844 + newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
845 845  
846 846 /* Yield scheduler intercept not implemented. */
847 847 /* Gating storage scheduler intercept not implemented. */
... ... @@ -851,7 +851,7 @@ void helper_mtc0_vpecontrol (target_ulong t0)
851 851 env->CP0_VPEControl = newval;
852 852 }
853 853  
854   -void helper_mtc0_vpeconf0 (target_ulong t0)
  854 +void helper_mtc0_vpeconf0 (target_ulong arg1)
855 855 {
856 856 uint32_t mask = 0;
857 857 uint32_t newval;
... ... @@ -861,14 +861,14 @@ void helper_mtc0_vpeconf0 (target_ulong t0)
861 861 mask |= (0xff << CP0VPEC0_XTC);
862 862 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
863 863 }
864   - newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
  864 + newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
865 865  
866 866 // TODO: TC exclusive handling due to ERL/EXL.
867 867  
868 868 env->CP0_VPEConf0 = newval;
869 869 }
870 870  
871   -void helper_mtc0_vpeconf1 (target_ulong t0)
  871 +void helper_mtc0_vpeconf1 (target_ulong arg1)
872 872 {
873 873 uint32_t mask = 0;
874 874 uint32_t newval;
... ... @@ -876,7 +876,7 @@ void helper_mtc0_vpeconf1 (target_ulong t0)
876 876 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
877 877 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
878 878 (0xff << CP0VPEC1_NCP1);
879   - newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
  879 + newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
880 880  
881 881 /* UDI not implemented. */
882 882 /* CP2 not implemented. */
... ... @@ -886,60 +886,60 @@ void helper_mtc0_vpeconf1 (target_ulong t0)
886 886 env->CP0_VPEConf1 = newval;
887 887 }
888 888  
889   -void helper_mtc0_yqmask (target_ulong t0)
  889 +void helper_mtc0_yqmask (target_ulong arg1)
890 890 {
891 891 /* Yield qualifier inputs not implemented. */
892 892 env->CP0_YQMask = 0x00000000;
893 893 }
894 894  
895   -void helper_mtc0_vpeopt (target_ulong t0)
  895 +void helper_mtc0_vpeopt (target_ulong arg1)
896 896 {
897   - env->CP0_VPEOpt = t0 & 0x0000ffff;
  897 + env->CP0_VPEOpt = arg1 & 0x0000ffff;
898 898 }
899 899  
900   -void helper_mtc0_entrylo0 (target_ulong t0)
  900 +void helper_mtc0_entrylo0 (target_ulong arg1)
901 901 {
902 902 /* Large physaddr (PABITS) not implemented */
903 903 /* 1k pages not implemented */
904   - env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
  904 + env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
905 905 }
906 906  
907   -void helper_mtc0_tcstatus (target_ulong t0)
  907 +void helper_mtc0_tcstatus (target_ulong arg1)
908 908 {
909 909 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
910 910 uint32_t newval;
911 911  
912   - newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask);
  912 + newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
913 913  
914 914 // TODO: Sync with CP0_Status.
915 915  
916 916 env->active_tc.CP0_TCStatus = newval;
917 917 }
918 918  
919   -void helper_mttc0_tcstatus (target_ulong t0)
  919 +void helper_mttc0_tcstatus (target_ulong arg1)
920 920 {
921 921 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
922 922  
923 923 // TODO: Sync with CP0_Status.
924 924  
925 925 if (other_tc == env->current_tc)
926   - env->active_tc.CP0_TCStatus = t0;
  926 + env->active_tc.CP0_TCStatus = arg1;
927 927 else
928   - env->tcs[other_tc].CP0_TCStatus = t0;
  928 + env->tcs[other_tc].CP0_TCStatus = arg1;
929 929 }
930 930  
931   -void helper_mtc0_tcbind (target_ulong t0)
  931 +void helper_mtc0_tcbind (target_ulong arg1)
932 932 {
933 933 uint32_t mask = (1 << CP0TCBd_TBE);
934 934 uint32_t newval;
935 935  
936 936 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
937 937 mask |= (1 << CP0TCBd_CurVPE);
938   - newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
  938 + newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
939 939 env->active_tc.CP0_TCBind = newval;
940 940 }
941 941  
942   -void helper_mttc0_tcbind (target_ulong t0)
  942 +void helper_mttc0_tcbind (target_ulong arg1)
943 943 {
944 944 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
945 945 uint32_t mask = (1 << CP0TCBd_TBE);
... ... @@ -948,122 +948,122 @@ void helper_mttc0_tcbind (target_ulong t0)
948 948 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
949 949 mask |= (1 << CP0TCBd_CurVPE);
950 950 if (other_tc == env->current_tc) {
951   - newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
  951 + newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
952 952 env->active_tc.CP0_TCBind = newval;
953 953 } else {
954   - newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask);
  954 + newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
955 955 env->tcs[other_tc].CP0_TCBind = newval;
956 956 }
957 957 }
958 958  
959   -void helper_mtc0_tcrestart (target_ulong t0)
  959 +void helper_mtc0_tcrestart (target_ulong arg1)
960 960 {
961   - env->active_tc.PC = t0;
  961 + env->active_tc.PC = arg1;
962 962 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
963 963 env->CP0_LLAddr = 0ULL;
964 964 /* MIPS16 not implemented. */
965 965 }
966 966  
967   -void helper_mttc0_tcrestart (target_ulong t0)
  967 +void helper_mttc0_tcrestart (target_ulong arg1)
968 968 {
969 969 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
970 970  
971 971 if (other_tc == env->current_tc) {
972   - env->active_tc.PC = t0;
  972 + env->active_tc.PC = arg1;
973 973 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
974 974 env->CP0_LLAddr = 0ULL;
975 975 /* MIPS16 not implemented. */
976 976 } else {
977   - env->tcs[other_tc].PC = t0;
  977 + env->tcs[other_tc].PC = arg1;
978 978 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
979 979 env->CP0_LLAddr = 0ULL;
980 980 /* MIPS16 not implemented. */
981 981 }
982 982 }
983 983  
984   -void helper_mtc0_tchalt (target_ulong t0)
  984 +void helper_mtc0_tchalt (target_ulong arg1)
985 985 {
986   - env->active_tc.CP0_TCHalt = t0 & 0x1;
  986 + env->active_tc.CP0_TCHalt = arg1 & 0x1;
987 987  
988 988 // TODO: Halt TC / Restart (if allocated+active) TC.
989 989 }
990 990  
991   -void helper_mttc0_tchalt (target_ulong t0)
  991 +void helper_mttc0_tchalt (target_ulong arg1)
992 992 {
993 993 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
994 994  
995 995 // TODO: Halt TC / Restart (if allocated+active) TC.
996 996  
997 997 if (other_tc == env->current_tc)
998   - env->active_tc.CP0_TCHalt = t0;
  998 + env->active_tc.CP0_TCHalt = arg1;
999 999 else
1000   - env->tcs[other_tc].CP0_TCHalt = t0;
  1000 + env->tcs[other_tc].CP0_TCHalt = arg1;
1001 1001 }
1002 1002  
1003   -void helper_mtc0_tccontext (target_ulong t0)
  1003 +void helper_mtc0_tccontext (target_ulong arg1)
1004 1004 {
1005   - env->active_tc.CP0_TCContext = t0;
  1005 + env->active_tc.CP0_TCContext = arg1;
1006 1006 }
1007 1007  
1008   -void helper_mttc0_tccontext (target_ulong t0)
  1008 +void helper_mttc0_tccontext (target_ulong arg1)
1009 1009 {
1010 1010 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1011 1011  
1012 1012 if (other_tc == env->current_tc)
1013   - env->active_tc.CP0_TCContext = t0;
  1013 + env->active_tc.CP0_TCContext = arg1;
1014 1014 else
1015   - env->tcs[other_tc].CP0_TCContext = t0;
  1015 + env->tcs[other_tc].CP0_TCContext = arg1;
1016 1016 }
1017 1017  
1018   -void helper_mtc0_tcschedule (target_ulong t0)
  1018 +void helper_mtc0_tcschedule (target_ulong arg1)
1019 1019 {
1020   - env->active_tc.CP0_TCSchedule = t0;
  1020 + env->active_tc.CP0_TCSchedule = arg1;
1021 1021 }
1022 1022  
1023   -void helper_mttc0_tcschedule (target_ulong t0)
  1023 +void helper_mttc0_tcschedule (target_ulong arg1)
1024 1024 {
1025 1025 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1026 1026  
1027 1027 if (other_tc == env->current_tc)
1028   - env->active_tc.CP0_TCSchedule = t0;
  1028 + env->active_tc.CP0_TCSchedule = arg1;
1029 1029 else
1030   - env->tcs[other_tc].CP0_TCSchedule = t0;
  1030 + env->tcs[other_tc].CP0_TCSchedule = arg1;
1031 1031 }
1032 1032  
1033   -void helper_mtc0_tcschefback (target_ulong t0)
  1033 +void helper_mtc0_tcschefback (target_ulong arg1)
1034 1034 {
1035   - env->active_tc.CP0_TCScheFBack = t0;
  1035 + env->active_tc.CP0_TCScheFBack = arg1;
1036 1036 }
1037 1037  
1038   -void helper_mttc0_tcschefback (target_ulong t0)
  1038 +void helper_mttc0_tcschefback (target_ulong arg1)
1039 1039 {
1040 1040 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1041 1041  
1042 1042 if (other_tc == env->current_tc)
1043   - env->active_tc.CP0_TCScheFBack = t0;
  1043 + env->active_tc.CP0_TCScheFBack = arg1;
1044 1044 else
1045   - env->tcs[other_tc].CP0_TCScheFBack = t0;
  1045 + env->tcs[other_tc].CP0_TCScheFBack = arg1;
1046 1046 }
1047 1047  
1048   -void helper_mtc0_entrylo1 (target_ulong t0)
  1048 +void helper_mtc0_entrylo1 (target_ulong arg1)
1049 1049 {
1050 1050 /* Large physaddr (PABITS) not implemented */
1051 1051 /* 1k pages not implemented */
1052   - env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
  1052 + env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1053 1053 }
1054 1054  
1055   -void helper_mtc0_context (target_ulong t0)
  1055 +void helper_mtc0_context (target_ulong arg1)
1056 1056 {
1057   - env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
  1057 + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1058 1058 }
1059 1059  
1060   -void helper_mtc0_pagemask (target_ulong t0)
  1060 +void helper_mtc0_pagemask (target_ulong arg1)
1061 1061 {
1062 1062 /* 1k pages not implemented */
1063   - env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
  1063 + env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1064 1064 }
1065 1065  
1066   -void helper_mtc0_pagegrain (target_ulong t0)
  1066 +void helper_mtc0_pagegrain (target_ulong arg1)
1067 1067 {
1068 1068 /* SmartMIPS not implemented */
1069 1069 /* Large physaddr (PABITS) not implemented */
... ... @@ -1071,52 +1071,52 @@ void helper_mtc0_pagegrain (target_ulong t0)
1071 1071 env->CP0_PageGrain = 0;
1072 1072 }
1073 1073  
1074   -void helper_mtc0_wired (target_ulong t0)
  1074 +void helper_mtc0_wired (target_ulong arg1)
1075 1075 {
1076   - env->CP0_Wired = t0 % env->tlb->nb_tlb;
  1076 + env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1077 1077 }
1078 1078  
1079   -void helper_mtc0_srsconf0 (target_ulong t0)
  1079 +void helper_mtc0_srsconf0 (target_ulong arg1)
1080 1080 {
1081   - env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
  1081 + env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1082 1082 }
1083 1083  
1084   -void helper_mtc0_srsconf1 (target_ulong t0)
  1084 +void helper_mtc0_srsconf1 (target_ulong arg1)
1085 1085 {
1086   - env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
  1086 + env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1087 1087 }
1088 1088  
1089   -void helper_mtc0_srsconf2 (target_ulong t0)
  1089 +void helper_mtc0_srsconf2 (target_ulong arg1)
1090 1090 {
1091   - env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
  1091 + env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1092 1092 }
1093 1093  
1094   -void helper_mtc0_srsconf3 (target_ulong t0)
  1094 +void helper_mtc0_srsconf3 (target_ulong arg1)
1095 1095 {
1096   - env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
  1096 + env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1097 1097 }
1098 1098  
1099   -void helper_mtc0_srsconf4 (target_ulong t0)
  1099 +void helper_mtc0_srsconf4 (target_ulong arg1)
1100 1100 {
1101   - env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
  1101 + env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1102 1102 }
1103 1103  
1104   -void helper_mtc0_hwrena (target_ulong t0)
  1104 +void helper_mtc0_hwrena (target_ulong arg1)
1105 1105 {
1106   - env->CP0_HWREna = t0 & 0x0000000F;
  1106 + env->CP0_HWREna = arg1 & 0x0000000F;
1107 1107 }
1108 1108  
1109   -void helper_mtc0_count (target_ulong t0)
  1109 +void helper_mtc0_count (target_ulong arg1)
1110 1110 {
1111   - cpu_mips_store_count(env, t0);
  1111 + cpu_mips_store_count(env, arg1);
1112 1112 }
1113 1113  
1114   -void helper_mtc0_entryhi (target_ulong t0)
  1114 +void helper_mtc0_entryhi (target_ulong arg1)
1115 1115 {
1116 1116 target_ulong old, val;
1117 1117  
1118 1118 /* 1k pages not implemented */
1119   - val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
  1119 + val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1120 1120 #if defined(TARGET_MIPS64)
1121 1121 val &= env->SEGMask;
1122 1122 #endif
... ... @@ -1131,32 +1131,32 @@ void helper_mtc0_entryhi (target_ulong t0)
1131 1131 cpu_mips_tlb_flush(env, 1);
1132 1132 }
1133 1133  
1134   -void helper_mttc0_entryhi(target_ulong t0)
  1134 +void helper_mttc0_entryhi(target_ulong arg1)
1135 1135 {
1136 1136 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1137 1137 int32_t tcstatus;
1138 1138  
1139   - env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
  1139 + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
1140 1140 if (other_tc == env->current_tc) {
1141   - tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff);
  1141 + tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1142 1142 env->active_tc.CP0_TCStatus = tcstatus;
1143 1143 } else {
1144   - tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff);
  1144 + tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1145 1145 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1146 1146 }
1147 1147 }
1148 1148  
1149   -void helper_mtc0_compare (target_ulong t0)
  1149 +void helper_mtc0_compare (target_ulong arg1)
1150 1150 {
1151   - cpu_mips_store_compare(env, t0);
  1151 + cpu_mips_store_compare(env, arg1);
1152 1152 }
1153 1153  
1154   -void helper_mtc0_status (target_ulong t0)
  1154 +void helper_mtc0_status (target_ulong arg1)
1155 1155 {
1156 1156 uint32_t val, old;
1157 1157 uint32_t mask = env->CP0_Status_rw_bitmask;
1158 1158  
1159   - val = t0 & mask;
  1159 + val = arg1 & mask;
1160 1160 old = env->CP0_Status;
1161 1161 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1162 1162 compute_hflags(env);
... ... @@ -1175,34 +1175,34 @@ void helper_mtc0_status (target_ulong t0)
1175 1175 cpu_mips_update_irq(env);
1176 1176 }
1177 1177  
1178   -void helper_mttc0_status(target_ulong t0)
  1178 +void helper_mttc0_status(target_ulong arg1)
1179 1179 {
1180 1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181 1181 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
1182 1182  
1183   - env->CP0_Status = t0 & ~0xf1000018;
1184   - tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
1185   - tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1186   - tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
  1183 + env->CP0_Status = arg1 & ~0xf1000018;
  1184 + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
  1185 + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
  1186 + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1187 1187 if (other_tc == env->current_tc)
1188 1188 env->active_tc.CP0_TCStatus = tcstatus;
1189 1189 else
1190 1190 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1191 1191 }
1192 1192  
1193   -void helper_mtc0_intctl (target_ulong t0)
  1193 +void helper_mtc0_intctl (target_ulong arg1)
1194 1194 {
1195 1195 /* vectored interrupts not implemented, no performance counters. */
1196   - env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
  1196 + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
1197 1197 }
1198 1198  
1199   -void helper_mtc0_srsctl (target_ulong t0)
  1199 +void helper_mtc0_srsctl (target_ulong arg1)
1200 1200 {
1201 1201 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1202   - env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
  1202 + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1203 1203 }
1204 1204  
1205   -void helper_mtc0_cause (target_ulong t0)
  1205 +void helper_mtc0_cause (target_ulong arg1)
1206 1206 {
1207 1207 uint32_t mask = 0x00C00300;
1208 1208 uint32_t old = env->CP0_Cause;
... ... @@ -1210,7 +1210,7 @@ void helper_mtc0_cause (target_ulong t0)
1210 1210 if (env->insn_flags & ISA_MIPS32R2)
1211 1211 mask |= 1 << CP0Ca_DC;
1212 1212  
1213   - env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
  1213 + env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
1214 1214  
1215 1215 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1216 1216 if (env->CP0_Cause & (1 << CP0Ca_DC))
... ... @@ -1221,66 +1221,66 @@ void helper_mtc0_cause (target_ulong t0)
1221 1221  
1222 1222 /* Handle the software interrupt as an hardware one, as they
1223 1223 are very similar */
1224   - if (t0 & CP0Ca_IP_mask) {
  1224 + if (arg1 & CP0Ca_IP_mask) {
1225 1225 cpu_mips_update_irq(env);
1226 1226 }
1227 1227 }
1228 1228  
1229   -void helper_mtc0_ebase (target_ulong t0)
  1229 +void helper_mtc0_ebase (target_ulong arg1)
1230 1230 {
1231 1231 /* vectored interrupts not implemented */
1232 1232 /* Multi-CPU not implemented */
1233   - env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
  1233 + env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
1234 1234 }
1235 1235  
1236   -void helper_mtc0_config0 (target_ulong t0)
  1236 +void helper_mtc0_config0 (target_ulong arg1)
1237 1237 {
1238   - env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
  1238 + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1239 1239 }
1240 1240  
1241   -void helper_mtc0_config2 (target_ulong t0)
  1241 +void helper_mtc0_config2 (target_ulong arg1)
1242 1242 {
1243 1243 /* tertiary/secondary caches not implemented */
1244 1244 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1245 1245 }
1246 1246  
1247   -void helper_mtc0_watchlo (target_ulong t0, uint32_t sel)
  1247 +void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
1248 1248 {
1249 1249 /* Watch exceptions for instructions, data loads, data stores
1250 1250 not implemented. */
1251   - env->CP0_WatchLo[sel] = (t0 & ~0x7);
  1251 + env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1252 1252 }
1253 1253  
1254   -void helper_mtc0_watchhi (target_ulong t0, uint32_t sel)
  1254 +void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
1255 1255 {
1256   - env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1257   - env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
  1256 + env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
  1257 + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1258 1258 }
1259 1259  
1260   -void helper_mtc0_xcontext (target_ulong t0)
  1260 +void helper_mtc0_xcontext (target_ulong arg1)
1261 1261 {
1262 1262 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1263   - env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
  1263 + env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1264 1264 }
1265 1265  
1266   -void helper_mtc0_framemask (target_ulong t0)
  1266 +void helper_mtc0_framemask (target_ulong arg1)
1267 1267 {
1268   - env->CP0_Framemask = t0; /* XXX */
  1268 + env->CP0_Framemask = arg1; /* XXX */
1269 1269 }
1270 1270  
1271   -void helper_mtc0_debug (target_ulong t0)
  1271 +void helper_mtc0_debug (target_ulong arg1)
1272 1272 {
1273   - env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
1274   - if (t0 & (1 << CP0DB_DM))
  1273 + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
  1274 + if (arg1 & (1 << CP0DB_DM))
1275 1275 env->hflags |= MIPS_HFLAG_DM;
1276 1276 else
1277 1277 env->hflags &= ~MIPS_HFLAG_DM;
1278 1278 }
1279 1279  
1280   -void helper_mttc0_debug(target_ulong t0)
  1280 +void helper_mttc0_debug(target_ulong arg1)
1281 1281 {
1282 1282 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1283   - uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
  1283 + uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1284 1284  
1285 1285 /* XXX: Might be wrong, check with EJTAG spec. */
1286 1286 if (other_tc == env->current_tc)
... ... @@ -1288,32 +1288,32 @@ void helper_mttc0_debug(target_ulong t0)
1288 1288 else
1289 1289 env->tcs[other_tc].CP0_Debug_tcstatus = val;
1290 1290 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1291   - (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
  1291 + (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1292 1292 }
1293 1293  
1294   -void helper_mtc0_performance0 (target_ulong t0)
  1294 +void helper_mtc0_performance0 (target_ulong arg1)
1295 1295 {
1296   - env->CP0_Performance0 = t0 & 0x000007ff;
  1296 + env->CP0_Performance0 = arg1 & 0x000007ff;
1297 1297 }
1298 1298  
1299   -void helper_mtc0_taglo (target_ulong t0)
  1299 +void helper_mtc0_taglo (target_ulong arg1)
1300 1300 {
1301   - env->CP0_TagLo = t0 & 0xFFFFFCF6;
  1301 + env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1302 1302 }
1303 1303  
1304   -void helper_mtc0_datalo (target_ulong t0)
  1304 +void helper_mtc0_datalo (target_ulong arg1)
1305 1305 {
1306   - env->CP0_DataLo = t0; /* XXX */
  1306 + env->CP0_DataLo = arg1; /* XXX */
1307 1307 }
1308 1308  
1309   -void helper_mtc0_taghi (target_ulong t0)
  1309 +void helper_mtc0_taghi (target_ulong arg1)
1310 1310 {
1311   - env->CP0_TagHi = t0; /* XXX */
  1311 + env->CP0_TagHi = arg1; /* XXX */
1312 1312 }
1313 1313  
1314   -void helper_mtc0_datahi (target_ulong t0)
  1314 +void helper_mtc0_datahi (target_ulong arg1)
1315 1315 {
1316   - env->CP0_DataHi = t0; /* XXX */
  1316 + env->CP0_DataHi = arg1; /* XXX */
1317 1317 }
1318 1318  
1319 1319 /* MIPS MT functions */
... ... @@ -1367,106 +1367,106 @@ target_ulong helper_mftdsp(void)
1367 1367 return env->tcs[other_tc].DSPControl;
1368 1368 }
1369 1369  
1370   -void helper_mttgpr(target_ulong t0, uint32_t sel)
  1370 +void helper_mttgpr(target_ulong arg1, uint32_t sel)
1371 1371 {
1372 1372 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1373 1373  
1374 1374 if (other_tc == env->current_tc)
1375   - env->active_tc.gpr[sel] = t0;
  1375 + env->active_tc.gpr[sel] = arg1;
1376 1376 else
1377   - env->tcs[other_tc].gpr[sel] = t0;
  1377 + env->tcs[other_tc].gpr[sel] = arg1;
1378 1378 }
1379 1379  
1380   -void helper_mttlo(target_ulong t0, uint32_t sel)
  1380 +void helper_mttlo(target_ulong arg1, uint32_t sel)
1381 1381 {
1382 1382 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1383 1383  
1384 1384 if (other_tc == env->current_tc)
1385   - env->active_tc.LO[sel] = t0;
  1385 + env->active_tc.LO[sel] = arg1;
1386 1386 else
1387   - env->tcs[other_tc].LO[sel] = t0;
  1387 + env->tcs[other_tc].LO[sel] = arg1;
1388 1388 }
1389 1389  
1390   -void helper_mtthi(target_ulong t0, uint32_t sel)
  1390 +void helper_mtthi(target_ulong arg1, uint32_t sel)
1391 1391 {
1392 1392 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1393 1393  
1394 1394 if (other_tc == env->current_tc)
1395   - env->active_tc.HI[sel] = t0;
  1395 + env->active_tc.HI[sel] = arg1;
1396 1396 else
1397   - env->tcs[other_tc].HI[sel] = t0;
  1397 + env->tcs[other_tc].HI[sel] = arg1;
1398 1398 }
1399 1399  
1400   -void helper_mttacx(target_ulong t0, uint32_t sel)
  1400 +void helper_mttacx(target_ulong arg1, uint32_t sel)
1401 1401 {
1402 1402 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1403 1403  
1404 1404 if (other_tc == env->current_tc)
1405   - env->active_tc.ACX[sel] = t0;
  1405 + env->active_tc.ACX[sel] = arg1;
1406 1406 else
1407   - env->tcs[other_tc].ACX[sel] = t0;
  1407 + env->tcs[other_tc].ACX[sel] = arg1;
1408 1408 }
1409 1409  
1410   -void helper_mttdsp(target_ulong t0)
  1410 +void helper_mttdsp(target_ulong arg1)
1411 1411 {
1412 1412 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1413 1413  
1414 1414 if (other_tc == env->current_tc)
1415   - env->active_tc.DSPControl = t0;
  1415 + env->active_tc.DSPControl = arg1;
1416 1416 else
1417   - env->tcs[other_tc].DSPControl = t0;
  1417 + env->tcs[other_tc].DSPControl = arg1;
1418 1418 }
1419 1419  
1420 1420 /* MIPS MT functions */
1421   -target_ulong helper_dmt(target_ulong t0)
  1421 +target_ulong helper_dmt(target_ulong arg1)
1422 1422 {
1423 1423 // TODO
1424   - t0 = 0;
1425   - // rt = t0
  1424 + arg1 = 0;
  1425 + // rt = arg1
1426 1426  
1427   - return t0;
  1427 + return arg1;
1428 1428 }
1429 1429  
1430   -target_ulong helper_emt(target_ulong t0)
  1430 +target_ulong helper_emt(target_ulong arg1)
1431 1431 {
1432 1432 // TODO
1433   - t0 = 0;
1434   - // rt = t0
  1433 + arg1 = 0;
  1434 + // rt = arg1
1435 1435  
1436   - return t0;
  1436 + return arg1;
1437 1437 }
1438 1438  
1439   -target_ulong helper_dvpe(target_ulong t0)
  1439 +target_ulong helper_dvpe(target_ulong arg1)
1440 1440 {
1441 1441 // TODO
1442   - t0 = 0;
1443   - // rt = t0
  1442 + arg1 = 0;
  1443 + // rt = arg1
1444 1444  
1445   - return t0;
  1445 + return arg1;
1446 1446 }
1447 1447  
1448   -target_ulong helper_evpe(target_ulong t0)
  1448 +target_ulong helper_evpe(target_ulong arg1)
1449 1449 {
1450 1450 // TODO
1451   - t0 = 0;
1452   - // rt = t0
  1451 + arg1 = 0;
  1452 + // rt = arg1
1453 1453  
1454   - return t0;
  1454 + return arg1;
1455 1455 }
1456 1456 #endif /* !CONFIG_USER_ONLY */
1457 1457  
1458   -void helper_fork(target_ulong t0, target_ulong t1)
  1458 +void helper_fork(target_ulong arg1, target_ulong arg2)
1459 1459 {
1460   - // t0 = rt, t1 = rs
1461   - t0 = 0;
  1460 + // arg1 = rt, arg2 = rs
  1461 + arg1 = 0;
1462 1462 // TODO: store to TC register
1463 1463 }
1464 1464  
1465   -target_ulong helper_yield(target_ulong t0)
  1465 +target_ulong helper_yield(target_ulong arg1)
1466 1466 {
1467   - if (t0 < 0) {
  1467 + if (arg1 < 0) {
1468 1468 /* No scheduling policy implemented. */
1469   - if (t0 != -2) {
  1469 + if (arg1 != -2) {
1470 1470 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1471 1471 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1472 1472 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
... ... @@ -1474,14 +1474,14 @@ target_ulong helper_yield(target_ulong t0)
1474 1474 helper_raise_exception(EXCP_THREAD);
1475 1475 }
1476 1476 }
1477   - } else if (t0 == 0) {
  1477 + } else if (arg1 == 0) {
1478 1478 if (0 /* TODO: TC underflow */) {
1479 1479 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1480 1480 helper_raise_exception(EXCP_THREAD);
1481 1481 } else {
1482 1482 // TODO: Deallocate TC
1483 1483 }
1484   - } else if (t0 > 0) {
  1484 + } else if (arg1 > 0) {
1485 1485 /* Yield qualifier inputs not implemented. */
1486 1486 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1487 1487 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
... ... @@ -1884,53 +1884,53 @@ unsigned int ieee_rm[] = {
1884 1884  
1885 1885 target_ulong helper_cfc1 (uint32_t reg)
1886 1886 {
1887   - target_ulong t0;
  1887 + target_ulong arg1;
1888 1888  
1889 1889 switch (reg) {
1890 1890 case 0:
1891   - t0 = (int32_t)env->active_fpu.fcr0;
  1891 + arg1 = (int32_t)env->active_fpu.fcr0;
1892 1892 break;
1893 1893 case 25:
1894   - t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
  1894 + arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
1895 1895 break;
1896 1896 case 26:
1897   - t0 = env->active_fpu.fcr31 & 0x0003f07c;
  1897 + arg1 = env->active_fpu.fcr31 & 0x0003f07c;
1898 1898 break;
1899 1899 case 28:
1900   - t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
  1900 + arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
1901 1901 break;
1902 1902 default:
1903   - t0 = (int32_t)env->active_fpu.fcr31;
  1903 + arg1 = (int32_t)env->active_fpu.fcr31;
1904 1904 break;
1905 1905 }
1906 1906  
1907   - return t0;
  1907 + return arg1;
1908 1908 }
1909 1909  
1910   -void helper_ctc1 (target_ulong t0, uint32_t reg)
  1910 +void helper_ctc1 (target_ulong arg1, uint32_t reg)
1911 1911 {
1912 1912 switch(reg) {
1913 1913 case 25:
1914   - if (t0 & 0xffffff00)
  1914 + if (arg1 & 0xffffff00)
1915 1915 return;
1916   - env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
1917   - ((t0 & 0x1) << 23);
  1916 + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
  1917 + ((arg1 & 0x1) << 23);
1918 1918 break;
1919 1919 case 26:
1920   - if (t0 & 0x007c0000)
  1920 + if (arg1 & 0x007c0000)
1921 1921 return;
1922   - env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
  1922 + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
1923 1923 break;
1924 1924 case 28:
1925   - if (t0 & 0x007c0000)
  1925 + if (arg1 & 0x007c0000)
1926 1926 return;
1927   - env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
1928   - ((t0 & 0x4) << 22);
  1927 + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
  1928 + ((arg1 & 0x4) << 22);
1929 1929 break;
1930 1930 case 31:
1931   - if (t0 & 0x007c0000)
  1931 + if (arg1 & 0x007c0000)
1932 1932 return;
1933   - env->active_fpu.fcr31 = t0;
  1933 + env->active_fpu.fcr31 = arg1;
1934 1934 break;
1935 1935 default:
1936 1936 return;
... ...
target-mips/translate.c
  View file @d9bea11
... ... @@ -546,48 +546,48 @@ static inline void gen_store_ACX (TCGv t, int reg)
546 546 /* Moves to/from shadow registers. */
547 547 static inline void gen_load_srsgpr (int from, int to)
548 548 {
549   - TCGv r_tmp1 = tcg_temp_new();
  549 + TCGv t0 = tcg_temp_new();
550 550  
551 551 if (from == 0)
552   - tcg_gen_movi_tl(r_tmp1, 0);
  552 + tcg_gen_movi_tl(t0, 0);
553 553 else {
554   - TCGv_i32 r_tmp2 = tcg_temp_new_i32();
  554 + TCGv_i32 t2 = tcg_temp_new_i32();
555 555 TCGv_ptr addr = tcg_temp_new_ptr();
556 556  
557   - tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
558   - tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
559   - tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
560   - tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
561   - tcg_gen_ext_i32_ptr(addr, r_tmp2);
  557 + tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
  558 + tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
  559 + tcg_gen_andi_i32(t2, t2, 0xf);
  560 + tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
  561 + tcg_gen_ext_i32_ptr(addr, t2);
562 562 tcg_gen_add_ptr(addr, cpu_env, addr);
563 563  
564   - tcg_gen_ld_tl(r_tmp1, addr, sizeof(target_ulong) * from);
  564 + tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
565 565 tcg_temp_free_ptr(addr);
566   - tcg_temp_free_i32(r_tmp2);
  566 + tcg_temp_free_i32(t2);
567 567 }
568   - gen_store_gpr(r_tmp1, to);
569   - tcg_temp_free(r_tmp1);
  568 + gen_store_gpr(t0, to);
  569 + tcg_temp_free(t0);
570 570 }
571 571  
572 572 static inline void gen_store_srsgpr (int from, int to)
573 573 {
574 574 if (to != 0) {
575   - TCGv r_tmp1 = tcg_temp_new();
576   - TCGv_i32 r_tmp2 = tcg_temp_new_i32();
  575 + TCGv t0 = tcg_temp_new();
  576 + TCGv_i32 t2 = tcg_temp_new_i32();
577 577 TCGv_ptr addr = tcg_temp_new_ptr();
578 578  
579   - gen_load_gpr(r_tmp1, from);
580   - tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
581   - tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
582   - tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
583   - tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
584   - tcg_gen_ext_i32_ptr(addr, r_tmp2);
  579 + gen_load_gpr(t0, from);
  580 + tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
  581 + tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
  582 + tcg_gen_andi_i32(t2, t2, 0xf);
  583 + tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
  584 + tcg_gen_ext_i32_ptr(addr, t2);
585 585 tcg_gen_add_ptr(addr, cpu_env, addr);
586 586  
587   - tcg_gen_st_tl(r_tmp1, addr, sizeof(target_ulong) * to);
  587 + tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
588 588 tcg_temp_free_ptr(addr);
589   - tcg_temp_free_i32(r_tmp2);
590   - tcg_temp_free(r_tmp1);
  589 + tcg_temp_free_i32(t2);
  590 + tcg_temp_free(t0);
591 591 }
592 592 }
593 593  
... ... @@ -887,10 +887,10 @@ static inline void check_mips_64(DisasContext *ctx)
887 887 }
888 888  
889 889 /* load/store instructions. */
890   -#define OP_LD(insn,fname) \
891   -static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
892   -{ \
893   - tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
  890 +#define OP_LD(insn,fname) \
  891 +static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
  892 +{ \
  893 + tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
894 894 }
895 895 OP_LD(lb,ld8s);
896 896 OP_LD(lbu,ld8u);
... ... @@ -903,10 +903,10 @@ OP_LD(ld,ld64);
903 903 #endif
904 904 #undef OP_LD
905 905  
906   -#define OP_ST(insn,fname) \
907   -static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
908   -{ \
909   - tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
  906 +#define OP_ST(insn,fname) \
  907 +static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
  908 +{ \
  909 + tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
910 910 }
911 911 OP_ST(sb,st8);
912 912 OP_ST(sh,st16);
... ... @@ -916,12 +916,14 @@ OP_ST(sd,st64);
916 916 #endif
917 917 #undef OP_ST
918 918  
919   -#define OP_LD_ATOMIC(insn,fname) \
920   -static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
921   -{ \
922   - tcg_gen_mov_tl(t1, t0); \
923   - tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
924   - tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
  919 +#define OP_LD_ATOMIC(insn,fname) \
  920 +static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
  921 +{ \
  922 + TCGv t0 = tcg_temp_new(); \
  923 + tcg_gen_mov_tl(t0, arg1); \
  924 + tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
  925 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
  926 + tcg_temp_free(t0); \
925 927 }
926 928 OP_LD_ATOMIC(ll,ld32s);
927 929 #if defined(TARGET_MIPS64)
... ... @@ -929,28 +931,28 @@ OP_LD_ATOMIC(lld,ld64);
929 931 #endif
930 932 #undef OP_LD_ATOMIC
931 933  
932   -#define OP_ST_ATOMIC(insn,fname,almask) \
933   -static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
934   -{ \
935   - TCGv r_tmp = tcg_temp_new(); \
936   - int l1 = gen_new_label(); \
937   - int l2 = gen_new_label(); \
938   - int l3 = gen_new_label(); \
939   - \
940   - tcg_gen_andi_tl(r_tmp, t0, almask); \
941   - tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
942   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
943   - generate_exception(ctx, EXCP_AdES); \
944   - gen_set_label(l1); \
945   - tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
946   - tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
947   - tcg_temp_free(r_tmp); \
948   - tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
949   - tcg_gen_movi_tl(t0, 1); \
950   - tcg_gen_br(l3); \
951   - gen_set_label(l2); \
952   - tcg_gen_movi_tl(t0, 0); \
953   - gen_set_label(l3); \
  934 +#define OP_ST_ATOMIC(insn,fname,almask) \
  935 +static inline void op_ldst_##insn(TCGv ret, TCGv arg1, TCGv arg2, DisasContext *ctx) \
  936 +{ \
  937 + TCGv t0 = tcg_temp_new(); \
  938 + int l1 = gen_new_label(); \
  939 + int l2 = gen_new_label(); \
  940 + int l3 = gen_new_label(); \
  941 + \
  942 + tcg_gen_andi_tl(t0, arg2, almask); \
  943 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
  944 + tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
  945 + generate_exception(ctx, EXCP_AdES); \
  946 + gen_set_label(l1); \
  947 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
  948 + tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
  949 + tcg_temp_free(t0); \
  950 + tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
  951 + tcg_gen_movi_tl(ret, 1); \
  952 + tcg_gen_br(l3); \
  953 + gen_set_label(l2); \
  954 + tcg_gen_movi_tl(ret, 0); \
  955 + gen_set_label(l3); \
954 956 }
955 957 OP_ST_ATOMIC(sc,st32,0x3);
956 958 #if defined(TARGET_MIPS64)
... ... @@ -980,132 +982,132 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
980 982 #if defined(TARGET_MIPS64)
981 983 case OPC_LWU:
982 984 save_cpu_state(ctx, 0);
983   - op_ldst_lwu(t0, ctx);
  985 + op_ldst_lwu(t0, t0, ctx);
984 986 gen_store_gpr(t0, rt);
985 987 opn = "lwu";
986 988 break;
987 989 case OPC_LD:
988 990 save_cpu_state(ctx, 0);
989   - op_ldst_ld(t0, ctx);
  991 + op_ldst_ld(t0, t0, ctx);
990 992 gen_store_gpr(t0, rt);
991 993 opn = "ld";
992 994 break;
993 995 case OPC_LLD:
994 996 save_cpu_state(ctx, 0);
995   - op_ldst_lld(t0, t1, ctx);
  997 + op_ldst_lld(t0, t0, ctx);
996 998 gen_store_gpr(t0, rt);
997 999 opn = "lld";
998 1000 break;
999 1001 case OPC_SD:
1000 1002 save_cpu_state(ctx, 0);
1001 1003 gen_load_gpr(t1, rt);
1002   - op_ldst_sd(t0, t1, ctx);
  1004 + op_ldst_sd(t1, t0, ctx);
1003 1005 opn = "sd";
1004 1006 break;
1005 1007 case OPC_LDL:
1006 1008 save_cpu_state(ctx, 1);
1007 1009 gen_load_gpr(t1, rt);
1008   - gen_helper_3i(ldl, t1, t0, t1, ctx->mem_idx);
  1010 + gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
1009 1011 gen_store_gpr(t1, rt);
1010 1012 opn = "ldl";
1011 1013 break;
1012 1014 case OPC_SDL:
1013 1015 save_cpu_state(ctx, 1);
1014 1016 gen_load_gpr(t1, rt);
1015   - gen_helper_2i(sdl, t0, t1, ctx->mem_idx);
  1017 + gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
1016 1018 opn = "sdl";
1017 1019 break;
1018 1020 case OPC_LDR:
1019 1021 save_cpu_state(ctx, 1);
1020 1022 gen_load_gpr(t1, rt);
1021   - gen_helper_3i(ldr, t1, t0, t1, ctx->mem_idx);
  1023 + gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
1022 1024 gen_store_gpr(t1, rt);
1023 1025 opn = "ldr";
1024 1026 break;
1025 1027 case OPC_SDR:
1026 1028 save_cpu_state(ctx, 1);
1027 1029 gen_load_gpr(t1, rt);
1028   - gen_helper_2i(sdr, t0, t1, ctx->mem_idx);
  1030 + gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
1029 1031 opn = "sdr";
1030 1032 break;
1031 1033 #endif
1032 1034 case OPC_LW:
1033 1035 save_cpu_state(ctx, 0);
1034   - op_ldst_lw(t0, ctx);
  1036 + op_ldst_lw(t0, t0, ctx);
1035 1037 gen_store_gpr(t0, rt);
1036 1038 opn = "lw";
1037 1039 break;
1038 1040 case OPC_SW:
1039 1041 save_cpu_state(ctx, 0);
1040 1042 gen_load_gpr(t1, rt);
1041   - op_ldst_sw(t0, t1, ctx);
  1043 + op_ldst_sw(t1, t0, ctx);
1042 1044 opn = "sw";
1043 1045 break;
1044 1046 case OPC_LH:
1045 1047 save_cpu_state(ctx, 0);
1046   - op_ldst_lh(t0, ctx);
  1048 + op_ldst_lh(t0, t0, ctx);
1047 1049 gen_store_gpr(t0, rt);
1048 1050 opn = "lh";
1049 1051 break;
1050 1052 case OPC_SH:
1051 1053 save_cpu_state(ctx, 0);
1052 1054 gen_load_gpr(t1, rt);
1053   - op_ldst_sh(t0, t1, ctx);
  1055 + op_ldst_sh(t1, t0, ctx);
1054 1056 opn = "sh";
1055 1057 break;
1056 1058 case OPC_LHU:
1057 1059 save_cpu_state(ctx, 0);
1058   - op_ldst_lhu(t0, ctx);
  1060 + op_ldst_lhu(t0, t0, ctx);
1059 1061 gen_store_gpr(t0, rt);
1060 1062 opn = "lhu";
1061 1063 break;
1062 1064 case OPC_LB:
1063 1065 save_cpu_state(ctx, 0);
1064   - op_ldst_lb(t0, ctx);
  1066 + op_ldst_lb(t0, t0, ctx);
1065 1067 gen_store_gpr(t0, rt);
1066 1068 opn = "lb";
1067 1069 break;
1068 1070 case OPC_SB:
1069 1071 save_cpu_state(ctx, 0);
1070 1072 gen_load_gpr(t1, rt);
1071   - op_ldst_sb(t0, t1, ctx);
  1073 + op_ldst_sb(t1, t0, ctx);
1072 1074 opn = "sb";
1073 1075 break;
1074 1076 case OPC_LBU:
1075 1077 save_cpu_state(ctx, 0);
1076   - op_ldst_lbu(t0, ctx);
  1078 + op_ldst_lbu(t0, t0, ctx);
1077 1079 gen_store_gpr(t0, rt);
1078 1080 opn = "lbu";
1079 1081 break;
1080 1082 case OPC_LWL:
1081 1083 save_cpu_state(ctx, 1);
1082 1084 gen_load_gpr(t1, rt);
1083   - gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
  1085 + gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
1084 1086 gen_store_gpr(t1, rt);
1085 1087 opn = "lwl";
1086 1088 break;
1087 1089 case OPC_SWL:
1088 1090 save_cpu_state(ctx, 1);
1089 1091 gen_load_gpr(t1, rt);
1090   - gen_helper_2i(swl, t0, t1, ctx->mem_idx);
  1092 + gen_helper_2i(swl, t1, t0, ctx->mem_idx);
1091 1093 opn = "swr";
1092 1094 break;
1093 1095 case OPC_LWR:
1094 1096 save_cpu_state(ctx, 1);
1095 1097 gen_load_gpr(t1, rt);
1096   - gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
  1098 + gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
1097 1099 gen_store_gpr(t1, rt);
1098 1100 opn = "lwr";
1099 1101 break;
1100 1102 case OPC_SWR:
1101 1103 save_cpu_state(ctx, 1);
1102 1104 gen_load_gpr(t1, rt);
1103   - gen_helper_2i(swr, t0, t1, ctx->mem_idx);
  1105 + gen_helper_2i(swr, t1, t0, ctx->mem_idx);
1104 1106 opn = "swr";
1105 1107 break;
1106 1108 case OPC_LL:
1107 1109 save_cpu_state(ctx, 0);
1108   - op_ldst_ll(t0, t1, ctx);
  1110 + op_ldst_ll(t0, t0, ctx);
1109 1111 gen_store_gpr(t0, rt);
1110 1112 opn = "ll";
1111 1113 break;
... ... @@ -1141,13 +1143,13 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
1141 1143 #if defined(TARGET_MIPS64)
1142 1144 case OPC_SCD:
1143 1145 save_cpu_state(ctx, 0);
1144   - op_ldst_scd(t0, t1, ctx);
  1146 + op_ldst_scd(t0, t1, t0, ctx);
1145 1147 opn = "scd";
1146 1148 break;
1147 1149 #endif
1148 1150 case OPC_SC:
1149 1151 save_cpu_state(ctx, 0);
1150   - op_ldst_sc(t0, t1, ctx);
  1152 + op_ldst_sc(t0, t1, t0, ctx);
1151 1153 opn = "sc";
1152 1154 break;
1153 1155 }
... ... @@ -1430,12 +1432,12 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
1430 1432 /* rotr is decoded as srl on non-R2 CPUs */
1431 1433 if (env->insn_flags & ISA_MIPS32R2) {
1432 1434 if (uimm != 0) {
1433   - TCGv_i32 r_tmp1 = tcg_temp_new_i32();
  1435 + TCGv_i32 t1 = tcg_temp_new_i32();
1434 1436  
1435   - tcg_gen_trunc_tl_i32(r_tmp1, t0);
1436   - tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm);
1437   - tcg_gen_ext_i32_tl(cpu_gpr[rt], r_tmp1);
1438   - tcg_temp_free_i32(r_tmp1);
  1437 + tcg_gen_trunc_tl_i32(t1, t0);
  1438 + tcg_gen_rotri_i32(t1, t1, uimm);
  1439 + tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
  1440 + tcg_temp_free_i32(t1);
1439 1441 }
1440 1442 opn = "rotr";
1441 1443 } else {
... ... @@ -2840,37 +2842,37 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
2840 2842  
2841 2843 #ifndef CONFIG_USER_ONLY
2842 2844 /* CP0 (MMU and control) */
2843   -static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
  2845 +static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
2844 2846 {
2845   - TCGv_i32 r_tmp = tcg_temp_new_i32();
  2847 + TCGv_i32 t0 = tcg_temp_new_i32();
2846 2848  
2847   - tcg_gen_ld_i32(r_tmp, cpu_env, off);
2848   - tcg_gen_ext_i32_tl(t, r_tmp);
2849   - tcg_temp_free_i32(r_tmp);
  2849 + tcg_gen_ld_i32(t0, cpu_env, off);
  2850 + tcg_gen_ext_i32_tl(arg, t0);
  2851 + tcg_temp_free_i32(t0);
2850 2852 }
2851 2853  
2852   -static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
  2854 +static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
2853 2855 {
2854   - tcg_gen_ld_tl(t, cpu_env, off);
2855   - tcg_gen_ext32s_tl(t, t);
  2856 + tcg_gen_ld_tl(arg, cpu_env, off);
  2857 + tcg_gen_ext32s_tl(arg, arg);
2856 2858 }
2857 2859  
2858   -static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
  2860 +static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
2859 2861 {
2860   - TCGv_i32 r_tmp = tcg_temp_new_i32();
  2862 + TCGv_i32 t0 = tcg_temp_new_i32();
2861 2863  
2862   - tcg_gen_trunc_tl_i32(r_tmp, t);
2863   - tcg_gen_st_i32(r_tmp, cpu_env, off);
2864   - tcg_temp_free_i32(r_tmp);
  2864 + tcg_gen_trunc_tl_i32(t0, arg);
  2865 + tcg_gen_st_i32(t0, cpu_env, off);
  2866 + tcg_temp_free_i32(t0);
2865 2867 }
2866 2868  
2867   -static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
  2869 +static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
2868 2870 {
2869   - tcg_gen_ext32s_tl(t, t);
2870   - tcg_gen_st_tl(t, cpu_env, off);
  2871 + tcg_gen_ext32s_tl(arg, arg);
  2872 + tcg_gen_st_tl(arg, cpu_env, off);
2871 2873 }
2872 2874  
2873   -static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
  2875 +static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
2874 2876 {
2875 2877 const char *rn = "invalid";
2876 2878  
... ... @@ -2881,22 +2883,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
2881 2883 case 0:
2882 2884 switch (sel) {
2883 2885 case 0:
2884   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
  2886 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
2885 2887 rn = "Index";
2886 2888 break;
2887 2889 case 1:
2888 2890 check_insn(env, ctx, ASE_MT);
2889   - gen_helper_mfc0_mvpcontrol(t0);
  2891 + gen_helper_mfc0_mvpcontrol(arg);
2890 2892 rn = "MVPControl";
2891 2893 break;
2892 2894 case 2:
2893 2895 check_insn(env, ctx, ASE_MT);
2894   - gen_helper_mfc0_mvpconf0(t0);
  2896 + gen_helper_mfc0_mvpconf0(arg);
2895 2897 rn = "MVPConf0";
2896 2898 break;
2897 2899 case 3:
2898 2900 check_insn(env, ctx, ASE_MT);
2899   - gen_helper_mfc0_mvpconf1(t0);
  2901 + gen_helper_mfc0_mvpconf1(arg);
2900 2902 rn = "MVPConf1";
2901 2903 break;
2902 2904 default:
... ... @@ -2906,42 +2908,42 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
2906 2908 case 1:
2907 2909 switch (sel) {
2908 2910 case 0:
2909   - gen_helper_mfc0_random(t0);
  2911 + gen_helper_mfc0_random(arg);
2910 2912 rn = "Random";
2911 2913 break;
2912 2914 case 1:
2913 2915 check_insn(env, ctx, ASE_MT);
2914   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
  2916 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
2915 2917 rn = "VPEControl";
2916 2918 break;
2917 2919 case 2:
2918 2920 check_insn(env, ctx, ASE_MT);
2919   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
  2921 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
2920 2922 rn = "VPEConf0";
2921 2923 break;
2922 2924 case 3:
2923 2925 check_insn(env, ctx, ASE_MT);
2924   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
  2926 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
2925 2927 rn = "VPEConf1";
2926 2928 break;
2927 2929 case 4:
2928 2930 check_insn(env, ctx, ASE_MT);
2929   - gen_mfc0_load64(t0, offsetof(CPUState, CP0_YQMask));
  2931 + gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
2930 2932 rn = "YQMask";
2931 2933 break;
2932 2934 case 5:
2933 2935 check_insn(env, ctx, ASE_MT);
2934   - gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPESchedule));
  2936 + gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
2935 2937 rn = "VPESchedule";
2936 2938 break;
2937 2939 case 6:
2938 2940 check_insn(env, ctx, ASE_MT);
2939   - gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPEScheFBack));
  2941 + gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
2940 2942 rn = "VPEScheFBack";
2941 2943 break;
2942 2944 case 7:
2943 2945 check_insn(env, ctx, ASE_MT);
2944   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
  2946 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
2945 2947 rn = "VPEOpt";
2946 2948 break;
2947 2949 default:
... ... @@ -2951,43 +2953,43 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
2951 2953 case 2:
2952 2954 switch (sel) {
2953 2955 case 0:
2954   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
2955   - tcg_gen_ext32s_tl(t0, t0);
  2956 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
  2957 + tcg_gen_ext32s_tl(arg, arg);
2956 2958 rn = "EntryLo0";
2957 2959 break;
2958 2960 case 1:
2959 2961 check_insn(env, ctx, ASE_MT);
2960   - gen_helper_mfc0_tcstatus(t0);
  2962 + gen_helper_mfc0_tcstatus(arg);
2961 2963 rn = "TCStatus";
2962 2964 break;
2963 2965 case 2:
2964 2966 check_insn(env, ctx, ASE_MT);
2965   - gen_helper_mfc0_tcbind(t0);
  2967 + gen_helper_mfc0_tcbind(arg);
2966 2968 rn = "TCBind";
2967 2969 break;
2968 2970 case 3:
2969 2971 check_insn(env, ctx, ASE_MT);
2970   - gen_helper_mfc0_tcrestart(t0);
  2972 + gen_helper_mfc0_tcrestart(arg);
2971 2973 rn = "TCRestart";
2972 2974 break;
2973 2975 case 4:
2974 2976 check_insn(env, ctx, ASE_MT);
2975   - gen_helper_mfc0_tchalt(t0);
  2977 + gen_helper_mfc0_tchalt(arg);
2976 2978 rn = "TCHalt";
2977 2979 break;
2978 2980 case 5:
2979 2981 check_insn(env, ctx, ASE_MT);
2980   - gen_helper_mfc0_tccontext(t0);
  2982 + gen_helper_mfc0_tccontext(arg);
2981 2983 rn = "TCContext";
2982 2984 break;
2983 2985 case 6:
2984 2986 check_insn(env, ctx, ASE_MT);
2985   - gen_helper_mfc0_tcschedule(t0);
  2987 + gen_helper_mfc0_tcschedule(arg);
2986 2988 rn = "TCSchedule";
2987 2989 break;
2988 2990 case 7:
2989 2991 check_insn(env, ctx, ASE_MT);
2990   - gen_helper_mfc0_tcschefback(t0);
  2992 + gen_helper_mfc0_tcschefback(arg);
2991 2993 rn = "TCScheFBack";
2992 2994 break;
2993 2995 default:
... ... @@ -2997,8 +2999,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
2997 2999 case 3:
2998 3000 switch (sel) {
2999 3001 case 0:
3000   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
3001   - tcg_gen_ext32s_tl(t0, t0);
  3002 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
  3003 + tcg_gen_ext32s_tl(arg, arg);
3002 3004 rn = "EntryLo1";
3003 3005 break;
3004 3006 default:
... ... @@ -3008,12 +3010,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3008 3010 case 4:
3009 3011 switch (sel) {
3010 3012 case 0:
3011   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
3012   - tcg_gen_ext32s_tl(t0, t0);
  3013 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
  3014 + tcg_gen_ext32s_tl(arg, arg);
3013 3015 rn = "Context";
3014 3016 break;
3015 3017 case 1:
3016   -// gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
  3018 +// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3017 3019 rn = "ContextConfig";
3018 3020 // break;
3019 3021 default:
... ... @@ -3023,12 +3025,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3023 3025 case 5:
3024 3026 switch (sel) {
3025 3027 case 0:
3026   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
  3028 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
3027 3029 rn = "PageMask";
3028 3030 break;
3029 3031 case 1:
3030 3032 check_insn(env, ctx, ISA_MIPS32R2);
3031   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
  3033 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
3032 3034 rn = "PageGrain";
3033 3035 break;
3034 3036 default:
... ... @@ -3038,32 +3040,32 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3038 3040 case 6:
3039 3041 switch (sel) {
3040 3042 case 0:
3041   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
  3043 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
3042 3044 rn = "Wired";
3043 3045 break;
3044 3046 case 1:
3045 3047 check_insn(env, ctx, ISA_MIPS32R2);
3046   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
  3048 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
3047 3049 rn = "SRSConf0";
3048 3050 break;
3049 3051 case 2:
3050 3052 check_insn(env, ctx, ISA_MIPS32R2);
3051   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
  3053 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
3052 3054 rn = "SRSConf1";
3053 3055 break;
3054 3056 case 3:
3055 3057 check_insn(env, ctx, ISA_MIPS32R2);
3056   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
  3058 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
3057 3059 rn = "SRSConf2";
3058 3060 break;
3059 3061 case 4:
3060 3062 check_insn(env, ctx, ISA_MIPS32R2);
3061   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
  3063 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
3062 3064 rn = "SRSConf3";
3063 3065 break;
3064 3066 case 5:
3065 3067 check_insn(env, ctx, ISA_MIPS32R2);
3066   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
  3068 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
3067 3069 rn = "SRSConf4";
3068 3070 break;
3069 3071 default:
... ... @@ -3074,7 +3076,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3074 3076 switch (sel) {
3075 3077 case 0:
3076 3078 check_insn(env, ctx, ISA_MIPS32R2);
3077   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
  3079 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
3078 3080 rn = "HWREna";
3079 3081 break;
3080 3082 default:
... ... @@ -3084,8 +3086,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3084 3086 case 8:
3085 3087 switch (sel) {
3086 3088 case 0:
3087   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
3088   - tcg_gen_ext32s_tl(t0, t0);
  3089 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
  3090 + tcg_gen_ext32s_tl(arg, arg);
3089 3091 rn = "BadVAddr";
3090 3092 break;
3091 3093 default:
... ... @@ -3098,7 +3100,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3098 3100 /* Mark as an IO operation because we read the time. */
3099 3101 if (use_icount)
3100 3102 gen_io_start();
3101   - gen_helper_mfc0_count(t0);
  3103 + gen_helper_mfc0_count(arg);
3102 3104 if (use_icount) {
3103 3105 gen_io_end();
3104 3106 ctx->bstate = BS_STOP;
... ... @@ -3113,8 +3115,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3113 3115 case 10:
3114 3116 switch (sel) {
3115 3117 case 0:
3116   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
3117   - tcg_gen_ext32s_tl(t0, t0);
  3118 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
  3119 + tcg_gen_ext32s_tl(arg, arg);
3118 3120 rn = "EntryHi";
3119 3121 break;
3120 3122 default:
... ... @@ -3124,7 +3126,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3124 3126 case 11:
3125 3127 switch (sel) {
3126 3128 case 0:
3127   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
  3129 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
3128 3130 rn = "Compare";
3129 3131 break;
3130 3132 /* 6,7 are implementation dependent */
... ... @@ -3135,22 +3137,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3135 3137 case 12:
3136 3138 switch (sel) {
3137 3139 case 0:
3138   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
  3140 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
3139 3141 rn = "Status";
3140 3142 break;
3141 3143 case 1:
3142 3144 check_insn(env, ctx, ISA_MIPS32R2);
3143   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
  3145 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
3144 3146 rn = "IntCtl";
3145 3147 break;
3146 3148 case 2:
3147 3149 check_insn(env, ctx, ISA_MIPS32R2);
3148   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
  3150 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
3149 3151 rn = "SRSCtl";
3150 3152 break;
3151 3153 case 3:
3152 3154 check_insn(env, ctx, ISA_MIPS32R2);
3153   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
  3155 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
3154 3156 rn = "SRSMap";
3155 3157 break;
3156 3158 default:
... ... @@ -3160,7 +3162,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3160 3162 case 13:
3161 3163 switch (sel) {
3162 3164 case 0:
3163   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
  3165 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
3164 3166 rn = "Cause";
3165 3167 break;
3166 3168 default:
... ... @@ -3170,8 +3172,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3170 3172 case 14:
3171 3173 switch (sel) {
3172 3174 case 0:
3173   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
3174   - tcg_gen_ext32s_tl(t0, t0);
  3175 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
  3176 + tcg_gen_ext32s_tl(arg, arg);
3175 3177 rn = "EPC";
3176 3178 break;
3177 3179 default:
... ... @@ -3181,12 +3183,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3181 3183 case 15:
3182 3184 switch (sel) {
3183 3185 case 0:
3184   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
  3186 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
3185 3187 rn = "PRid";
3186 3188 break;
3187 3189 case 1:
3188 3190 check_insn(env, ctx, ISA_MIPS32R2);
3189   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
  3191 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
3190 3192 rn = "EBase";
3191 3193 break;
3192 3194 default:
... ... @@ -3196,29 +3198,29 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3196 3198 case 16:
3197 3199 switch (sel) {
3198 3200 case 0:
3199   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
  3201 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
3200 3202 rn = "Config";
3201 3203 break;
3202 3204 case 1:
3203   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
  3205 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
3204 3206 rn = "Config1";
3205 3207 break;
3206 3208 case 2:
3207   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
  3209 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
3208 3210 rn = "Config2";
3209 3211 break;
3210 3212 case 3:
3211   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
  3213 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
3212 3214 rn = "Config3";
3213 3215 break;
3214 3216 /* 4,5 are reserved */
3215 3217 /* 6,7 are implementation dependent */
3216 3218 case 6:
3217   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
  3219 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
3218 3220 rn = "Config6";
3219 3221 break;
3220 3222 case 7:
3221   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
  3223 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
3222 3224 rn = "Config7";
3223 3225 break;
3224 3226 default:
... ... @@ -3228,7 +3230,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3228 3230 case 17:
3229 3231 switch (sel) {
3230 3232 case 0:
3231   - gen_helper_mfc0_lladdr(t0);
  3233 + gen_helper_mfc0_lladdr(arg);
3232 3234 rn = "LLAddr";
3233 3235 break;
3234 3236 default:
... ... @@ -3238,7 +3240,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3238 3240 case 18:
3239 3241 switch (sel) {
3240 3242 case 0 ... 7:
3241   - gen_helper_1i(mfc0_watchlo, t0, sel);
  3243 + gen_helper_1i(mfc0_watchlo, arg, sel);
3242 3244 rn = "WatchLo";
3243 3245 break;
3244 3246 default:
... ... @@ -3248,7 +3250,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3248 3250 case 19:
3249 3251 switch (sel) {
3250 3252 case 0 ...7:
3251   - gen_helper_1i(mfc0_watchhi, t0, sel);
  3253 + gen_helper_1i(mfc0_watchhi, arg, sel);
3252 3254 rn = "WatchHi";
3253 3255 break;
3254 3256 default:
... ... @@ -3260,8 +3262,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3260 3262 case 0:
3261 3263 #if defined(TARGET_MIPS64)
3262 3264 check_insn(env, ctx, ISA_MIPS3);
3263   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
3264   - tcg_gen_ext32s_tl(t0, t0);
  3265 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
  3266 + tcg_gen_ext32s_tl(arg, arg);
3265 3267 rn = "XContext";
3266 3268 break;
3267 3269 #endif
... ... @@ -3273,7 +3275,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3273 3275 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3274 3276 switch (sel) {
3275 3277 case 0:
3276   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
  3278 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
3277 3279 rn = "Framemask";
3278 3280 break;
3279 3281 default:
... ... @@ -3281,29 +3283,29 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3281 3283 }
3282 3284 break;
3283 3285 case 22:
3284   - tcg_gen_movi_tl(t0, 0); /* unimplemented */
  3286 + tcg_gen_movi_tl(arg, 0); /* unimplemented */
3285 3287 rn = "'Diagnostic"; /* implementation dependent */
3286 3288 break;
3287 3289 case 23:
3288 3290 switch (sel) {
3289 3291 case 0:
3290   - gen_helper_mfc0_debug(t0); /* EJTAG support */
  3292 + gen_helper_mfc0_debug(arg); /* EJTAG support */
3291 3293 rn = "Debug";
3292 3294 break;
3293 3295 case 1:
3294   -// gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
  3296 +// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3295 3297 rn = "TraceControl";
3296 3298 // break;
3297 3299 case 2:
3298   -// gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
  3300 +// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3299 3301 rn = "TraceControl2";
3300 3302 // break;
3301 3303 case 3:
3302   -// gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
  3304 +// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3303 3305 rn = "UserTraceData";
3304 3306 // break;
3305 3307 case 4:
3306   -// gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
  3308 +// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3307 3309 rn = "TraceBPC";
3308 3310 // break;
3309 3311 default:
... ... @@ -3314,8 +3316,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3314 3316 switch (sel) {
3315 3317 case 0:
3316 3318 /* EJTAG support */
3317   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
3318   - tcg_gen_ext32s_tl(t0, t0);
  3319 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
  3320 + tcg_gen_ext32s_tl(arg, arg);
3319 3321 rn = "DEPC";
3320 3322 break;
3321 3323 default:
... ... @@ -3325,35 +3327,35 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3325 3327 case 25:
3326 3328 switch (sel) {
3327 3329 case 0:
3328   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
  3330 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
3329 3331 rn = "Performance0";
3330 3332 break;
3331 3333 case 1:
3332   -// gen_helper_mfc0_performance1(t0);
  3334 +// gen_helper_mfc0_performance1(arg);
3333 3335 rn = "Performance1";
3334 3336 // break;
3335 3337 case 2:
3336   -// gen_helper_mfc0_performance2(t0);
  3338 +// gen_helper_mfc0_performance2(arg);
3337 3339 rn = "Performance2";
3338 3340 // break;
3339 3341 case 3:
3340   -// gen_helper_mfc0_performance3(t0);
  3342 +// gen_helper_mfc0_performance3(arg);
3341 3343 rn = "Performance3";
3342 3344 // break;
3343 3345 case 4:
3344   -// gen_helper_mfc0_performance4(t0);
  3346 +// gen_helper_mfc0_performance4(arg);
3345 3347 rn = "Performance4";
3346 3348 // break;
3347 3349 case 5:
3348   -// gen_helper_mfc0_performance5(t0);
  3350 +// gen_helper_mfc0_performance5(arg);
3349 3351 rn = "Performance5";
3350 3352 // break;
3351 3353 case 6:
3352   -// gen_helper_mfc0_performance6(t0);
  3354 +// gen_helper_mfc0_performance6(arg);
3353 3355 rn = "Performance6";
3354 3356 // break;
3355 3357 case 7:
3356   -// gen_helper_mfc0_performance7(t0);
  3358 +// gen_helper_mfc0_performance7(arg);
3357 3359 rn = "Performance7";
3358 3360 // break;
3359 3361 default:
... ... @@ -3361,13 +3363,13 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3361 3363 }
3362 3364 break;
3363 3365 case 26:
3364   - tcg_gen_movi_tl(t0, 0); /* unimplemented */
  3366 + tcg_gen_movi_tl(arg, 0); /* unimplemented */
3365 3367 rn = "ECC";
3366 3368 break;
3367 3369 case 27:
3368 3370 switch (sel) {
3369 3371 case 0 ... 3:
3370   - tcg_gen_movi_tl(t0, 0); /* unimplemented */
  3372 + tcg_gen_movi_tl(arg, 0); /* unimplemented */
3371 3373 rn = "CacheErr";
3372 3374 break;
3373 3375 default:
... ... @@ -3380,14 +3382,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3380 3382 case 2:
3381 3383 case 4:
3382 3384 case 6:
3383   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
  3385 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
3384 3386 rn = "TagLo";
3385 3387 break;
3386 3388 case 1:
3387 3389 case 3:
3388 3390 case 5:
3389 3391 case 7:
3390   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
  3392 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
3391 3393 rn = "DataLo";
3392 3394 break;
3393 3395 default:
... ... @@ -3400,14 +3402,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3400 3402 case 2:
3401 3403 case 4:
3402 3404 case 6:
3403   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
  3405 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
3404 3406 rn = "TagHi";
3405 3407 break;
3406 3408 case 1:
3407 3409 case 3:
3408 3410 case 5:
3409 3411 case 7:
3410   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
  3412 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
3411 3413 rn = "DataHi";
3412 3414 break;
3413 3415 default:
... ... @@ -3417,8 +3419,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3417 3419 case 30:
3418 3420 switch (sel) {
3419 3421 case 0:
3420   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
3421   - tcg_gen_ext32s_tl(t0, t0);
  3422 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
  3423 + tcg_gen_ext32s_tl(arg, arg);
3422 3424 rn = "ErrorEPC";
3423 3425 break;
3424 3426 default:
... ... @@ -3429,7 +3431,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3429 3431 switch (sel) {
3430 3432 case 0:
3431 3433 /* EJTAG support */
3432   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
  3434 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
3433 3435 rn = "DESAVE";
3434 3436 break;
3435 3437 default:
... ... @@ -3447,7 +3449,7 @@ die:
3447 3449 generate_exception(ctx, EXCP_RI);
3448 3450 }
3449 3451  
3450   -static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
  3452 +static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
3451 3453 {
3452 3454 const char *rn = "invalid";
3453 3455  
... ... @@ -3461,12 +3463,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3461 3463 case 0:
3462 3464 switch (sel) {
3463 3465 case 0:
3464   - gen_helper_mtc0_index(t0);
  3466 + gen_helper_mtc0_index(arg);
3465 3467 rn = "Index";
3466 3468 break;
3467 3469 case 1:
3468 3470 check_insn(env, ctx, ASE_MT);
3469   - gen_helper_mtc0_mvpcontrol(t0);
  3471 + gen_helper_mtc0_mvpcontrol(arg);
3470 3472 rn = "MVPControl";
3471 3473 break;
3472 3474 case 2:
... ... @@ -3491,37 +3493,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3491 3493 break;
3492 3494 case 1:
3493 3495 check_insn(env, ctx, ASE_MT);
3494   - gen_helper_mtc0_vpecontrol(t0);
  3496 + gen_helper_mtc0_vpecontrol(arg);
3495 3497 rn = "VPEControl";
3496 3498 break;
3497 3499 case 2:
3498 3500 check_insn(env, ctx, ASE_MT);
3499   - gen_helper_mtc0_vpeconf0(t0);
  3501 + gen_helper_mtc0_vpeconf0(arg);
3500 3502 rn = "VPEConf0";
3501 3503 break;
3502 3504 case 3:
3503 3505 check_insn(env, ctx, ASE_MT);
3504   - gen_helper_mtc0_vpeconf1(t0);
  3506 + gen_helper_mtc0_vpeconf1(arg);
3505 3507 rn = "VPEConf1";
3506 3508 break;
3507 3509 case 4:
3508 3510 check_insn(env, ctx, ASE_MT);
3509   - gen_helper_mtc0_yqmask(t0);
  3511 + gen_helper_mtc0_yqmask(arg);
3510 3512 rn = "YQMask";
3511 3513 break;
3512 3514 case 5:
3513 3515 check_insn(env, ctx, ASE_MT);
3514   - gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPESchedule));
  3516 + gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
3515 3517 rn = "VPESchedule";
3516 3518 break;
3517 3519 case 6:
3518 3520 check_insn(env, ctx, ASE_MT);
3519   - gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPEScheFBack));
  3521 + gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
3520 3522 rn = "VPEScheFBack";
3521 3523 break;
3522 3524 case 7:
3523 3525 check_insn(env, ctx, ASE_MT);
3524   - gen_helper_mtc0_vpeopt(t0);
  3526 + gen_helper_mtc0_vpeopt(arg);
3525 3527 rn = "VPEOpt";
3526 3528 break;
3527 3529 default:
... ... @@ -3531,42 +3533,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3531 3533 case 2:
3532 3534 switch (sel) {
3533 3535 case 0:
3534   - gen_helper_mtc0_entrylo0(t0);
  3536 + gen_helper_mtc0_entrylo0(arg);
3535 3537 rn = "EntryLo0";
3536 3538 break;
3537 3539 case 1:
3538 3540 check_insn(env, ctx, ASE_MT);
3539   - gen_helper_mtc0_tcstatus(t0);
  3541 + gen_helper_mtc0_tcstatus(arg);
3540 3542 rn = "TCStatus";
3541 3543 break;
3542 3544 case 2:
3543 3545 check_insn(env, ctx, ASE_MT);
3544   - gen_helper_mtc0_tcbind(t0);
  3546 + gen_helper_mtc0_tcbind(arg);
3545 3547 rn = "TCBind";
3546 3548 break;
3547 3549 case 3:
3548 3550 check_insn(env, ctx, ASE_MT);
3549   - gen_helper_mtc0_tcrestart(t0);
  3551 + gen_helper_mtc0_tcrestart(arg);
3550 3552 rn = "TCRestart";
3551 3553 break;
3552 3554 case 4:
3553 3555 check_insn(env, ctx, ASE_MT);
3554   - gen_helper_mtc0_tchalt(t0);
  3556 + gen_helper_mtc0_tchalt(arg);
3555 3557 rn = "TCHalt";
3556 3558 break;
3557 3559 case 5:
3558 3560 check_insn(env, ctx, ASE_MT);
3559   - gen_helper_mtc0_tccontext(t0);
  3561 + gen_helper_mtc0_tccontext(arg);
3560 3562 rn = "TCContext";
3561 3563 break;
3562 3564 case 6:
3563 3565 check_insn(env, ctx, ASE_MT);
3564   - gen_helper_mtc0_tcschedule(t0);
  3566 + gen_helper_mtc0_tcschedule(arg);
3565 3567 rn = "TCSchedule";
3566 3568 break;
3567 3569 case 7:
3568 3570 check_insn(env, ctx, ASE_MT);
3569   - gen_helper_mtc0_tcschefback(t0);
  3571 + gen_helper_mtc0_tcschefback(arg);
3570 3572 rn = "TCScheFBack";
3571 3573 break;
3572 3574 default:
... ... @@ -3576,7 +3578,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3576 3578 case 3:
3577 3579 switch (sel) {
3578 3580 case 0:
3579   - gen_helper_mtc0_entrylo1(t0);
  3581 + gen_helper_mtc0_entrylo1(arg);
3580 3582 rn = "EntryLo1";
3581 3583 break;
3582 3584 default:
... ... @@ -3586,11 +3588,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3586 3588 case 4:
3587 3589 switch (sel) {
3588 3590 case 0:
3589   - gen_helper_mtc0_context(t0);
  3591 + gen_helper_mtc0_context(arg);
3590 3592 rn = "Context";
3591 3593 break;
3592 3594 case 1:
3593   -// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
  3595 +// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3594 3596 rn = "ContextConfig";
3595 3597 // break;
3596 3598 default:
... ... @@ -3600,12 +3602,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3600 3602 case 5:
3601 3603 switch (sel) {
3602 3604 case 0:
3603   - gen_helper_mtc0_pagemask(t0);
  3605 + gen_helper_mtc0_pagemask(arg);
3604 3606 rn = "PageMask";
3605 3607 break;
3606 3608 case 1:
3607 3609 check_insn(env, ctx, ISA_MIPS32R2);
3608   - gen_helper_mtc0_pagegrain(t0);
  3610 + gen_helper_mtc0_pagegrain(arg);
3609 3611 rn = "PageGrain";
3610 3612 break;
3611 3613 default:
... ... @@ -3615,32 +3617,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3615 3617 case 6:
3616 3618 switch (sel) {
3617 3619 case 0:
3618   - gen_helper_mtc0_wired(t0);
  3620 + gen_helper_mtc0_wired(arg);
3619 3621 rn = "Wired";
3620 3622 break;
3621 3623 case 1:
3622 3624 check_insn(env, ctx, ISA_MIPS32R2);
3623   - gen_helper_mtc0_srsconf0(t0);
  3625 + gen_helper_mtc0_srsconf0(arg);
3624 3626 rn = "SRSConf0";
3625 3627 break;
3626 3628 case 2:
3627 3629 check_insn(env, ctx, ISA_MIPS32R2);
3628   - gen_helper_mtc0_srsconf1(t0);
  3630 + gen_helper_mtc0_srsconf1(arg);
3629 3631 rn = "SRSConf1";
3630 3632 break;
3631 3633 case 3:
3632 3634 check_insn(env, ctx, ISA_MIPS32R2);
3633   - gen_helper_mtc0_srsconf2(t0);
  3635 + gen_helper_mtc0_srsconf2(arg);
3634 3636 rn = "SRSConf2";
3635 3637 break;
3636 3638 case 4:
3637 3639 check_insn(env, ctx, ISA_MIPS32R2);
3638   - gen_helper_mtc0_srsconf3(t0);
  3640 + gen_helper_mtc0_srsconf3(arg);
3639 3641 rn = "SRSConf3";
3640 3642 break;
3641 3643 case 5:
3642 3644 check_insn(env, ctx, ISA_MIPS32R2);
3643   - gen_helper_mtc0_srsconf4(t0);
  3645 + gen_helper_mtc0_srsconf4(arg);
3644 3646 rn = "SRSConf4";
3645 3647 break;
3646 3648 default:
... ... @@ -3651,7 +3653,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3651 3653 switch (sel) {
3652 3654 case 0:
3653 3655 check_insn(env, ctx, ISA_MIPS32R2);
3654   - gen_helper_mtc0_hwrena(t0);
  3656 + gen_helper_mtc0_hwrena(arg);
3655 3657 rn = "HWREna";
3656 3658 break;
3657 3659 default:
... ... @@ -3665,7 +3667,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3665 3667 case 9:
3666 3668 switch (sel) {
3667 3669 case 0:
3668   - gen_helper_mtc0_count(t0);
  3670 + gen_helper_mtc0_count(arg);
3669 3671 rn = "Count";
3670 3672 break;
3671 3673 /* 6,7 are implementation dependent */
... ... @@ -3676,7 +3678,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3676 3678 case 10:
3677 3679 switch (sel) {
3678 3680 case 0:
3679   - gen_helper_mtc0_entryhi(t0);
  3681 + gen_helper_mtc0_entryhi(arg);
3680 3682 rn = "EntryHi";
3681 3683 break;
3682 3684 default:
... ... @@ -3686,7 +3688,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3686 3688 case 11:
3687 3689 switch (sel) {
3688 3690 case 0:
3689   - gen_helper_mtc0_compare(t0);
  3691 + gen_helper_mtc0_compare(arg);
3690 3692 rn = "Compare";
3691 3693 break;
3692 3694 /* 6,7 are implementation dependent */
... ... @@ -3698,7 +3700,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3698 3700 switch (sel) {
3699 3701 case 0:
3700 3702 save_cpu_state(ctx, 1);
3701   - gen_helper_mtc0_status(t0);
  3703 + gen_helper_mtc0_status(arg);
3702 3704 /* BS_STOP isn't good enough here, hflags may have changed. */
3703 3705 gen_save_pc(ctx->pc + 4);
3704 3706 ctx->bstate = BS_EXCP;
... ... @@ -3706,21 +3708,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3706 3708 break;
3707 3709 case 1:
3708 3710 check_insn(env, ctx, ISA_MIPS32R2);
3709   - gen_helper_mtc0_intctl(t0);
  3711 + gen_helper_mtc0_intctl(arg);
3710 3712 /* Stop translation as we may have switched the execution mode */
3711 3713 ctx->bstate = BS_STOP;
3712 3714 rn = "IntCtl";
3713 3715 break;
3714 3716 case 2:
3715 3717 check_insn(env, ctx, ISA_MIPS32R2);
3716   - gen_helper_mtc0_srsctl(t0);
  3718 + gen_helper_mtc0_srsctl(arg);
3717 3719 /* Stop translation as we may have switched the execution mode */
3718 3720 ctx->bstate = BS_STOP;
3719 3721 rn = "SRSCtl";
3720 3722 break;
3721 3723 case 3:
3722 3724 check_insn(env, ctx, ISA_MIPS32R2);
3723   - gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
  3725 + gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
3724 3726 /* Stop translation as we may have switched the execution mode */
3725 3727 ctx->bstate = BS_STOP;
3726 3728 rn = "SRSMap";
... ... @@ -3733,7 +3735,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3733 3735 switch (sel) {
3734 3736 case 0:
3735 3737 save_cpu_state(ctx, 1);
3736   - gen_helper_mtc0_cause(t0);
  3738 + gen_helper_mtc0_cause(arg);
3737 3739 rn = "Cause";
3738 3740 break;
3739 3741 default:
... ... @@ -3743,7 +3745,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3743 3745 case 14:
3744 3746 switch (sel) {
3745 3747 case 0:
3746   - gen_mtc0_store64(t0, offsetof(CPUState, CP0_EPC));
  3748 + gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
3747 3749 rn = "EPC";
3748 3750 break;
3749 3751 default:
... ... @@ -3758,7 +3760,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3758 3760 break;
3759 3761 case 1:
3760 3762 check_insn(env, ctx, ISA_MIPS32R2);
3761   - gen_helper_mtc0_ebase(t0);
  3763 + gen_helper_mtc0_ebase(arg);
3762 3764 rn = "EBase";
3763 3765 break;
3764 3766 default:
... ... @@ -3768,7 +3770,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3768 3770 case 16:
3769 3771 switch (sel) {
3770 3772 case 0:
3771   - gen_helper_mtc0_config0(t0);
  3773 + gen_helper_mtc0_config0(arg);
3772 3774 rn = "Config";
3773 3775 /* Stop translation as we may have switched the execution mode */
3774 3776 ctx->bstate = BS_STOP;
... ... @@ -3778,7 +3780,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3778 3780 rn = "Config1";
3779 3781 break;
3780 3782 case 2:
3781   - gen_helper_mtc0_config2(t0);
  3783 + gen_helper_mtc0_config2(arg);
3782 3784 rn = "Config2";
3783 3785 /* Stop translation as we may have switched the execution mode */
3784 3786 ctx->bstate = BS_STOP;
... ... @@ -3815,7 +3817,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3815 3817 case 18:
3816 3818 switch (sel) {
3817 3819 case 0 ... 7:
3818   - gen_helper_1i(mtc0_watchlo, t0, sel);
  3820 + gen_helper_1i(mtc0_watchlo, arg, sel);
3819 3821 rn = "WatchLo";
3820 3822 break;
3821 3823 default:
... ... @@ -3825,7 +3827,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3825 3827 case 19:
3826 3828 switch (sel) {
3827 3829 case 0 ... 7:
3828   - gen_helper_1i(mtc0_watchhi, t0, sel);
  3830 + gen_helper_1i(mtc0_watchhi, arg, sel);
3829 3831 rn = "WatchHi";
3830 3832 break;
3831 3833 default:
... ... @@ -3837,7 +3839,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3837 3839 case 0:
3838 3840 #if defined(TARGET_MIPS64)
3839 3841 check_insn(env, ctx, ISA_MIPS3);
3840   - gen_helper_mtc0_xcontext(t0);
  3842 + gen_helper_mtc0_xcontext(arg);
3841 3843 rn = "XContext";
3842 3844 break;
3843 3845 #endif
... ... @@ -3849,7 +3851,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3849 3851 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3850 3852 switch (sel) {
3851 3853 case 0:
3852   - gen_helper_mtc0_framemask(t0);
  3854 + gen_helper_mtc0_framemask(arg);
3853 3855 rn = "Framemask";
3854 3856 break;
3855 3857 default:
... ... @@ -3863,20 +3865,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3863 3865 case 23:
3864 3866 switch (sel) {
3865 3867 case 0:
3866   - gen_helper_mtc0_debug(t0); /* EJTAG support */
  3868 + gen_helper_mtc0_debug(arg); /* EJTAG support */
3867 3869 /* BS_STOP isn't good enough here, hflags may have changed. */
3868 3870 gen_save_pc(ctx->pc + 4);
3869 3871 ctx->bstate = BS_EXCP;
3870 3872 rn = "Debug";
3871 3873 break;
3872 3874 case 1:
3873   -// gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
  3875 +// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3874 3876 rn = "TraceControl";
3875 3877 /* Stop translation as we may have switched the execution mode */
3876 3878 ctx->bstate = BS_STOP;
3877 3879 // break;
3878 3880 case 2:
3879   -// gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
  3881 +// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3880 3882 rn = "TraceControl2";
3881 3883 /* Stop translation as we may have switched the execution mode */
3882 3884 ctx->bstate = BS_STOP;
... ... @@ -3884,13 +3886,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3884 3886 case 3:
3885 3887 /* Stop translation as we may have switched the execution mode */
3886 3888 ctx->bstate = BS_STOP;
3887   -// gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
  3889 +// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3888 3890 rn = "UserTraceData";
3889 3891 /* Stop translation as we may have switched the execution mode */
3890 3892 ctx->bstate = BS_STOP;
3891 3893 // break;
3892 3894 case 4:
3893   -// gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
  3895 +// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3894 3896 /* Stop translation as we may have switched the execution mode */
3895 3897 ctx->bstate = BS_STOP;
3896 3898 rn = "TraceBPC";
... ... @@ -3903,7 +3905,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3903 3905 switch (sel) {
3904 3906 case 0:
3905 3907 /* EJTAG support */
3906   - gen_mtc0_store64(t0, offsetof(CPUState, CP0_DEPC));
  3908 + gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
3907 3909 rn = "DEPC";
3908 3910 break;
3909 3911 default:
... ... @@ -3913,35 +3915,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3913 3915 case 25:
3914 3916 switch (sel) {
3915 3917 case 0:
3916   - gen_helper_mtc0_performance0(t0);
  3918 + gen_helper_mtc0_performance0(arg);
3917 3919 rn = "Performance0";
3918 3920 break;
3919 3921 case 1:
3920   -// gen_helper_mtc0_performance1(t0);
  3922 +// gen_helper_mtc0_performance1(arg);
3921 3923 rn = "Performance1";
3922 3924 // break;
3923 3925 case 2:
3924   -// gen_helper_mtc0_performance2(t0);
  3926 +// gen_helper_mtc0_performance2(arg);
3925 3927 rn = "Performance2";
3926 3928 // break;
3927 3929 case 3:
3928   -// gen_helper_mtc0_performance3(t0);
  3930 +// gen_helper_mtc0_performance3(arg);
3929 3931 rn = "Performance3";
3930 3932 // break;
3931 3933 case 4:
3932   -// gen_helper_mtc0_performance4(t0);
  3934 +// gen_helper_mtc0_performance4(arg);
3933 3935 rn = "Performance4";
3934 3936 // break;
3935 3937 case 5:
3936   -// gen_helper_mtc0_performance5(t0);
  3938 +// gen_helper_mtc0_performance5(arg);
3937 3939 rn = "Performance5";
3938 3940 // break;
3939 3941 case 6:
3940   -// gen_helper_mtc0_performance6(t0);
  3942 +// gen_helper_mtc0_performance6(arg);
3941 3943 rn = "Performance6";
3942 3944 // break;
3943 3945 case 7:
3944   -// gen_helper_mtc0_performance7(t0);
  3946 +// gen_helper_mtc0_performance7(arg);
3945 3947 rn = "Performance7";
3946 3948 // break;
3947 3949 default:
... ... @@ -3968,14 +3970,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3968 3970 case 2:
3969 3971 case 4:
3970 3972 case 6:
3971   - gen_helper_mtc0_taglo(t0);
  3973 + gen_helper_mtc0_taglo(arg);
3972 3974 rn = "TagLo";
3973 3975 break;
3974 3976 case 1:
3975 3977 case 3:
3976 3978 case 5:
3977 3979 case 7:
3978   - gen_helper_mtc0_datalo(t0);
  3980 + gen_helper_mtc0_datalo(arg);
3979 3981 rn = "DataLo";
3980 3982 break;
3981 3983 default:
... ... @@ -3988,14 +3990,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3988 3990 case 2:
3989 3991 case 4:
3990 3992 case 6:
3991   - gen_helper_mtc0_taghi(t0);
  3993 + gen_helper_mtc0_taghi(arg);
3992 3994 rn = "TagHi";
3993 3995 break;
3994 3996 case 1:
3995 3997 case 3:
3996 3998 case 5:
3997 3999 case 7:
3998   - gen_helper_mtc0_datahi(t0);
  4000 + gen_helper_mtc0_datahi(arg);
3999 4001 rn = "DataHi";
4000 4002 break;
4001 4003 default:
... ... @@ -4006,7 +4008,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
4006 4008 case 30:
4007 4009 switch (sel) {
4008 4010 case 0:
4009   - gen_mtc0_store64(t0, offsetof(CPUState, CP0_ErrorEPC));
  4011 + gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
4010 4012 rn = "ErrorEPC";
4011 4013 break;
4012 4014 default:
... ... @@ -4017,7 +4019,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
4017 4019 switch (sel) {
4018 4020 case 0:
4019 4021 /* EJTAG support */
4020   - gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
  4022 + gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
4021 4023 rn = "DESAVE";
4022 4024 break;
4023 4025 default:
... ... @@ -4043,7 +4045,7 @@ die:
4043 4045 }
4044 4046  
4045 4047 #if defined(TARGET_MIPS64)
4046   -static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
  4048 +static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4047 4049 {
4048 4050 const char *rn = "invalid";
4049 4051  
... ... @@ -4054,22 +4056,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4054 4056 case 0:
4055 4057 switch (sel) {
4056 4058 case 0:
4057   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
  4059 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
4058 4060 rn = "Index";
4059 4061 break;
4060 4062 case 1:
4061 4063 check_insn(env, ctx, ASE_MT);
4062   - gen_helper_mfc0_mvpcontrol(t0);
  4064 + gen_helper_mfc0_mvpcontrol(arg);
4063 4065 rn = "MVPControl";
4064 4066 break;
4065 4067 case 2:
4066 4068 check_insn(env, ctx, ASE_MT);
4067   - gen_helper_mfc0_mvpconf0(t0);
  4069 + gen_helper_mfc0_mvpconf0(arg);
4068 4070 rn = "MVPConf0";
4069 4071 break;
4070 4072 case 3:
4071 4073 check_insn(env, ctx, ASE_MT);
4072   - gen_helper_mfc0_mvpconf1(t0);
  4074 + gen_helper_mfc0_mvpconf1(arg);
4073 4075 rn = "MVPConf1";
4074 4076 break;
4075 4077 default:
... ... @@ -4079,42 +4081,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4079 4081 case 1:
4080 4082 switch (sel) {
4081 4083 case 0:
4082   - gen_helper_mfc0_random(t0);
  4084 + gen_helper_mfc0_random(arg);
4083 4085 rn = "Random";
4084 4086 break;
4085 4087 case 1:
4086 4088 check_insn(env, ctx, ASE_MT);
4087   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
  4089 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
4088 4090 rn = "VPEControl";
4089 4091 break;
4090 4092 case 2:
4091 4093 check_insn(env, ctx, ASE_MT);
4092   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
  4094 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
4093 4095 rn = "VPEConf0";
4094 4096 break;
4095 4097 case 3:
4096 4098 check_insn(env, ctx, ASE_MT);
4097   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
  4099 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
4098 4100 rn = "VPEConf1";
4099 4101 break;
4100 4102 case 4:
4101 4103 check_insn(env, ctx, ASE_MT);
4102   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_YQMask));
  4104 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
4103 4105 rn = "YQMask";
4104 4106 break;
4105 4107 case 5:
4106 4108 check_insn(env, ctx, ASE_MT);
4107   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
  4109 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4108 4110 rn = "VPESchedule";
4109 4111 break;
4110 4112 case 6:
4111 4113 check_insn(env, ctx, ASE_MT);
4112   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
  4114 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4113 4115 rn = "VPEScheFBack";
4114 4116 break;
4115 4117 case 7:
4116 4118 check_insn(env, ctx, ASE_MT);
4117   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
  4119 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
4118 4120 rn = "VPEOpt";
4119 4121 break;
4120 4122 default:
... ... @@ -4124,42 +4126,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4124 4126 case 2:
4125 4127 switch (sel) {
4126 4128 case 0:
4127   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
  4129 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4128 4130 rn = "EntryLo0";
4129 4131 break;
4130 4132 case 1:
4131 4133 check_insn(env, ctx, ASE_MT);
4132   - gen_helper_mfc0_tcstatus(t0);
  4134 + gen_helper_mfc0_tcstatus(arg);
4133 4135 rn = "TCStatus";
4134 4136 break;
4135 4137 case 2:
4136 4138 check_insn(env, ctx, ASE_MT);
4137   - gen_helper_mfc0_tcbind(t0);
  4139 + gen_helper_mfc0_tcbind(arg);
4138 4140 rn = "TCBind";
4139 4141 break;
4140 4142 case 3:
4141 4143 check_insn(env, ctx, ASE_MT);
4142   - gen_helper_dmfc0_tcrestart(t0);
  4144 + gen_helper_dmfc0_tcrestart(arg);
4143 4145 rn = "TCRestart";
4144 4146 break;
4145 4147 case 4:
4146 4148 check_insn(env, ctx, ASE_MT);
4147   - gen_helper_dmfc0_tchalt(t0);
  4149 + gen_helper_dmfc0_tchalt(arg);
4148 4150 rn = "TCHalt";
4149 4151 break;
4150 4152 case 5:
4151 4153 check_insn(env, ctx, ASE_MT);
4152   - gen_helper_dmfc0_tccontext(t0);
  4154 + gen_helper_dmfc0_tccontext(arg);
4153 4155 rn = "TCContext";
4154 4156 break;
4155 4157 case 6:
4156 4158 check_insn(env, ctx, ASE_MT);
4157   - gen_helper_dmfc0_tcschedule(t0);
  4159 + gen_helper_dmfc0_tcschedule(arg);
4158 4160 rn = "TCSchedule";
4159 4161 break;
4160 4162 case 7:
4161 4163 check_insn(env, ctx, ASE_MT);
4162   - gen_helper_dmfc0_tcschefback(t0);
  4164 + gen_helper_dmfc0_tcschefback(arg);
4163 4165 rn = "TCScheFBack";
4164 4166 break;
4165 4167 default:
... ... @@ -4169,7 +4171,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4169 4171 case 3:
4170 4172 switch (sel) {
4171 4173 case 0:
4172   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
  4174 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4173 4175 rn = "EntryLo1";
4174 4176 break;
4175 4177 default:
... ... @@ -4179,11 +4181,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4179 4181 case 4:
4180 4182 switch (sel) {
4181 4183 case 0:
4182   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
  4184 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
4183 4185 rn = "Context";
4184 4186 break;
4185 4187 case 1:
4186   -// gen_helper_dmfc0_contextconfig(t0); /* SmartMIPS ASE */
  4188 +// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4187 4189 rn = "ContextConfig";
4188 4190 // break;
4189 4191 default:
... ... @@ -4193,12 +4195,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4193 4195 case 5:
4194 4196 switch (sel) {
4195 4197 case 0:
4196   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
  4198 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
4197 4199 rn = "PageMask";
4198 4200 break;
4199 4201 case 1:
4200 4202 check_insn(env, ctx, ISA_MIPS32R2);
4201   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
  4203 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
4202 4204 rn = "PageGrain";
4203 4205 break;
4204 4206 default:
... ... @@ -4208,32 +4210,32 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4208 4210 case 6:
4209 4211 switch (sel) {
4210 4212 case 0:
4211   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
  4213 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
4212 4214 rn = "Wired";
4213 4215 break;
4214 4216 case 1:
4215 4217 check_insn(env, ctx, ISA_MIPS32R2);
4216   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
  4218 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
4217 4219 rn = "SRSConf0";
4218 4220 break;
4219 4221 case 2:
4220 4222 check_insn(env, ctx, ISA_MIPS32R2);
4221   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
  4223 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
4222 4224 rn = "SRSConf1";
4223 4225 break;
4224 4226 case 3:
4225 4227 check_insn(env, ctx, ISA_MIPS32R2);
4226   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
  4228 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
4227 4229 rn = "SRSConf2";
4228 4230 break;
4229 4231 case 4:
4230 4232 check_insn(env, ctx, ISA_MIPS32R2);
4231   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
  4233 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
4232 4234 rn = "SRSConf3";
4233 4235 break;
4234 4236 case 5:
4235 4237 check_insn(env, ctx, ISA_MIPS32R2);
4236   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
  4238 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
4237 4239 rn = "SRSConf4";
4238 4240 break;
4239 4241 default:
... ... @@ -4244,7 +4246,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4244 4246 switch (sel) {
4245 4247 case 0:
4246 4248 check_insn(env, ctx, ISA_MIPS32R2);
4247   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
  4249 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
4248 4250 rn = "HWREna";
4249 4251 break;
4250 4252 default:
... ... @@ -4254,7 +4256,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4254 4256 case 8:
4255 4257 switch (sel) {
4256 4258 case 0:
4257   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
  4259 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4258 4260 rn = "BadVAddr";
4259 4261 break;
4260 4262 default:
... ... @@ -4267,7 +4269,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4267 4269 /* Mark as an IO operation because we read the time. */
4268 4270 if (use_icount)
4269 4271 gen_io_start();
4270   - gen_helper_mfc0_count(t0);
  4272 + gen_helper_mfc0_count(arg);
4271 4273 if (use_icount) {
4272 4274 gen_io_end();
4273 4275 ctx->bstate = BS_STOP;
... ... @@ -4282,7 +4284,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4282 4284 case 10:
4283 4285 switch (sel) {
4284 4286 case 0:
4285   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
  4287 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
4286 4288 rn = "EntryHi";
4287 4289 break;
4288 4290 default:
... ... @@ -4292,7 +4294,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4292 4294 case 11:
4293 4295 switch (sel) {
4294 4296 case 0:
4295   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
  4297 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
4296 4298 rn = "Compare";
4297 4299 break;
4298 4300 /* 6,7 are implementation dependent */
... ... @@ -4303,22 +4305,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4303 4305 case 12:
4304 4306 switch (sel) {
4305 4307 case 0:
4306   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
  4308 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
4307 4309 rn = "Status";
4308 4310 break;
4309 4311 case 1:
4310 4312 check_insn(env, ctx, ISA_MIPS32R2);
4311   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
  4313 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
4312 4314 rn = "IntCtl";
4313 4315 break;
4314 4316 case 2:
4315 4317 check_insn(env, ctx, ISA_MIPS32R2);
4316   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
  4318 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
4317 4319 rn = "SRSCtl";
4318 4320 break;
4319 4321 case 3:
4320 4322 check_insn(env, ctx, ISA_MIPS32R2);
4321   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
  4323 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
4322 4324 rn = "SRSMap";
4323 4325 break;
4324 4326 default:
... ... @@ -4328,7 +4330,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4328 4330 case 13:
4329 4331 switch (sel) {
4330 4332 case 0:
4331   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
  4333 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
4332 4334 rn = "Cause";
4333 4335 break;
4334 4336 default:
... ... @@ -4338,7 +4340,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4338 4340 case 14:
4339 4341 switch (sel) {
4340 4342 case 0:
4341   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
  4343 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4342 4344 rn = "EPC";
4343 4345 break;
4344 4346 default:
... ... @@ -4348,12 +4350,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4348 4350 case 15:
4349 4351 switch (sel) {
4350 4352 case 0:
4351   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
  4353 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
4352 4354 rn = "PRid";
4353 4355 break;
4354 4356 case 1:
4355 4357 check_insn(env, ctx, ISA_MIPS32R2);
4356   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
  4358 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
4357 4359 rn = "EBase";
4358 4360 break;
4359 4361 default:
... ... @@ -4363,28 +4365,28 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4363 4365 case 16:
4364 4366 switch (sel) {
4365 4367 case 0:
4366   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
  4368 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
4367 4369 rn = "Config";
4368 4370 break;
4369 4371 case 1:
4370   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
  4372 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
4371 4373 rn = "Config1";
4372 4374 break;
4373 4375 case 2:
4374   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
  4376 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
4375 4377 rn = "Config2";
4376 4378 break;
4377 4379 case 3:
4378   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
  4380 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
4379 4381 rn = "Config3";
4380 4382 break;
4381 4383 /* 6,7 are implementation dependent */
4382 4384 case 6:
4383   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
  4385 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
4384 4386 rn = "Config6";
4385 4387 break;
4386 4388 case 7:
4387   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
  4389 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
4388 4390 rn = "Config7";
4389 4391 break;
4390 4392 default:
... ... @@ -4394,7 +4396,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4394 4396 case 17:
4395 4397 switch (sel) {
4396 4398 case 0:
4397   - gen_helper_dmfc0_lladdr(t0);
  4399 + gen_helper_dmfc0_lladdr(arg);
4398 4400 rn = "LLAddr";
4399 4401 break;
4400 4402 default:
... ... @@ -4404,7 +4406,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4404 4406 case 18:
4405 4407 switch (sel) {
4406 4408 case 0 ... 7:
4407   - gen_helper_1i(dmfc0_watchlo, t0, sel);
  4409 + gen_helper_1i(dmfc0_watchlo, arg, sel);
4408 4410 rn = "WatchLo";
4409 4411 break;
4410 4412 default:
... ... @@ -4414,7 +4416,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4414 4416 case 19:
4415 4417 switch (sel) {
4416 4418 case 0 ... 7:
4417   - gen_helper_1i(mfc0_watchhi, t0, sel);
  4419 + gen_helper_1i(mfc0_watchhi, arg, sel);
4418 4420 rn = "WatchHi";
4419 4421 break;
4420 4422 default:
... ... @@ -4425,7 +4427,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4425 4427 switch (sel) {
4426 4428 case 0:
4427 4429 check_insn(env, ctx, ISA_MIPS3);
4428   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
  4430 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
4429 4431 rn = "XContext";
4430 4432 break;
4431 4433 default:
... ... @@ -4436,7 +4438,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4436 4438 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4437 4439 switch (sel) {
4438 4440 case 0:
4439   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
  4441 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
4440 4442 rn = "Framemask";
4441 4443 break;
4442 4444 default:
... ... @@ -4444,29 +4446,29 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4444 4446 }
4445 4447 break;
4446 4448 case 22:
4447   - tcg_gen_movi_tl(t0, 0); /* unimplemented */
  4449 + tcg_gen_movi_tl(arg, 0); /* unimplemented */
4448 4450 rn = "'Diagnostic"; /* implementation dependent */
4449 4451 break;
4450 4452 case 23:
4451 4453 switch (sel) {
4452 4454 case 0:
4453   - gen_helper_mfc0_debug(t0); /* EJTAG support */
  4455 + gen_helper_mfc0_debug(arg); /* EJTAG support */
4454 4456 rn = "Debug";
4455 4457 break;
4456 4458 case 1:
4457   -// gen_helper_dmfc0_tracecontrol(t0); /* PDtrace support */
  4459 +// gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4458 4460 rn = "TraceControl";
4459 4461 // break;
4460 4462 case 2:
4461   -// gen_helper_dmfc0_tracecontrol2(t0); /* PDtrace support */
  4463 +// gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4462 4464 rn = "TraceControl2";
4463 4465 // break;
4464 4466 case 3:
4465   -// gen_helper_dmfc0_usertracedata(t0); /* PDtrace support */
  4467 +// gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4466 4468 rn = "UserTraceData";
4467 4469 // break;
4468 4470 case 4:
4469   -// gen_helper_dmfc0_tracebpc(t0); /* PDtrace support */
  4471 +// gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4470 4472 rn = "TraceBPC";
4471 4473 // break;
4472 4474 default:
... ... @@ -4477,7 +4479,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4477 4479 switch (sel) {
4478 4480 case 0:
4479 4481 /* EJTAG support */
4480   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
  4482 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
4481 4483 rn = "DEPC";
4482 4484 break;
4483 4485 default:
... ... @@ -4487,35 +4489,35 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4487 4489 case 25:
4488 4490 switch (sel) {
4489 4491 case 0:
4490   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
  4492 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
4491 4493 rn = "Performance0";
4492 4494 break;
4493 4495 case 1:
4494   -// gen_helper_dmfc0_performance1(t0);
  4496 +// gen_helper_dmfc0_performance1(arg);
4495 4497 rn = "Performance1";
4496 4498 // break;
4497 4499 case 2:
4498   -// gen_helper_dmfc0_performance2(t0);
  4500 +// gen_helper_dmfc0_performance2(arg);
4499 4501 rn = "Performance2";
4500 4502 // break;
4501 4503 case 3:
4502   -// gen_helper_dmfc0_performance3(t0);
  4504 +// gen_helper_dmfc0_performance3(arg);
4503 4505 rn = "Performance3";
4504 4506 // break;
4505 4507 case 4:
4506   -// gen_helper_dmfc0_performance4(t0);
  4508 +// gen_helper_dmfc0_performance4(arg);
4507 4509 rn = "Performance4";
4508 4510 // break;
4509 4511 case 5:
4510   -// gen_helper_dmfc0_performance5(t0);
  4512 +// gen_helper_dmfc0_performance5(arg);
4511 4513 rn = "Performance5";
4512 4514 // break;
4513 4515 case 6:
4514   -// gen_helper_dmfc0_performance6(t0);
  4516 +// gen_helper_dmfc0_performance6(arg);
4515 4517 rn = "Performance6";
4516 4518 // break;
4517 4519 case 7:
4518   -// gen_helper_dmfc0_performance7(t0);
  4520 +// gen_helper_dmfc0_performance7(arg);
4519 4521 rn = "Performance7";
4520 4522 // break;
4521 4523 default:
... ... @@ -4523,14 +4525,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4523 4525 }
4524 4526 break;
4525 4527 case 26:
4526   - tcg_gen_movi_tl(t0, 0); /* unimplemented */
  4528 + tcg_gen_movi_tl(arg, 0); /* unimplemented */
4527 4529 rn = "ECC";
4528 4530 break;
4529 4531 case 27:
4530 4532 switch (sel) {
4531 4533 /* ignored */
4532 4534 case 0 ... 3:
4533   - tcg_gen_movi_tl(t0, 0); /* unimplemented */
  4535 + tcg_gen_movi_tl(arg, 0); /* unimplemented */
4534 4536 rn = "CacheErr";
4535 4537 break;
4536 4538 default:
... ... @@ -4543,14 +4545,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4543 4545 case 2:
4544 4546 case 4:
4545 4547 case 6:
4546   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
  4548 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
4547 4549 rn = "TagLo";
4548 4550 break;
4549 4551 case 1:
4550 4552 case 3:
4551 4553 case 5:
4552 4554 case 7:
4553   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
  4555 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
4554 4556 rn = "DataLo";
4555 4557 break;
4556 4558 default:
... ... @@ -4563,14 +4565,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4563 4565 case 2:
4564 4566 case 4:
4565 4567 case 6:
4566   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
  4568 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
4567 4569 rn = "TagHi";
4568 4570 break;
4569 4571 case 1:
4570 4572 case 3:
4571 4573 case 5:
4572 4574 case 7:
4573   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
  4575 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
4574 4576 rn = "DataHi";
4575 4577 break;
4576 4578 default:
... ... @@ -4580,7 +4582,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4580 4582 case 30:
4581 4583 switch (sel) {
4582 4584 case 0:
4583   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
  4585 + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4584 4586 rn = "ErrorEPC";
4585 4587 break;
4586 4588 default:
... ... @@ -4591,7 +4593,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4591 4593 switch (sel) {
4592 4594 case 0:
4593 4595 /* EJTAG support */
4594   - gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
  4596 + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
4595 4597 rn = "DESAVE";
4596 4598 break;
4597 4599 default:
... ... @@ -4609,7 +4611,7 @@ die:
4609 4611 generate_exception(ctx, EXCP_RI);
4610 4612 }
4611 4613  
4612   -static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
  4614 +static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4613 4615 {
4614 4616 const char *rn = "invalid";
4615 4617  
... ... @@ -4623,12 +4625,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4623 4625 case 0:
4624 4626 switch (sel) {
4625 4627 case 0:
4626   - gen_helper_mtc0_index(t0);
  4628 + gen_helper_mtc0_index(arg);
4627 4629 rn = "Index";
4628 4630 break;
4629 4631 case 1:
4630 4632 check_insn(env, ctx, ASE_MT);
4631   - gen_helper_mtc0_mvpcontrol(t0);
  4633 + gen_helper_mtc0_mvpcontrol(arg);
4632 4634 rn = "MVPControl";
4633 4635 break;
4634 4636 case 2:
... ... @@ -4653,37 +4655,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4653 4655 break;
4654 4656 case 1:
4655 4657 check_insn(env, ctx, ASE_MT);
4656   - gen_helper_mtc0_vpecontrol(t0);
  4658 + gen_helper_mtc0_vpecontrol(arg);
4657 4659 rn = "VPEControl";
4658 4660 break;
4659 4661 case 2:
4660 4662 check_insn(env, ctx, ASE_MT);
4661   - gen_helper_mtc0_vpeconf0(t0);
  4663 + gen_helper_mtc0_vpeconf0(arg);
4662 4664 rn = "VPEConf0";
4663 4665 break;
4664 4666 case 3:
4665 4667 check_insn(env, ctx, ASE_MT);
4666   - gen_helper_mtc0_vpeconf1(t0);
  4668 + gen_helper_mtc0_vpeconf1(arg);
4667 4669 rn = "VPEConf1";
4668 4670 break;
4669 4671 case 4:
4670 4672 check_insn(env, ctx, ASE_MT);
4671   - gen_helper_mtc0_yqmask(t0);
  4673 + gen_helper_mtc0_yqmask(arg);
4672 4674 rn = "YQMask";
4673 4675 break;
4674 4676 case 5:
4675 4677 check_insn(env, ctx, ASE_MT);
4676   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
  4678 + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4677 4679 rn = "VPESchedule";
4678 4680 break;
4679 4681 case 6:
4680 4682 check_insn(env, ctx, ASE_MT);
4681   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
  4683 + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4682 4684 rn = "VPEScheFBack";
4683 4685 break;
4684 4686 case 7:
4685 4687 check_insn(env, ctx, ASE_MT);
4686   - gen_helper_mtc0_vpeopt(t0);
  4688 + gen_helper_mtc0_vpeopt(arg);
4687 4689 rn = "VPEOpt";
4688 4690 break;
4689 4691 default:
... ... @@ -4693,42 +4695,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4693 4695 case 2:
4694 4696 switch (sel) {
4695 4697 case 0:
4696   - gen_helper_mtc0_entrylo0(t0);
  4698 + gen_helper_mtc0_entrylo0(arg);
4697 4699 rn = "EntryLo0";
4698 4700 break;
4699 4701 case 1:
4700 4702 check_insn(env, ctx, ASE_MT);
4701   - gen_helper_mtc0_tcstatus(t0);
  4703 + gen_helper_mtc0_tcstatus(arg);
4702 4704 rn = "TCStatus";
4703 4705 break;
4704 4706 case 2:
4705 4707 check_insn(env, ctx, ASE_MT);
4706   - gen_helper_mtc0_tcbind(t0);
  4708 + gen_helper_mtc0_tcbind(arg);
4707 4709 rn = "TCBind";
4708 4710 break;
4709 4711 case 3:
4710 4712 check_insn(env, ctx, ASE_MT);
4711   - gen_helper_mtc0_tcrestart(t0);
  4713 + gen_helper_mtc0_tcrestart(arg);
4712 4714 rn = "TCRestart";
4713 4715 break;
4714 4716 case 4:
4715 4717 check_insn(env, ctx, ASE_MT);
4716   - gen_helper_mtc0_tchalt(t0);
  4718 + gen_helper_mtc0_tchalt(arg);
4717 4719 rn = "TCHalt";
4718 4720 break;
4719 4721 case 5:
4720 4722 check_insn(env, ctx, ASE_MT);
4721   - gen_helper_mtc0_tccontext(t0);
  4723 + gen_helper_mtc0_tccontext(arg);
4722 4724 rn = "TCContext";
4723 4725 break;
4724 4726 case 6:
4725 4727 check_insn(env, ctx, ASE_MT);
4726   - gen_helper_mtc0_tcschedule(t0);
  4728 + gen_helper_mtc0_tcschedule(arg);
4727 4729 rn = "TCSchedule";
4728 4730 break;
4729 4731 case 7:
4730 4732 check_insn(env, ctx, ASE_MT);
4731   - gen_helper_mtc0_tcschefback(t0);
  4733 + gen_helper_mtc0_tcschefback(arg);
4732 4734 rn = "TCScheFBack";
4733 4735 break;
4734 4736 default:
... ... @@ -4738,7 +4740,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4738 4740 case 3:
4739 4741 switch (sel) {
4740 4742 case 0:
4741   - gen_helper_mtc0_entrylo1(t0);
  4743 + gen_helper_mtc0_entrylo1(arg);
4742 4744 rn = "EntryLo1";
4743 4745 break;
4744 4746 default:
... ... @@ -4748,11 +4750,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4748 4750 case 4:
4749 4751 switch (sel) {
4750 4752 case 0:
4751   - gen_helper_mtc0_context(t0);
  4753 + gen_helper_mtc0_context(arg);
4752 4754 rn = "Context";
4753 4755 break;
4754 4756 case 1:
4755   -// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
  4757 +// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4756 4758 rn = "ContextConfig";
4757 4759 // break;
4758 4760 default:
... ... @@ -4762,12 +4764,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4762 4764 case 5:
4763 4765 switch (sel) {
4764 4766 case 0:
4765   - gen_helper_mtc0_pagemask(t0);
  4767 + gen_helper_mtc0_pagemask(arg);
4766 4768 rn = "PageMask";
4767 4769 break;
4768 4770 case 1:
4769 4771 check_insn(env, ctx, ISA_MIPS32R2);
4770   - gen_helper_mtc0_pagegrain(t0);
  4772 + gen_helper_mtc0_pagegrain(arg);
4771 4773 rn = "PageGrain";
4772 4774 break;
4773 4775 default:
... ... @@ -4777,32 +4779,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4777 4779 case 6:
4778 4780 switch (sel) {
4779 4781 case 0:
4780   - gen_helper_mtc0_wired(t0);
  4782 + gen_helper_mtc0_wired(arg);
4781 4783 rn = "Wired";
4782 4784 break;
4783 4785 case 1:
4784 4786 check_insn(env, ctx, ISA_MIPS32R2);
4785   - gen_helper_mtc0_srsconf0(t0);
  4787 + gen_helper_mtc0_srsconf0(arg);
4786 4788 rn = "SRSConf0";
4787 4789 break;
4788 4790 case 2:
4789 4791 check_insn(env, ctx, ISA_MIPS32R2);
4790   - gen_helper_mtc0_srsconf1(t0);
  4792 + gen_helper_mtc0_srsconf1(arg);
4791 4793 rn = "SRSConf1";
4792 4794 break;
4793 4795 case 3:
4794 4796 check_insn(env, ctx, ISA_MIPS32R2);
4795   - gen_helper_mtc0_srsconf2(t0);
  4797 + gen_helper_mtc0_srsconf2(arg);
4796 4798 rn = "SRSConf2";
4797 4799 break;
4798 4800 case 4:
4799 4801 check_insn(env, ctx, ISA_MIPS32R2);
4800   - gen_helper_mtc0_srsconf3(t0);
  4802 + gen_helper_mtc0_srsconf3(arg);
4801 4803 rn = "SRSConf3";
4802 4804 break;
4803 4805 case 5:
4804 4806 check_insn(env, ctx, ISA_MIPS32R2);
4805   - gen_helper_mtc0_srsconf4(t0);
  4807 + gen_helper_mtc0_srsconf4(arg);
4806 4808 rn = "SRSConf4";
4807 4809 break;
4808 4810 default:
... ... @@ -4813,7 +4815,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4813 4815 switch (sel) {
4814 4816 case 0:
4815 4817 check_insn(env, ctx, ISA_MIPS32R2);
4816   - gen_helper_mtc0_hwrena(t0);
  4818 + gen_helper_mtc0_hwrena(arg);
4817 4819 rn = "HWREna";
4818 4820 break;
4819 4821 default:
... ... @@ -4827,7 +4829,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4827 4829 case 9:
4828 4830 switch (sel) {
4829 4831 case 0:
4830   - gen_helper_mtc0_count(t0);
  4832 + gen_helper_mtc0_count(arg);
4831 4833 rn = "Count";
4832 4834 break;
4833 4835 /* 6,7 are implementation dependent */
... ... @@ -4840,7 +4842,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4840 4842 case 10:
4841 4843 switch (sel) {
4842 4844 case 0:
4843   - gen_helper_mtc0_entryhi(t0);
  4845 + gen_helper_mtc0_entryhi(arg);
4844 4846 rn = "EntryHi";
4845 4847 break;
4846 4848 default:
... ... @@ -4850,7 +4852,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4850 4852 case 11:
4851 4853 switch (sel) {
4852 4854 case 0:
4853   - gen_helper_mtc0_compare(t0);
  4855 + gen_helper_mtc0_compare(arg);
4854 4856 rn = "Compare";
4855 4857 break;
4856 4858 /* 6,7 are implementation dependent */
... ... @@ -4864,7 +4866,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4864 4866 switch (sel) {
4865 4867 case 0:
4866 4868 save_cpu_state(ctx, 1);
4867   - gen_helper_mtc0_status(t0);
  4869 + gen_helper_mtc0_status(arg);
4868 4870 /* BS_STOP isn't good enough here, hflags may have changed. */
4869 4871 gen_save_pc(ctx->pc + 4);
4870 4872 ctx->bstate = BS_EXCP;
... ... @@ -4872,21 +4874,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4872 4874 break;
4873 4875 case 1:
4874 4876 check_insn(env, ctx, ISA_MIPS32R2);
4875   - gen_helper_mtc0_intctl(t0);
  4877 + gen_helper_mtc0_intctl(arg);
4876 4878 /* Stop translation as we may have switched the execution mode */
4877 4879 ctx->bstate = BS_STOP;
4878 4880 rn = "IntCtl";
4879 4881 break;
4880 4882 case 2:
4881 4883 check_insn(env, ctx, ISA_MIPS32R2);
4882   - gen_helper_mtc0_srsctl(t0);
  4884 + gen_helper_mtc0_srsctl(arg);
4883 4885 /* Stop translation as we may have switched the execution mode */
4884 4886 ctx->bstate = BS_STOP;
4885 4887 rn = "SRSCtl";
4886 4888 break;
4887 4889 case 3:
4888 4890 check_insn(env, ctx, ISA_MIPS32R2);
4889   - gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
  4891 + gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
4890 4892 /* Stop translation as we may have switched the execution mode */
4891 4893 ctx->bstate = BS_STOP;
4892 4894 rn = "SRSMap";
... ... @@ -4899,7 +4901,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4899 4901 switch (sel) {
4900 4902 case 0:
4901 4903 save_cpu_state(ctx, 1);
4902   - gen_helper_mtc0_cause(t0);
  4904 + gen_helper_mtc0_cause(arg);
4903 4905 rn = "Cause";
4904 4906 break;
4905 4907 default:
... ... @@ -4909,7 +4911,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4909 4911 case 14:
4910 4912 switch (sel) {
4911 4913 case 0:
4912   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
  4914 + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4913 4915 rn = "EPC";
4914 4916 break;
4915 4917 default:
... ... @@ -4924,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4924 4926 break;
4925 4927 case 1:
4926 4928 check_insn(env, ctx, ISA_MIPS32R2);
4927   - gen_helper_mtc0_ebase(t0);
  4929 + gen_helper_mtc0_ebase(arg);
4928 4930 rn = "EBase";
4929 4931 break;
4930 4932 default:
... ... @@ -4934,7 +4936,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4934 4936 case 16:
4935 4937 switch (sel) {
4936 4938 case 0:
4937   - gen_helper_mtc0_config0(t0);
  4939 + gen_helper_mtc0_config0(arg);
4938 4940 rn = "Config";
4939 4941 /* Stop translation as we may have switched the execution mode */
4940 4942 ctx->bstate = BS_STOP;
... ... @@ -4944,7 +4946,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4944 4946 rn = "Config1";
4945 4947 break;
4946 4948 case 2:
4947   - gen_helper_mtc0_config2(t0);
  4949 + gen_helper_mtc0_config2(arg);
4948 4950 rn = "Config2";
4949 4951 /* Stop translation as we may have switched the execution mode */
4950 4952 ctx->bstate = BS_STOP;
... ... @@ -4972,7 +4974,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4972 4974 case 18:
4973 4975 switch (sel) {
4974 4976 case 0 ... 7:
4975   - gen_helper_1i(mtc0_watchlo, t0, sel);
  4977 + gen_helper_1i(mtc0_watchlo, arg, sel);
4976 4978 rn = "WatchLo";
4977 4979 break;
4978 4980 default:
... ... @@ -4982,7 +4984,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4982 4984 case 19:
4983 4985 switch (sel) {
4984 4986 case 0 ... 7:
4985   - gen_helper_1i(mtc0_watchhi, t0, sel);
  4987 + gen_helper_1i(mtc0_watchhi, arg, sel);
4986 4988 rn = "WatchHi";
4987 4989 break;
4988 4990 default:
... ... @@ -4993,7 +4995,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4993 4995 switch (sel) {
4994 4996 case 0:
4995 4997 check_insn(env, ctx, ISA_MIPS3);
4996   - gen_helper_mtc0_xcontext(t0);
  4998 + gen_helper_mtc0_xcontext(arg);
4997 4999 rn = "XContext";
4998 5000 break;
4999 5001 default:
... ... @@ -5004,7 +5006,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5004 5006 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5005 5007 switch (sel) {
5006 5008 case 0:
5007   - gen_helper_mtc0_framemask(t0);
  5009 + gen_helper_mtc0_framemask(arg);
5008 5010 rn = "Framemask";
5009 5011 break;
5010 5012 default:
... ... @@ -5018,32 +5020,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5018 5020 case 23:
5019 5021 switch (sel) {
5020 5022 case 0:
5021   - gen_helper_mtc0_debug(t0); /* EJTAG support */
  5023 + gen_helper_mtc0_debug(arg); /* EJTAG support */
5022 5024 /* BS_STOP isn't good enough here, hflags may have changed. */
5023 5025 gen_save_pc(ctx->pc + 4);
5024 5026 ctx->bstate = BS_EXCP;
5025 5027 rn = "Debug";
5026 5028 break;
5027 5029 case 1:
5028   -// gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
  5030 +// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5029 5031 /* Stop translation as we may have switched the execution mode */
5030 5032 ctx->bstate = BS_STOP;
5031 5033 rn = "TraceControl";
5032 5034 // break;
5033 5035 case 2:
5034   -// gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
  5036 +// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5035 5037 /* Stop translation as we may have switched the execution mode */
5036 5038 ctx->bstate = BS_STOP;
5037 5039 rn = "TraceControl2";
5038 5040 // break;
5039 5041 case 3:
5040   -// gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
  5042 +// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5041 5043 /* Stop translation as we may have switched the execution mode */
5042 5044 ctx->bstate = BS_STOP;
5043 5045 rn = "UserTraceData";
5044 5046 // break;
5045 5047 case 4:
5046   -// gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
  5048 +// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5047 5049 /* Stop translation as we may have switched the execution mode */
5048 5050 ctx->bstate = BS_STOP;
5049 5051 rn = "TraceBPC";
... ... @@ -5056,7 +5058,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5056 5058 switch (sel) {
5057 5059 case 0:
5058 5060 /* EJTAG support */
5059   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
  5061 + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
5060 5062 rn = "DEPC";
5061 5063 break;
5062 5064 default:
... ... @@ -5066,35 +5068,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5066 5068 case 25:
5067 5069 switch (sel) {
5068 5070 case 0:
5069   - gen_helper_mtc0_performance0(t0);
  5071 + gen_helper_mtc0_performance0(arg);
5070 5072 rn = "Performance0";
5071 5073 break;
5072 5074 case 1:
5073   -// gen_helper_mtc0_performance1(t0);
  5075 +// gen_helper_mtc0_performance1(arg);
5074 5076 rn = "Performance1";
5075 5077 // break;
5076 5078 case 2:
5077   -// gen_helper_mtc0_performance2(t0);
  5079 +// gen_helper_mtc0_performance2(arg);
5078 5080 rn = "Performance2";
5079 5081 // break;
5080 5082 case 3:
5081   -// gen_helper_mtc0_performance3(t0);
  5083 +// gen_helper_mtc0_performance3(arg);
5082 5084 rn = "Performance3";
5083 5085 // break;
5084 5086 case 4:
5085   -// gen_helper_mtc0_performance4(t0);
  5087 +// gen_helper_mtc0_performance4(arg);
5086 5088 rn = "Performance4";
5087 5089 // break;
5088 5090 case 5:
5089   -// gen_helper_mtc0_performance5(t0);
  5091 +// gen_helper_mtc0_performance5(arg);
5090 5092 rn = "Performance5";
5091 5093 // break;
5092 5094 case 6:
5093   -// gen_helper_mtc0_performance6(t0);
  5095 +// gen_helper_mtc0_performance6(arg);
5094 5096 rn = "Performance6";
5095 5097 // break;
5096 5098 case 7:
5097   -// gen_helper_mtc0_performance7(t0);
  5099 +// gen_helper_mtc0_performance7(arg);
5098 5100 rn = "Performance7";
5099 5101 // break;
5100 5102 default:
... ... @@ -5121,14 +5123,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5121 5123 case 2:
5122 5124 case 4:
5123 5125 case 6:
5124   - gen_helper_mtc0_taglo(t0);
  5126 + gen_helper_mtc0_taglo(arg);
5125 5127 rn = "TagLo";
5126 5128 break;
5127 5129 case 1:
5128 5130 case 3:
5129 5131 case 5:
5130 5132 case 7:
5131   - gen_helper_mtc0_datalo(t0);
  5133 + gen_helper_mtc0_datalo(arg);
5132 5134 rn = "DataLo";
5133 5135 break;
5134 5136 default:
... ... @@ -5141,14 +5143,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5141 5143 case 2:
5142 5144 case 4:
5143 5145 case 6:
5144   - gen_helper_mtc0_taghi(t0);
  5146 + gen_helper_mtc0_taghi(arg);
5145 5147 rn = "TagHi";
5146 5148 break;
5147 5149 case 1:
5148 5150 case 3:
5149 5151 case 5:
5150 5152 case 7:
5151   - gen_helper_mtc0_datahi(t0);
  5153 + gen_helper_mtc0_datahi(arg);
5152 5154 rn = "DataHi";
5153 5155 break;
5154 5156 default:
... ... @@ -5159,7 +5161,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5159 5161 case 30:
5160 5162 switch (sel) {
5161 5163 case 0:
5162   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
  5164 + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5163 5165 rn = "ErrorEPC";
5164 5166 break;
5165 5167 default:
... ... @@ -5170,7 +5172,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5170 5172 switch (sel) {
5171 5173 case 0:
5172 5174 /* EJTAG support */
5173   - gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
  5175 + gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
5174 5176 rn = "DESAVE";
5175 5177 break;
5176 5178 default:
... ...