Commit d95b2f8d365a3ef431111e9188d219de1f577a90
1 parent
ce819861
Switch to qemu_ram_alloc() for memory allocation in PXA255/270.
Pass correct RAM size to arm_load_kernel (currently unused) - thanks to BobOfDoom. Register the Xscale Internal Memory Storage. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2784 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
4 changed files
with
35 additions
and
19 deletions
hw/pxa.h
| @@ -57,7 +57,8 @@ | @@ -57,7 +57,8 @@ | ||
| 57 | # define PXA2XX_RX_RQ_SSP3 66 | 57 | # define PXA2XX_RX_RQ_SSP3 66 |
| 58 | # define PXA2XX_TX_RQ_SSP3 67 | 58 | # define PXA2XX_TX_RQ_SSP3 67 |
| 59 | 59 | ||
| 60 | -# define PXA2XX_RAM_BASE 0xa0000000 | 60 | +# define PXA2XX_SDRAM_BASE 0xa0000000 |
| 61 | +# define PXA2XX_INTERNAL_BASE 0x5c000000 | ||
| 61 | 62 | ||
| 62 | /* pxa2xx_pic.c */ | 63 | /* pxa2xx_pic.c */ |
| 63 | struct pxa2xx_pic_state_s; | 64 | struct pxa2xx_pic_state_s; |
| @@ -200,8 +201,9 @@ struct pxa2xx_i2s_s { | @@ -200,8 +201,9 @@ struct pxa2xx_i2s_s { | ||
| 200 | # define PA_FMT "0x%08lx" | 201 | # define PA_FMT "0x%08lx" |
| 201 | # define REG_FMT "0x%lx" | 202 | # define REG_FMT "0x%lx" |
| 202 | 203 | ||
| 203 | -struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision); | ||
| 204 | -struct pxa2xx_state_s *pxa255_init(DisplayState *ds); | 204 | +struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds, |
| 205 | + const char *revision); | ||
| 206 | +struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds); | ||
| 205 | 207 | ||
| 206 | void pxa2xx_reset(int line, int level, void *opaque); | 208 | void pxa2xx_reset(int line, int level, void *opaque); |
| 207 | 209 |
hw/pxa2xx.c
| @@ -1515,7 +1515,8 @@ void pxa2xx_reset(int line, int level, void *opaque) | @@ -1515,7 +1515,8 @@ void pxa2xx_reset(int line, int level, void *opaque) | ||
| 1515 | } | 1515 | } |
| 1516 | 1516 | ||
| 1517 | /* Initialise a PXA270 integrated chip (ARM based core). */ | 1517 | /* Initialise a PXA270 integrated chip (ARM based core). */ |
| 1518 | -struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision) | 1518 | +struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, |
| 1519 | + DisplayState *ds, const char *revision) | ||
| 1519 | { | 1520 | { |
| 1520 | struct pxa2xx_state_s *s; | 1521 | struct pxa2xx_state_s *s; |
| 1521 | struct pxa2xx_ssp_s *ssp; | 1522 | struct pxa2xx_ssp_s *ssp; |
| @@ -1530,6 +1531,12 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision) | @@ -1530,6 +1531,12 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision) | ||
| 1530 | s->env = cpu_init(); | 1531 | s->env = cpu_init(); |
| 1531 | cpu_arm_set_model(s->env, revision ?: "pxa270"); | 1532 | cpu_arm_set_model(s->env, revision ?: "pxa270"); |
| 1532 | 1533 | ||
| 1534 | + /* SDRAM & Internal Memory Storage */ | ||
| 1535 | + cpu_register_physical_memory(PXA2XX_SDRAM_BASE, | ||
| 1536 | + sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM); | ||
| 1537 | + cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, | ||
| 1538 | + 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM); | ||
| 1539 | + | ||
| 1533 | s->pic = pxa2xx_pic_init(0x40d00000, s->env); | 1540 | s->pic = pxa2xx_pic_init(0x40d00000, s->env); |
| 1534 | 1541 | ||
| 1535 | s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); | 1542 | s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); |
| @@ -1613,7 +1620,8 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision) | @@ -1613,7 +1620,8 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision) | ||
| 1613 | } | 1620 | } |
| 1614 | 1621 | ||
| 1615 | /* Initialise a PXA255 integrated chip (ARM based core). */ | 1622 | /* Initialise a PXA255 integrated chip (ARM based core). */ |
| 1616 | -struct pxa2xx_state_s *pxa255_init(DisplayState *ds) | 1623 | +struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, |
| 1624 | + DisplayState *ds) | ||
| 1617 | { | 1625 | { |
| 1618 | struct pxa2xx_state_s *s; | 1626 | struct pxa2xx_state_s *s; |
| 1619 | struct pxa2xx_ssp_s *ssp; | 1627 | struct pxa2xx_ssp_s *ssp; |
| @@ -1623,6 +1631,12 @@ struct pxa2xx_state_s *pxa255_init(DisplayState *ds) | @@ -1623,6 +1631,12 @@ struct pxa2xx_state_s *pxa255_init(DisplayState *ds) | ||
| 1623 | s->env = cpu_init(); | 1631 | s->env = cpu_init(); |
| 1624 | cpu_arm_set_model(s->env, "pxa255"); | 1632 | cpu_arm_set_model(s->env, "pxa255"); |
| 1625 | 1633 | ||
| 1634 | + /* SDRAM & Internal Memory Storage */ | ||
| 1635 | + cpu_register_physical_memory(PXA2XX_SDRAM_BASE, | ||
| 1636 | + sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM); | ||
| 1637 | + cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, | ||
| 1638 | + 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM); | ||
| 1639 | + | ||
| 1626 | s->pic = pxa2xx_pic_init(0x40d00000, s->env); | 1640 | s->pic = pxa2xx_pic_init(0x40d00000, s->env); |
| 1627 | 1641 | ||
| 1628 | s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); | 1642 | s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); |
hw/pxa2xx_lcd.c
| @@ -300,11 +300,11 @@ static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) | @@ -300,11 +300,11 @@ static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) | ||
| 300 | } else | 300 | } else |
| 301 | descptr = s->dma_ch[i].descriptor; | 301 | descptr = s->dma_ch[i].descriptor; |
| 302 | 302 | ||
| 303 | - if (!(descptr >= PXA2XX_RAM_BASE && descptr + | ||
| 304 | - sizeof(*desc[i]) <= PXA2XX_RAM_BASE + phys_ram_size)) | 303 | + if (!(descptr >= PXA2XX_SDRAM_BASE && descptr + |
| 304 | + sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size)) | ||
| 305 | continue; | 305 | continue; |
| 306 | 306 | ||
| 307 | - descptr -= PXA2XX_RAM_BASE; | 307 | + descptr -= PXA2XX_SDRAM_BASE; |
| 308 | desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr); | 308 | desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr); |
| 309 | s->dma_ch[i].descriptor = desc[i]->fdaddr; | 309 | s->dma_ch[i].descriptor = desc[i]->fdaddr; |
| 310 | s->dma_ch[i].source = desc[i]->fsaddr; | 310 | s->dma_ch[i].source = desc[i]->fsaddr; |
| @@ -855,12 +855,12 @@ static void pxa2xx_update_display(void *opaque) | @@ -855,12 +855,12 @@ static void pxa2xx_update_display(void *opaque) | ||
| 855 | continue; | 855 | continue; |
| 856 | } | 856 | } |
| 857 | fbptr = s->dma_ch[ch].source; | 857 | fbptr = s->dma_ch[ch].source; |
| 858 | - if (!(fbptr >= PXA2XX_RAM_BASE && | ||
| 859 | - fbptr <= PXA2XX_RAM_BASE + phys_ram_size)) { | 858 | + if (!(fbptr >= PXA2XX_SDRAM_BASE && |
| 859 | + fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) { | ||
| 860 | pxa2xx_dma_ber_set(s, ch); | 860 | pxa2xx_dma_ber_set(s, ch); |
| 861 | continue; | 861 | continue; |
| 862 | } | 862 | } |
| 863 | - fbptr -= PXA2XX_RAM_BASE; | 863 | + fbptr -= PXA2XX_SDRAM_BASE; |
| 864 | fb = phys_ram_base + fbptr; | 864 | fb = phys_ram_base + fbptr; |
| 865 | 865 | ||
| 866 | if (s->dma_ch[ch].command & LDCMD_PAL) { | 866 | if (s->dma_ch[ch].command & LDCMD_PAL) { |
hw/spitz.c
| @@ -1001,19 +1001,19 @@ static void spitz_common_init(int ram_size, int vga_ram_size, | @@ -1001,19 +1001,19 @@ static void spitz_common_init(int ram_size, int vga_ram_size, | ||
| 1001 | 1001 | ||
| 1002 | if (!cpu_model) | 1002 | if (!cpu_model) |
| 1003 | cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; | 1003 | cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; |
| 1004 | - cpu = pxa270_init(ds, cpu_model); | ||
| 1005 | 1004 | ||
| 1006 | - /* Setup memory */ | 1005 | + /* Setup CPU & memory */ |
| 1007 | if (ram_size < spitz_ram + spitz_rom) { | 1006 | if (ram_size < spitz_ram + spitz_rom) { |
| 1008 | fprintf(stderr, "This platform requires %i bytes of memory\n", | 1007 | fprintf(stderr, "This platform requires %i bytes of memory\n", |
| 1009 | spitz_ram + spitz_rom); | 1008 | spitz_ram + spitz_rom); |
| 1010 | exit(1); | 1009 | exit(1); |
| 1011 | } | 1010 | } |
| 1012 | - cpu_register_physical_memory(PXA2XX_RAM_BASE, spitz_ram, IO_MEM_RAM); | 1011 | + cpu = pxa270_init(spitz_ram, ds, cpu_model); |
| 1013 | 1012 | ||
| 1014 | sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); | 1013 | sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); |
| 1015 | 1014 | ||
| 1016 | - cpu_register_physical_memory(0, spitz_rom, spitz_ram | IO_MEM_ROM); | 1015 | + cpu_register_physical_memory(0, spitz_rom, |
| 1016 | + qemu_ram_alloc(spitz_rom) | IO_MEM_ROM); | ||
| 1017 | 1017 | ||
| 1018 | /* Setup peripherals */ | 1018 | /* Setup peripherals */ |
| 1019 | spitz_keyboard_register(cpu); | 1019 | spitz_keyboard_register(cpu); |
| @@ -1034,11 +1034,11 @@ static void spitz_common_init(int ram_size, int vga_ram_size, | @@ -1034,11 +1034,11 @@ static void spitz_common_init(int ram_size, int vga_ram_size, | ||
| 1034 | spitz_microdrive_attach(cpu); | 1034 | spitz_microdrive_attach(cpu); |
| 1035 | 1035 | ||
| 1036 | /* Setup initial (reset) machine state */ | 1036 | /* Setup initial (reset) machine state */ |
| 1037 | - cpu->env->regs[15] = PXA2XX_RAM_BASE; | 1037 | + cpu->env->regs[15] = PXA2XX_SDRAM_BASE; |
| 1038 | 1038 | ||
| 1039 | - arm_load_kernel(cpu->env, ram_size, kernel_filename, kernel_cmdline, | ||
| 1040 | - initrd_filename, arm_id, PXA2XX_RAM_BASE); | ||
| 1041 | - sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_RAM_BASE); | 1039 | + arm_load_kernel(cpu->env, spitz_ram, kernel_filename, kernel_cmdline, |
| 1040 | + initrd_filename, arm_id, PXA2XX_SDRAM_BASE); | ||
| 1041 | + sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE); | ||
| 1042 | } | 1042 | } |
| 1043 | 1043 | ||
| 1044 | static void spitz_init(int ram_size, int vga_ram_size, int boot_device, | 1044 | static void spitz_init(int ram_size, int vga_ram_size, int boot_device, |