Commit d8a5950a62ee91d7fd8ed5ba459992b55e9cb3b7
1 parent
b46a8906
Switch bc1any* instructions off if no MIPS-3D is implemented.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3426 c046a42c-6fe2-441c-8c8c-71466251a162
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target-mips/translate.c
| @@ -749,6 +749,12 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx) | @@ -749,6 +749,12 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx) | ||
| 749 | generate_exception(ctx, EXCP_RI); | 749 | generate_exception(ctx, EXCP_RI); |
| 750 | } | 750 | } |
| 751 | 751 | ||
| 752 | +static always_inline void check_cp1_3d(CPUState *env, DisasContext *ctx) | ||
| 753 | +{ | ||
| 754 | + if (unlikely(!(env->fpu->fcr0 & (1 << FCR0_3D)))) | ||
| 755 | + generate_exception(ctx, EXCP_RI); | ||
| 756 | +} | ||
| 757 | + | ||
| 752 | /* | 758 | /* |
| 753 | * Verify if floating point register is valid; an operation is not defined | 759 | * Verify if floating point register is valid; an operation is not defined |
| 754 | * if bit 0 of any register specification is set and the FR bit in the | 760 | * if bit 0 of any register specification is set and the FR bit in the |
| @@ -6328,9 +6334,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) | @@ -6328,9 +6334,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) | ||
| 6328 | gen_cp1(ctx, op1, rt, rd); | 6334 | gen_cp1(ctx, op1, rt, rd); |
| 6329 | break; | 6335 | break; |
| 6330 | #endif | 6336 | #endif |
| 6331 | - case OPC_BC1: | ||
| 6332 | case OPC_BC1ANY2: | 6337 | case OPC_BC1ANY2: |
| 6333 | case OPC_BC1ANY4: | 6338 | case OPC_BC1ANY4: |
| 6339 | + check_cp1_3d(env, ctx); | ||
| 6340 | + /* fall through */ | ||
| 6341 | + case OPC_BC1: | ||
| 6334 | gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), | 6342 | gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), |
| 6335 | (rt >> 2) & 0x7, imm << 2); | 6343 | (rt >> 2) & 0x7, imm << 2); |
| 6336 | return; | 6344 | return; |