gwj / at91sam9263 · Commits

Commit d88bbf9500bf44b1123a474dbd46bc1114993fa8

Authored by blueswir1
1 parent 97e7df27

Constification 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2916 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 7 additions and 7 deletions
sparc-dis.c
  View file @d88bbf9
@@ -2206,7 +2206,7 @@ sparc_decode_asi_v8 (int value) @@ -2206,7 +2206,7 @@ sparc_decode_asi_v8 (int value)
2206 2206
2207 /* Handle membar masks. */ 2207 /* Handle membar masks. */
2208 2208
2209 -static arg membar_table[] = 2209 +static const arg membar_table[] =
2210 { 2210 {
2211 { 0x40, "#Sync" }, 2211 { 0x40, "#Sync" },
2212 { 0x20, "#MemIssue" }, 2212 { 0x20, "#MemIssue" },
@@ -2238,7 +2238,7 @@ sparc_decode_membar (value) @@ -2238,7 +2238,7 @@ sparc_decode_membar (value)
2238 2238
2239 /* Handle prefetch args. */ 2239 /* Handle prefetch args. */
2240 2240
2241 -static arg prefetch_table[] = 2241 +static const arg prefetch_table[] =
2242 { 2242 {
2243 { 0, "#n_reads" }, 2243 { 0, "#n_reads" },
2244 { 1, "#one_read" }, 2244 { 1, "#one_read" },
@@ -2269,7 +2269,7 @@ sparc_decode_prefetch (value) @@ -2269,7 +2269,7 @@ sparc_decode_prefetch (value)
2269 2269
2270 /* Handle sparclet coprocessor registers. */ 2270 /* Handle sparclet coprocessor registers. */
2271 2271
2272 -static arg sparclet_cpreg_table[] = 2272 +static const arg sparclet_cpreg_table[] =
2273 { 2273 {
2274 { 0, "%ccsr" }, 2274 { 0, "%ccsr" },
2275 { 1, "%ccfr" }, 2275 { 1, "%ccfr" },
@@ -2320,7 +2320,7 @@ static const struct sparc_opcode **sorted_opcodes; @@ -2320,7 +2320,7 @@ static const struct sparc_opcode **sorted_opcodes;
2320 /* It is important that we only look at insn code bits as that is how the 2320 /* It is important that we only look at insn code bits as that is how the
2321 opcode table is hashed. OPCODE_BITS is a table of valid bits for each 2321 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
2322 of the main types (0,1,2,3). */ 2322 of the main types (0,1,2,3). */
2323 -static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; 2323 +static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
2324 #define HASH_INSN(INSN) \ 2324 #define HASH_INSN(INSN) \
2325 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) 2325 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
2326 struct opcode_hash { 2326 struct opcode_hash {
@@ -2340,7 +2340,7 @@ static int compute_arch_mask PARAMS ((unsigned long)); @@ -2340,7 +2340,7 @@ static int compute_arch_mask PARAMS ((unsigned long));
2340 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ 2340 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2341 >> ((8 * sizeof (int)) - bits) ) 2341 >> ((8 * sizeof (int)) - bits) )
2342 2342
2343 -static char *reg_names[] = 2343 +static const char * const reg_names[] =
2344 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 2344 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2345 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", 2345 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2346 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 2346 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
@@ -2361,7 +2361,7 @@ static char *reg_names[] = @@ -2361,7 +2361,7 @@ static char *reg_names[] =
2361 2361
2362 /* These are ordered according to there register number in 2362 /* These are ordered according to there register number in
2363 rdpr and wrpr insns. */ 2363 rdpr and wrpr insns. */
2364 -static char *v9_priv_reg_names[] = 2364 +static const char * const v9_priv_reg_names[] =
2365 { 2365 {
2366 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", 2366 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
2367 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", 2367 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
@@ -2371,7 +2371,7 @@ static char *v9_priv_reg_names[] = @@ -2371,7 +2371,7 @@ static char *v9_priv_reg_names[] =
2371 2371
2372 /* These are ordered according to there register number in 2372 /* These are ordered according to there register number in
2373 rd and wr insns (-16). */ 2373 rd and wr insns (-16). */
2374 -static char *v9a_asr_reg_names[] = 2374 +static const char * const v9a_asr_reg_names[] =
2375 { 2375 {
2376 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", 2376 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
2377 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr" 2377 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"