gwj / at91sam9263 · Commits

Commit d84763bc1771583e1731c6a351daa157e2d02125

Authored by blueswir1
1 parent c5d04e99

Convert rest of ops using float32 to TCG, remove FT0 and FT1 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 39 additions and 64 deletions
target-sparc/cpu.h
  View file @d84763b
... ... @@ -303,7 +303,6 @@ typedef struct CPUSPARCState {
303 303 uint64_t prom_addr;
304 304 #endif
305 305 /* temporary float registers */
306   - float32 ft0, ft1;
307 306 float64 dt0, dt1;
308 307 float128 qt0, qt1;
309 308 float_status fp_status;
... ...
target-sparc/exec.h
  View file @d84763b
... ... @@ -5,8 +5,6 @@
5 5  
6 6 register struct CPUSPARCState *env asm(AREG0);
7 7  
8   -#define FT0 (env->ft0)
9   -#define FT1 (env->ft1)
10 8 #define DT0 (env->dt0)
11 9 #define DT1 (env->dt1)
12 10 #define QT0 (env->qt0)
... ...
target-sparc/helper.h
  View file @d84763b
... ... @@ -93,10 +93,6 @@ DEF_HELPER(void, helper_fcmpeq_fcc3, (void))
93 93 #endif
94 94 DEF_HELPER(void, raise_exception, (int tt))
95 95 #define F_HELPER_0_0(name) DEF_HELPER(void, helper_f ## name, (void))
96   -#define F_HELPER_SDQ_0_0(name) \
97   - F_HELPER_0_0(name ## s); \
98   - F_HELPER_0_0(name ## d); \
99   - F_HELPER_0_0(name ## q)
100 96 #define F_HELPER_DQ_0_0(name) \
101 97 F_HELPER_0_0(name ## d); \
102 98 F_HELPER_0_0(name ## q)
... ... @@ -111,11 +107,11 @@ DEF_HELPER(float32, helper_fsubs, (float32 src1, float32 src2))
111 107 DEF_HELPER(float32, helper_fmuls, (float32 src1, float32 src2))
112 108 DEF_HELPER(float32, helper_fdivs, (float32 src1, float32 src2))
113 109  
114   -F_HELPER_0_0(smuld);
  110 +DEF_HELPER(void, helper_fsmuld, (float32 src1, float32 src2))
115 111 F_HELPER_0_0(dmulq);
116 112  
117 113 DEF_HELPER(float32, helper_fnegs, (float32 src))
118   -F_HELPER_0_0(itod);
  114 +DEF_HELPER(void, helper_fitod, (int32_t src))
119 115 DEF_HELPER(void, helper_fitoq, (int32_t src))
120 116  
121 117 DEF_HELPER(float32, helper_fitos, (int32_t src))
... ... @@ -123,19 +119,20 @@ DEF_HELPER(float32, helper_fitos, (int32_t src))
123 119 #ifdef TARGET_SPARC64
124 120 DEF_HELPER(void, helper_fnegd, (void))
125 121 DEF_HELPER(void, helper_fnegq, (void))
126   -F_HELPER_SDQ_0_0(xto);
  122 +DEF_HELPER(uint32_t, helper_fxtos, (void))
  123 +F_HELPER_DQ_0_0(xto);
127 124 #endif
128   -F_HELPER_0_0(dtos);
129   -F_HELPER_0_0(stod);
  125 +DEF_HELPER(float32, helper_fdtos, (void))
  126 +DEF_HELPER(void, helper_fstod, (float32 src))
130 127 DEF_HELPER(float32, helper_fqtos, (void))
131 128 DEF_HELPER(void, helper_fstoq, (float32 src))
132 129 F_HELPER_0_0(qtod);
133 130 F_HELPER_0_0(dtoq);
134 131 DEF_HELPER(int32_t, helper_fstoi, (float32 src))
135   -F_HELPER_0_0(dtoi);
  132 +DEF_HELPER(int32_t, helper_fdtoi, (void))
136 133 DEF_HELPER(int32_t, helper_fqtoi, (void))
137 134 #ifdef TARGET_SPARC64
138   -F_HELPER_0_0(stox);
  135 +DEF_HELPER(void, helper_fstox, (uint32_t src))
139 136 F_HELPER_0_0(dtox);
140 137 F_HELPER_0_0(qtox);
141 138 F_HELPER_0_0(aligndata);
... ...
target-sparc/op_helper.c
  View file @d84763b
... ... @@ -106,10 +106,10 @@ F_BINOP(mul);
106 106 F_BINOP(div);
107 107 #undef F_BINOP
108 108  
109   -void helper_fsmuld(void)
  109 +void helper_fsmuld(float32 src1, float32 src2)
110 110 {
111   - DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
112   - float32_to_float64(FT1, &env->fp_status),
  111 + DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
  112 + float32_to_float64(src2, &env->fp_status),
113 113 &env->fp_status);
114 114 }
115 115  
... ... @@ -143,9 +143,9 @@ float32 helper_fitos(int32_t src)
143 143 return int32_to_float32(src, &env->fp_status);
144 144 }
145 145  
146   -F_HELPER(ito, d)
  146 +void helper_fitod(int32_t src)
147 147 {
148   - DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
  148 + DT0 = int32_to_float64(src, &env->fp_status);
149 149 }
150 150  
151 151 void helper_fitoq(int32_t src)
... ... @@ -154,9 +154,9 @@ void helper_fitoq(int32_t src)
154 154 }
155 155  
156 156 #ifdef TARGET_SPARC64
157   -F_HELPER(xto, s)
  157 +float32 helper_fxtos(void)
158 158 {
159   - FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
  159 + return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
160 160 }
161 161  
162 162 F_HELPER(xto, d)
... ... @@ -172,14 +172,14 @@ F_HELPER(xto, q)
172 172 #undef F_HELPER
173 173  
174 174 /* floating point conversion */
175   -void helper_fdtos(void)
  175 +float32 helper_fdtos(void)
176 176 {
177   - FT0 = float64_to_float32(DT1, &env->fp_status);
  177 + return float64_to_float32(DT1, &env->fp_status);
178 178 }
179 179  
180   -void helper_fstod(void)
  180 +void helper_fstod(float32 src)
181 181 {
182   - DT0 = float32_to_float64(FT1, &env->fp_status);
  182 + DT0 = float32_to_float64(src, &env->fp_status);
183 183 }
184 184  
185 185 float32 helper_fqtos(void)
... ... @@ -208,9 +208,9 @@ int32_t helper_fstoi(float32 src)
208 208 return float32_to_int32_round_to_zero(src, &env->fp_status);
209 209 }
210 210  
211   -void helper_fdtoi(void)
  211 +int32_t helper_fdtoi(void)
212 212 {
213   - *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
  213 + return float64_to_int32_round_to_zero(DT1, &env->fp_status);
214 214 }
215 215  
216 216 int32_t helper_fqtoi(void)
... ... @@ -219,9 +219,9 @@ int32_t helper_fqtoi(void)
219 219 }
220 220  
221 221 #ifdef TARGET_SPARC64
222   -void helper_fstox(void)
  222 +void helper_fstox(float32 src)
223 223 {
224   - *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
  224 + *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
225 225 }
226 226  
227 227 void helper_fdtox(void)
... ...
target-sparc/translate.c
  View file @d84763b
... ... @@ -102,21 +102,6 @@ static int sign_extend(int x, int len)
102 102 #define IS_IMM (insn & (1<<13))
103 103  
104 104 /* floating point registers moves */
105   -static void gen_op_load_fpr_FT0(unsigned int src)
106   -{
107   - tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, ft0));
108   -}
109   -
110   -static void gen_op_load_fpr_FT1(unsigned int src)
111   -{
112   - tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, ft1));
113   -}
114   -
115   -static void gen_op_store_FT0_fpr(unsigned int dst)
116   -{
117   - tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, ft0));
118   -}
119   -
120 105 static void gen_op_load_fpr_DT0(unsigned int src)
121 106 {
122 107 tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
... ... @@ -2475,12 +2460,11 @@ static void disas_sparc_insn(DisasContext * dc)
2475 2460 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2476 2461 gen_op_store_QT0_fpr(QFPREG(rd));
2477 2462 break;
2478   - case 0x69:
  2463 + case 0x69: /* fsmuld */
2479 2464 CHECK_FPU_FEATURE(dc, FSMULD);
2480   - gen_op_load_fpr_FT0(rs1);
2481   - gen_op_load_fpr_FT1(rs2);
2482 2465 gen_clear_float_exceptions();
2483   - tcg_gen_helper_0_0(helper_fsmuld);
  2466 + tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1],
  2467 + cpu_fpr[rs2]);
2484 2468 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2485 2469 gen_op_store_DT0_fpr(DFPREG(rd));
2486 2470 break;
... ... @@ -2500,12 +2484,12 @@ static void disas_sparc_insn(DisasContext * dc)
2500 2484 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2501 2485 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2502 2486 break;
2503   - case 0xc6:
  2487 + case 0xc6: /* fdtos */
2504 2488 gen_op_load_fpr_DT1(DFPREG(rs2));
2505 2489 gen_clear_float_exceptions();
2506   - tcg_gen_helper_0_0(helper_fdtos);
  2490 + tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32);
2507 2491 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2508   - gen_op_store_FT0_fpr(rd);
  2492 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2509 2493 break;
2510 2494 case 0xc7: /* fqtos */
2511 2495 CHECK_FPU_FEATURE(dc, FLOAT128);
... ... @@ -2515,14 +2499,12 @@ static void disas_sparc_insn(DisasContext * dc)
2515 2499 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2516 2500 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2517 2501 break;
2518   - case 0xc8:
2519   - gen_op_load_fpr_FT1(rs2);
2520   - tcg_gen_helper_0_0(helper_fitod);
  2502 + case 0xc8: /* fitod */
  2503 + tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]);
2521 2504 gen_op_store_DT0_fpr(DFPREG(rd));
2522 2505 break;
2523   - case 0xc9:
2524   - gen_op_load_fpr_FT1(rs2);
2525   - tcg_gen_helper_0_0(helper_fstod);
  2506 + case 0xc9: /* fstod */
  2507 + tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]);
2526 2508 gen_op_store_DT0_fpr(DFPREG(rd));
2527 2509 break;
2528 2510 case 0xcb: /* fqtod */
... ... @@ -2556,12 +2538,12 @@ static void disas_sparc_insn(DisasContext * dc)
2556 2538 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2557 2539 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2558 2540 break;
2559   - case 0xd2:
  2541 + case 0xd2: /* fdtoi */
2560 2542 gen_op_load_fpr_DT1(DFPREG(rs2));
2561 2543 gen_clear_float_exceptions();
2562   - tcg_gen_helper_0_0(helper_fdtoi);
  2544 + tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32);
2563 2545 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2564   - gen_op_store_FT0_fpr(rd);
  2546 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2565 2547 break;
2566 2548 case 0xd3: /* fqtoi */
2567 2549 CHECK_FPU_FEATURE(dc, FLOAT128);
... ... @@ -2612,9 +2594,8 @@ static void disas_sparc_insn(DisasContext * dc)
2612 2594 gen_op_store_QT0_fpr(QFPREG(rd));
2613 2595 break;
2614 2596 case 0x81: /* V9 fstox */
2615   - gen_op_load_fpr_FT1(rs2);
2616 2597 gen_clear_float_exceptions();
2617   - tcg_gen_helper_0_0(helper_fstox);
  2598 + tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]);
2618 2599 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2619 2600 gen_op_store_DT0_fpr(DFPREG(rd));
2620 2601 break;
... ... @@ -2636,9 +2617,9 @@ static void disas_sparc_insn(DisasContext * dc)
2636 2617 case 0x84: /* V9 fxtos */
2637 2618 gen_op_load_fpr_DT1(DFPREG(rs2));
2638 2619 gen_clear_float_exceptions();
2639   - tcg_gen_helper_0_0(helper_fxtos);
  2620 + tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32);
2640 2621 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2641   - gen_op_store_FT0_fpr(rd);
  2622 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2642 2623 break;
2643 2624 case 0x88: /* V9 fxtod */
2644 2625 gen_op_load_fpr_DT1(DFPREG(rs2));
... ...