gwj / at91sam9263 · Commits

Commit d785e6be4d85d08ae34f7942da139493be28ec6b

Authored by bellard
1 parent 5e83e8e3

x86_64 support 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1320 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 27 additions and 29 deletions
dyngen-exec.h
  View file @d785e6b
@@ -221,6 +221,7 @@ extern int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3; @@ -221,6 +221,7 @@ extern int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
221 #endif 221 #endif
222 #ifdef __x86_64__ 222 #ifdef __x86_64__
223 #define EXIT_TB() asm volatile ("ret") 223 #define EXIT_TB() asm volatile ("ret")
  224 +#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n)
224 #endif 225 #endif
225 #ifdef __powerpc__ 226 #ifdef __powerpc__
226 #define EXIT_TB() asm volatile ("blr") 227 #define EXIT_TB() asm volatile ("blr")
target-i386/exec.h
  View file @d785e6b
@@ -21,77 +21,74 @@ @@ -21,77 +21,74 @@
21 #include "dyngen-exec.h" 21 #include "dyngen-exec.h"
22 22
23 /* XXX: factorize this mess */ 23 /* XXX: factorize this mess */
24 -#if defined(__alpha__) || defined (__ia64__) || defined(__x86_64__)  
25 -#define HOST_LONG_BITS 64  
26 -#else  
27 -#define HOST_LONG_BITS 32  
28 -#endif  
29 -  
30 #ifdef TARGET_X86_64 24 #ifdef TARGET_X86_64
31 #define TARGET_LONG_BITS 64 25 #define TARGET_LONG_BITS 64
32 #else 26 #else
33 #define TARGET_LONG_BITS 32 27 #define TARGET_LONG_BITS 32
34 #endif 28 #endif
35 29
  30 +#include "cpu-defs.h"
  31 +
36 /* at least 4 register variables are defined */ 32 /* at least 4 register variables are defined */
37 register struct CPUX86State *env asm(AREG0); 33 register struct CPUX86State *env asm(AREG0);
38 34
39 -/* XXX: use 64 bit regs if HOST_LONG_BITS == 64 */  
40 -#if TARGET_LONG_BITS == 32 35 +#if TARGET_LONG_BITS > HOST_LONG_BITS
  36 +
  37 +/* no registers can be used */
  38 +#define T0 (env->t0)
  39 +#define T1 (env->t1)
  40 +#define T2 (env->t2)
41 41
42 -register uint32_t T0 asm(AREG1);  
43 -register uint32_t T1 asm(AREG2);  
44 -register uint32_t T2 asm(AREG3); 42 +#else
  43 +
  44 +/* XXX: use unsigned long instead of target_ulong - better code will
  45 + be generated for 64 bit CPUs */
  46 +register target_ulong T0 asm(AREG1);
  47 +register target_ulong T1 asm(AREG2);
  48 +register target_ulong T2 asm(AREG3);
45 49
46 /* if more registers are available, we define some registers too */ 50 /* if more registers are available, we define some registers too */
47 #ifdef AREG4 51 #ifdef AREG4
48 -register uint32_t EAX asm(AREG4); 52 +register target_ulong EAX asm(AREG4);
49 #define reg_EAX 53 #define reg_EAX
50 #endif 54 #endif
51 55
52 #ifdef AREG5 56 #ifdef AREG5
53 -register uint32_t ESP asm(AREG5); 57 +register target_ulong ESP asm(AREG5);
54 #define reg_ESP 58 #define reg_ESP
55 #endif 59 #endif
56 60
57 #ifdef AREG6 61 #ifdef AREG6
58 -register uint32_t EBP asm(AREG6); 62 +register target_ulong EBP asm(AREG6);
59 #define reg_EBP 63 #define reg_EBP
60 #endif 64 #endif
61 65
62 #ifdef AREG7 66 #ifdef AREG7
63 -register uint32_t ECX asm(AREG7); 67 +register target_ulong ECX asm(AREG7);
64 #define reg_ECX 68 #define reg_ECX
65 #endif 69 #endif
66 70
67 #ifdef AREG8 71 #ifdef AREG8
68 -register uint32_t EDX asm(AREG8); 72 +register target_ulong EDX asm(AREG8);
69 #define reg_EDX 73 #define reg_EDX
70 #endif 74 #endif
71 75
72 #ifdef AREG9 76 #ifdef AREG9
73 -register uint32_t EBX asm(AREG9); 77 +register target_ulong EBX asm(AREG9);
74 #define reg_EBX 78 #define reg_EBX
75 #endif 79 #endif
76 80
77 #ifdef AREG10 81 #ifdef AREG10
78 -register uint32_t ESI asm(AREG10); 82 +register target_ulong ESI asm(AREG10);
79 #define reg_ESI 83 #define reg_ESI
80 #endif 84 #endif
81 85
82 #ifdef AREG11 86 #ifdef AREG11
83 -register uint32_t EDI asm(AREG11); 87 +register target_ulong EDI asm(AREG11);
84 #define reg_EDI 88 #define reg_EDI
85 #endif 89 #endif
86 90
87 -#else  
88 -  
89 -/* no registers can be used */  
90 -#define T0 (env->t0)  
91 -#define T1 (env->t1)  
92 -#define T2 (env->t2)  
93 -  
94 -#endif 91 +#endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */
95 92
96 #define A0 T2 93 #define A0 T2
97 94
target-sparc/translate.c
  View file @d785e6b
@@ -1690,7 +1690,7 @@ void cpu_dump_state(CPUState *env, FILE *f, @@ -1690,7 +1690,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
1690 } 1690 }
1691 1691
1692 #if defined(CONFIG_USER_ONLY) 1692 #if defined(CONFIG_USER_ONLY)
1693 -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) 1693 +target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1694 { 1694 {
1695 return addr; 1695 return addr;
1696 } 1696 }
@@ -1700,7 +1700,7 @@ extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, in @@ -1700,7 +1700,7 @@ extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, in
1700 int *access_index, target_ulong address, int rw, 1700 int *access_index, target_ulong address, int rw,
1701 int is_user); 1701 int is_user);
1702 1702
1703 -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) 1703 +target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1704 { 1704 {
1705 target_phys_addr_t phys_addr; 1705 target_phys_addr_t phys_addr;
1706 int prot, access_index; 1706 int prot, access_index;