Commit d731dae8e3c9591727073f6e54af08c1ee960540
1 parent
c9087c2a
currently generated
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@192 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
1 changed file
with
0 additions
and
636 deletions
opc-i386.h deleted
100644 → 0
| 1 | -DEF(end, 0) | ||
| 2 | -DEF(movl_A0_EAX, 0) | ||
| 3 | -DEF(addl_A0_EAX, 0) | ||
| 4 | -DEF(addl_A0_EAX_s1, 0) | ||
| 5 | -DEF(addl_A0_EAX_s2, 0) | ||
| 6 | -DEF(addl_A0_EAX_s3, 0) | ||
| 7 | -DEF(movl_T0_EAX, 0) | ||
| 8 | -DEF(movl_T1_EAX, 0) | ||
| 9 | -DEF(movh_T0_EAX, 0) | ||
| 10 | -DEF(movh_T1_EAX, 0) | ||
| 11 | -DEF(movl_EAX_T0, 0) | ||
| 12 | -DEF(movl_EAX_T1, 0) | ||
| 13 | -DEF(movl_EAX_A0, 0) | ||
| 14 | -DEF(cmovw_EAX_T1_T0, 0) | ||
| 15 | -DEF(cmovl_EAX_T1_T0, 0) | ||
| 16 | -DEF(movw_EAX_T0, 0) | ||
| 17 | -DEF(movw_EAX_T1, 0) | ||
| 18 | -DEF(movw_EAX_A0, 0) | ||
| 19 | -DEF(movb_EAX_T0, 0) | ||
| 20 | -DEF(movh_EAX_T0, 0) | ||
| 21 | -DEF(movb_EAX_T1, 0) | ||
| 22 | -DEF(movh_EAX_T1, 0) | ||
| 23 | -DEF(movl_A0_ECX, 0) | ||
| 24 | -DEF(addl_A0_ECX, 0) | ||
| 25 | -DEF(addl_A0_ECX_s1, 0) | ||
| 26 | -DEF(addl_A0_ECX_s2, 0) | ||
| 27 | -DEF(addl_A0_ECX_s3, 0) | ||
| 28 | -DEF(movl_T0_ECX, 0) | ||
| 29 | -DEF(movl_T1_ECX, 0) | ||
| 30 | -DEF(movh_T0_ECX, 0) | ||
| 31 | -DEF(movh_T1_ECX, 0) | ||
| 32 | -DEF(movl_ECX_T0, 0) | ||
| 33 | -DEF(movl_ECX_T1, 0) | ||
| 34 | -DEF(movl_ECX_A0, 0) | ||
| 35 | -DEF(cmovw_ECX_T1_T0, 0) | ||
| 36 | -DEF(cmovl_ECX_T1_T0, 0) | ||
| 37 | -DEF(movw_ECX_T0, 0) | ||
| 38 | -DEF(movw_ECX_T1, 0) | ||
| 39 | -DEF(movw_ECX_A0, 0) | ||
| 40 | -DEF(movb_ECX_T0, 0) | ||
| 41 | -DEF(movh_ECX_T0, 0) | ||
| 42 | -DEF(movb_ECX_T1, 0) | ||
| 43 | -DEF(movh_ECX_T1, 0) | ||
| 44 | -DEF(movl_A0_EDX, 0) | ||
| 45 | -DEF(addl_A0_EDX, 0) | ||
| 46 | -DEF(addl_A0_EDX_s1, 0) | ||
| 47 | -DEF(addl_A0_EDX_s2, 0) | ||
| 48 | -DEF(addl_A0_EDX_s3, 0) | ||
| 49 | -DEF(movl_T0_EDX, 0) | ||
| 50 | -DEF(movl_T1_EDX, 0) | ||
| 51 | -DEF(movh_T0_EDX, 0) | ||
| 52 | -DEF(movh_T1_EDX, 0) | ||
| 53 | -DEF(movl_EDX_T0, 0) | ||
| 54 | -DEF(movl_EDX_T1, 0) | ||
| 55 | -DEF(movl_EDX_A0, 0) | ||
| 56 | -DEF(cmovw_EDX_T1_T0, 0) | ||
| 57 | -DEF(cmovl_EDX_T1_T0, 0) | ||
| 58 | -DEF(movw_EDX_T0, 0) | ||
| 59 | -DEF(movw_EDX_T1, 0) | ||
| 60 | -DEF(movw_EDX_A0, 0) | ||
| 61 | -DEF(movb_EDX_T0, 0) | ||
| 62 | -DEF(movh_EDX_T0, 0) | ||
| 63 | -DEF(movb_EDX_T1, 0) | ||
| 64 | -DEF(movh_EDX_T1, 0) | ||
| 65 | -DEF(movl_A0_EBX, 0) | ||
| 66 | -DEF(addl_A0_EBX, 0) | ||
| 67 | -DEF(addl_A0_EBX_s1, 0) | ||
| 68 | -DEF(addl_A0_EBX_s2, 0) | ||
| 69 | -DEF(addl_A0_EBX_s3, 0) | ||
| 70 | -DEF(movl_T0_EBX, 0) | ||
| 71 | -DEF(movl_T1_EBX, 0) | ||
| 72 | -DEF(movh_T0_EBX, 0) | ||
| 73 | -DEF(movh_T1_EBX, 0) | ||
| 74 | -DEF(movl_EBX_T0, 0) | ||
| 75 | -DEF(movl_EBX_T1, 0) | ||
| 76 | -DEF(movl_EBX_A0, 0) | ||
| 77 | -DEF(cmovw_EBX_T1_T0, 0) | ||
| 78 | -DEF(cmovl_EBX_T1_T0, 0) | ||
| 79 | -DEF(movw_EBX_T0, 0) | ||
| 80 | -DEF(movw_EBX_T1, 0) | ||
| 81 | -DEF(movw_EBX_A0, 0) | ||
| 82 | -DEF(movb_EBX_T0, 0) | ||
| 83 | -DEF(movh_EBX_T0, 0) | ||
| 84 | -DEF(movb_EBX_T1, 0) | ||
| 85 | -DEF(movh_EBX_T1, 0) | ||
| 86 | -DEF(movl_A0_ESP, 0) | ||
| 87 | -DEF(addl_A0_ESP, 0) | ||
| 88 | -DEF(addl_A0_ESP_s1, 0) | ||
| 89 | -DEF(addl_A0_ESP_s2, 0) | ||
| 90 | -DEF(addl_A0_ESP_s3, 0) | ||
| 91 | -DEF(movl_T0_ESP, 0) | ||
| 92 | -DEF(movl_T1_ESP, 0) | ||
| 93 | -DEF(movh_T0_ESP, 0) | ||
| 94 | -DEF(movh_T1_ESP, 0) | ||
| 95 | -DEF(movl_ESP_T0, 0) | ||
| 96 | -DEF(movl_ESP_T1, 0) | ||
| 97 | -DEF(movl_ESP_A0, 0) | ||
| 98 | -DEF(cmovw_ESP_T1_T0, 0) | ||
| 99 | -DEF(cmovl_ESP_T1_T0, 0) | ||
| 100 | -DEF(movw_ESP_T0, 0) | ||
| 101 | -DEF(movw_ESP_T1, 0) | ||
| 102 | -DEF(movw_ESP_A0, 0) | ||
| 103 | -DEF(movb_ESP_T0, 0) | ||
| 104 | -DEF(movh_ESP_T0, 0) | ||
| 105 | -DEF(movb_ESP_T1, 0) | ||
| 106 | -DEF(movh_ESP_T1, 0) | ||
| 107 | -DEF(movl_A0_EBP, 0) | ||
| 108 | -DEF(addl_A0_EBP, 0) | ||
| 109 | -DEF(addl_A0_EBP_s1, 0) | ||
| 110 | -DEF(addl_A0_EBP_s2, 0) | ||
| 111 | -DEF(addl_A0_EBP_s3, 0) | ||
| 112 | -DEF(movl_T0_EBP, 0) | ||
| 113 | -DEF(movl_T1_EBP, 0) | ||
| 114 | -DEF(movh_T0_EBP, 0) | ||
| 115 | -DEF(movh_T1_EBP, 0) | ||
| 116 | -DEF(movl_EBP_T0, 0) | ||
| 117 | -DEF(movl_EBP_T1, 0) | ||
| 118 | -DEF(movl_EBP_A0, 0) | ||
| 119 | -DEF(cmovw_EBP_T1_T0, 0) | ||
| 120 | -DEF(cmovl_EBP_T1_T0, 0) | ||
| 121 | -DEF(movw_EBP_T0, 0) | ||
| 122 | -DEF(movw_EBP_T1, 0) | ||
| 123 | -DEF(movw_EBP_A0, 0) | ||
| 124 | -DEF(movb_EBP_T0, 0) | ||
| 125 | -DEF(movh_EBP_T0, 0) | ||
| 126 | -DEF(movb_EBP_T1, 0) | ||
| 127 | -DEF(movh_EBP_T1, 0) | ||
| 128 | -DEF(movl_A0_ESI, 0) | ||
| 129 | -DEF(addl_A0_ESI, 0) | ||
| 130 | -DEF(addl_A0_ESI_s1, 0) | ||
| 131 | -DEF(addl_A0_ESI_s2, 0) | ||
| 132 | -DEF(addl_A0_ESI_s3, 0) | ||
| 133 | -DEF(movl_T0_ESI, 0) | ||
| 134 | -DEF(movl_T1_ESI, 0) | ||
| 135 | -DEF(movh_T0_ESI, 0) | ||
| 136 | -DEF(movh_T1_ESI, 0) | ||
| 137 | -DEF(movl_ESI_T0, 0) | ||
| 138 | -DEF(movl_ESI_T1, 0) | ||
| 139 | -DEF(movl_ESI_A0, 0) | ||
| 140 | -DEF(cmovw_ESI_T1_T0, 0) | ||
| 141 | -DEF(cmovl_ESI_T1_T0, 0) | ||
| 142 | -DEF(movw_ESI_T0, 0) | ||
| 143 | -DEF(movw_ESI_T1, 0) | ||
| 144 | -DEF(movw_ESI_A0, 0) | ||
| 145 | -DEF(movb_ESI_T0, 0) | ||
| 146 | -DEF(movh_ESI_T0, 0) | ||
| 147 | -DEF(movb_ESI_T1, 0) | ||
| 148 | -DEF(movh_ESI_T1, 0) | ||
| 149 | -DEF(movl_A0_EDI, 0) | ||
| 150 | -DEF(addl_A0_EDI, 0) | ||
| 151 | -DEF(addl_A0_EDI_s1, 0) | ||
| 152 | -DEF(addl_A0_EDI_s2, 0) | ||
| 153 | -DEF(addl_A0_EDI_s3, 0) | ||
| 154 | -DEF(movl_T0_EDI, 0) | ||
| 155 | -DEF(movl_T1_EDI, 0) | ||
| 156 | -DEF(movh_T0_EDI, 0) | ||
| 157 | -DEF(movh_T1_EDI, 0) | ||
| 158 | -DEF(movl_EDI_T0, 0) | ||
| 159 | -DEF(movl_EDI_T1, 0) | ||
| 160 | -DEF(movl_EDI_A0, 0) | ||
| 161 | -DEF(cmovw_EDI_T1_T0, 0) | ||
| 162 | -DEF(cmovl_EDI_T1_T0, 0) | ||
| 163 | -DEF(movw_EDI_T0, 0) | ||
| 164 | -DEF(movw_EDI_T1, 0) | ||
| 165 | -DEF(movw_EDI_A0, 0) | ||
| 166 | -DEF(movb_EDI_T0, 0) | ||
| 167 | -DEF(movh_EDI_T0, 0) | ||
| 168 | -DEF(movb_EDI_T1, 0) | ||
| 169 | -DEF(movh_EDI_T1, 0) | ||
| 170 | -DEF(addl_T0_T1_cc, 0) | ||
| 171 | -DEF(orl_T0_T1_cc, 0) | ||
| 172 | -DEF(andl_T0_T1_cc, 0) | ||
| 173 | -DEF(subl_T0_T1_cc, 0) | ||
| 174 | -DEF(xorl_T0_T1_cc, 0) | ||
| 175 | -DEF(cmpl_T0_T1_cc, 0) | ||
| 176 | -DEF(negl_T0_cc, 0) | ||
| 177 | -DEF(incl_T0_cc, 0) | ||
| 178 | -DEF(decl_T0_cc, 0) | ||
| 179 | -DEF(testl_T0_T1_cc, 0) | ||
| 180 | -DEF(addl_T0_T1, 0) | ||
| 181 | -DEF(orl_T0_T1, 0) | ||
| 182 | -DEF(andl_T0_T1, 0) | ||
| 183 | -DEF(subl_T0_T1, 0) | ||
| 184 | -DEF(xorl_T0_T1, 0) | ||
| 185 | -DEF(negl_T0, 0) | ||
| 186 | -DEF(incl_T0, 0) | ||
| 187 | -DEF(decl_T0, 0) | ||
| 188 | -DEF(notl_T0, 0) | ||
| 189 | -DEF(bswapl_T0, 0) | ||
| 190 | -DEF(mulb_AL_T0, 0) | ||
| 191 | -DEF(imulb_AL_T0, 0) | ||
| 192 | -DEF(mulw_AX_T0, 0) | ||
| 193 | -DEF(imulw_AX_T0, 0) | ||
| 194 | -DEF(mull_EAX_T0, 0) | ||
| 195 | -DEF(imull_EAX_T0, 0) | ||
| 196 | -DEF(imulw_T0_T1, 0) | ||
| 197 | -DEF(imull_T0_T1, 0) | ||
| 198 | -DEF(divb_AL_T0, 0) | ||
| 199 | -DEF(idivb_AL_T0, 0) | ||
| 200 | -DEF(divw_AX_T0, 0) | ||
| 201 | -DEF(idivw_AX_T0, 0) | ||
| 202 | -DEF(divl_EAX_T0, 0) | ||
| 203 | -DEF(idivl_EAX_T0, 0) | ||
| 204 | -DEF(movl_T0_im, 1) | ||
| 205 | -DEF(addl_T0_im, 1) | ||
| 206 | -DEF(andl_T0_ffff, 0) | ||
| 207 | -DEF(movl_T0_T1, 0) | ||
| 208 | -DEF(movl_T1_im, 1) | ||
| 209 | -DEF(addl_T1_im, 1) | ||
| 210 | -DEF(movl_T1_A0, 0) | ||
| 211 | -DEF(movl_A0_im, 1) | ||
| 212 | -DEF(addl_A0_im, 1) | ||
| 213 | -DEF(addl_A0_AL, 0) | ||
| 214 | -DEF(andl_A0_ffff, 0) | ||
| 215 | -DEF(ldub_T0_A0, 0) | ||
| 216 | -DEF(ldsb_T0_A0, 0) | ||
| 217 | -DEF(lduw_T0_A0, 0) | ||
| 218 | -DEF(ldsw_T0_A0, 0) | ||
| 219 | -DEF(ldl_T0_A0, 0) | ||
| 220 | -DEF(ldub_T1_A0, 0) | ||
| 221 | -DEF(ldsb_T1_A0, 0) | ||
| 222 | -DEF(lduw_T1_A0, 0) | ||
| 223 | -DEF(ldsw_T1_A0, 0) | ||
| 224 | -DEF(ldl_T1_A0, 0) | ||
| 225 | -DEF(stb_T0_A0, 0) | ||
| 226 | -DEF(stw_T0_A0, 0) | ||
| 227 | -DEF(stl_T0_A0, 0) | ||
| 228 | -DEF(add_bitw_A0_T1, 0) | ||
| 229 | -DEF(add_bitl_A0_T1, 0) | ||
| 230 | -DEF(jmp_T0, 0) | ||
| 231 | -DEF(jmp_im, 1) | ||
| 232 | -DEF(int_im, 2) | ||
| 233 | -DEF(raise_exception, 1) | ||
| 234 | -DEF(into, 1) | ||
| 235 | -DEF(cli, 0) | ||
| 236 | -DEF(sti, 0) | ||
| 237 | -DEF(boundw, 0) | ||
| 238 | -DEF(boundl, 0) | ||
| 239 | -DEF(cmpxchg8b, 0) | ||
| 240 | -DEF(jmp_tb_next, 2) | ||
| 241 | -DEF(movl_T0_0, 0) | ||
| 242 | -DEF(jb_subb, 3) | ||
| 243 | -DEF(jz_subb, 3) | ||
| 244 | -DEF(jbe_subb, 3) | ||
| 245 | -DEF(js_subb, 3) | ||
| 246 | -DEF(jl_subb, 3) | ||
| 247 | -DEF(jle_subb, 3) | ||
| 248 | -DEF(setb_T0_subb, 0) | ||
| 249 | -DEF(setz_T0_subb, 0) | ||
| 250 | -DEF(setbe_T0_subb, 0) | ||
| 251 | -DEF(sets_T0_subb, 0) | ||
| 252 | -DEF(setl_T0_subb, 0) | ||
| 253 | -DEF(setle_T0_subb, 0) | ||
| 254 | -DEF(rolb_T0_T1_cc, 0) | ||
| 255 | -DEF(rolb_T0_T1, 0) | ||
| 256 | -DEF(rorb_T0_T1_cc, 0) | ||
| 257 | -DEF(rorb_T0_T1, 0) | ||
| 258 | -DEF(rclb_T0_T1_cc, 0) | ||
| 259 | -DEF(rcrb_T0_T1_cc, 0) | ||
| 260 | -DEF(shlb_T0_T1_cc, 0) | ||
| 261 | -DEF(shlb_T0_T1, 0) | ||
| 262 | -DEF(shrb_T0_T1_cc, 0) | ||
| 263 | -DEF(shrb_T0_T1, 0) | ||
| 264 | -DEF(sarb_T0_T1_cc, 0) | ||
| 265 | -DEF(sarb_T0_T1, 0) | ||
| 266 | -DEF(adcb_T0_T1_cc, 0) | ||
| 267 | -DEF(sbbb_T0_T1_cc, 0) | ||
| 268 | -DEF(cmpxchgb_T0_T1_EAX_cc, 0) | ||
| 269 | -DEF(movsb_fast, 0) | ||
| 270 | -DEF(rep_movsb_fast, 0) | ||
| 271 | -DEF(stosb_fast, 0) | ||
| 272 | -DEF(rep_stosb_fast, 0) | ||
| 273 | -DEF(lodsb_fast, 0) | ||
| 274 | -DEF(rep_lodsb_fast, 0) | ||
| 275 | -DEF(scasb_fast, 0) | ||
| 276 | -DEF(repz_scasb_fast, 0) | ||
| 277 | -DEF(repnz_scasb_fast, 0) | ||
| 278 | -DEF(cmpsb_fast, 0) | ||
| 279 | -DEF(repz_cmpsb_fast, 0) | ||
| 280 | -DEF(repnz_cmpsb_fast, 0) | ||
| 281 | -DEF(outsb_fast, 0) | ||
| 282 | -DEF(rep_outsb_fast, 0) | ||
| 283 | -DEF(insb_fast, 0) | ||
| 284 | -DEF(rep_insb_fast, 0) | ||
| 285 | -DEF(movsb_a32, 0) | ||
| 286 | -DEF(rep_movsb_a32, 0) | ||
| 287 | -DEF(stosb_a32, 0) | ||
| 288 | -DEF(rep_stosb_a32, 0) | ||
| 289 | -DEF(lodsb_a32, 0) | ||
| 290 | -DEF(rep_lodsb_a32, 0) | ||
| 291 | -DEF(scasb_a32, 0) | ||
| 292 | -DEF(repz_scasb_a32, 0) | ||
| 293 | -DEF(repnz_scasb_a32, 0) | ||
| 294 | -DEF(cmpsb_a32, 0) | ||
| 295 | -DEF(repz_cmpsb_a32, 0) | ||
| 296 | -DEF(repnz_cmpsb_a32, 0) | ||
| 297 | -DEF(outsb_a32, 0) | ||
| 298 | -DEF(rep_outsb_a32, 0) | ||
| 299 | -DEF(insb_a32, 0) | ||
| 300 | -DEF(rep_insb_a32, 0) | ||
| 301 | -DEF(movsb_a16, 0) | ||
| 302 | -DEF(rep_movsb_a16, 0) | ||
| 303 | -DEF(stosb_a16, 0) | ||
| 304 | -DEF(rep_stosb_a16, 0) | ||
| 305 | -DEF(lodsb_a16, 0) | ||
| 306 | -DEF(rep_lodsb_a16, 0) | ||
| 307 | -DEF(scasb_a16, 0) | ||
| 308 | -DEF(repz_scasb_a16, 0) | ||
| 309 | -DEF(repnz_scasb_a16, 0) | ||
| 310 | -DEF(cmpsb_a16, 0) | ||
| 311 | -DEF(repz_cmpsb_a16, 0) | ||
| 312 | -DEF(repnz_cmpsb_a16, 0) | ||
| 313 | -DEF(outsb_a16, 0) | ||
| 314 | -DEF(rep_outsb_a16, 0) | ||
| 315 | -DEF(insb_a16, 0) | ||
| 316 | -DEF(rep_insb_a16, 0) | ||
| 317 | -DEF(outb_T0_T1, 0) | ||
| 318 | -DEF(inb_T0_T1, 0) | ||
| 319 | -DEF(jb_subw, 3) | ||
| 320 | -DEF(jz_subw, 3) | ||
| 321 | -DEF(jbe_subw, 3) | ||
| 322 | -DEF(js_subw, 3) | ||
| 323 | -DEF(jl_subw, 3) | ||
| 324 | -DEF(jle_subw, 3) | ||
| 325 | -DEF(loopnzw, 2) | ||
| 326 | -DEF(loopzw, 2) | ||
| 327 | -DEF(loopw, 2) | ||
| 328 | -DEF(jecxzw, 2) | ||
| 329 | -DEF(setb_T0_subw, 0) | ||
| 330 | -DEF(setz_T0_subw, 0) | ||
| 331 | -DEF(setbe_T0_subw, 0) | ||
| 332 | -DEF(sets_T0_subw, 0) | ||
| 333 | -DEF(setl_T0_subw, 0) | ||
| 334 | -DEF(setle_T0_subw, 0) | ||
| 335 | -DEF(rolw_T0_T1_cc, 0) | ||
| 336 | -DEF(rolw_T0_T1, 0) | ||
| 337 | -DEF(rorw_T0_T1_cc, 0) | ||
| 338 | -DEF(rorw_T0_T1, 0) | ||
| 339 | -DEF(rclw_T0_T1_cc, 0) | ||
| 340 | -DEF(rcrw_T0_T1_cc, 0) | ||
| 341 | -DEF(shlw_T0_T1_cc, 0) | ||
| 342 | -DEF(shlw_T0_T1, 0) | ||
| 343 | -DEF(shrw_T0_T1_cc, 0) | ||
| 344 | -DEF(shrw_T0_T1, 0) | ||
| 345 | -DEF(sarw_T0_T1_cc, 0) | ||
| 346 | -DEF(sarw_T0_T1, 0) | ||
| 347 | -DEF(shldw_T0_T1_im_cc, 1) | ||
| 348 | -DEF(shldw_T0_T1_ECX_cc, 0) | ||
| 349 | -DEF(shrdw_T0_T1_im_cc, 1) | ||
| 350 | -DEF(shrdw_T0_T1_ECX_cc, 0) | ||
| 351 | -DEF(adcw_T0_T1_cc, 0) | ||
| 352 | -DEF(sbbw_T0_T1_cc, 0) | ||
| 353 | -DEF(cmpxchgw_T0_T1_EAX_cc, 0) | ||
| 354 | -DEF(btw_T0_T1_cc, 0) | ||
| 355 | -DEF(btsw_T0_T1_cc, 0) | ||
| 356 | -DEF(btrw_T0_T1_cc, 0) | ||
| 357 | -DEF(btcw_T0_T1_cc, 0) | ||
| 358 | -DEF(bsfw_T0_cc, 0) | ||
| 359 | -DEF(bsrw_T0_cc, 0) | ||
| 360 | -DEF(movsw_fast, 0) | ||
| 361 | -DEF(rep_movsw_fast, 0) | ||
| 362 | -DEF(stosw_fast, 0) | ||
| 363 | -DEF(rep_stosw_fast, 0) | ||
| 364 | -DEF(lodsw_fast, 0) | ||
| 365 | -DEF(rep_lodsw_fast, 0) | ||
| 366 | -DEF(scasw_fast, 0) | ||
| 367 | -DEF(repz_scasw_fast, 0) | ||
| 368 | -DEF(repnz_scasw_fast, 0) | ||
| 369 | -DEF(cmpsw_fast, 0) | ||
| 370 | -DEF(repz_cmpsw_fast, 0) | ||
| 371 | -DEF(repnz_cmpsw_fast, 0) | ||
| 372 | -DEF(outsw_fast, 0) | ||
| 373 | -DEF(rep_outsw_fast, 0) | ||
| 374 | -DEF(insw_fast, 0) | ||
| 375 | -DEF(rep_insw_fast, 0) | ||
| 376 | -DEF(movsw_a32, 0) | ||
| 377 | -DEF(rep_movsw_a32, 0) | ||
| 378 | -DEF(stosw_a32, 0) | ||
| 379 | -DEF(rep_stosw_a32, 0) | ||
| 380 | -DEF(lodsw_a32, 0) | ||
| 381 | -DEF(rep_lodsw_a32, 0) | ||
| 382 | -DEF(scasw_a32, 0) | ||
| 383 | -DEF(repz_scasw_a32, 0) | ||
| 384 | -DEF(repnz_scasw_a32, 0) | ||
| 385 | -DEF(cmpsw_a32, 0) | ||
| 386 | -DEF(repz_cmpsw_a32, 0) | ||
| 387 | -DEF(repnz_cmpsw_a32, 0) | ||
| 388 | -DEF(outsw_a32, 0) | ||
| 389 | -DEF(rep_outsw_a32, 0) | ||
| 390 | -DEF(insw_a32, 0) | ||
| 391 | -DEF(rep_insw_a32, 0) | ||
| 392 | -DEF(movsw_a16, 0) | ||
| 393 | -DEF(rep_movsw_a16, 0) | ||
| 394 | -DEF(stosw_a16, 0) | ||
| 395 | -DEF(rep_stosw_a16, 0) | ||
| 396 | -DEF(lodsw_a16, 0) | ||
| 397 | -DEF(rep_lodsw_a16, 0) | ||
| 398 | -DEF(scasw_a16, 0) | ||
| 399 | -DEF(repz_scasw_a16, 0) | ||
| 400 | -DEF(repnz_scasw_a16, 0) | ||
| 401 | -DEF(cmpsw_a16, 0) | ||
| 402 | -DEF(repz_cmpsw_a16, 0) | ||
| 403 | -DEF(repnz_cmpsw_a16, 0) | ||
| 404 | -DEF(outsw_a16, 0) | ||
| 405 | -DEF(rep_outsw_a16, 0) | ||
| 406 | -DEF(insw_a16, 0) | ||
| 407 | -DEF(rep_insw_a16, 0) | ||
| 408 | -DEF(outw_T0_T1, 0) | ||
| 409 | -DEF(inw_T0_T1, 0) | ||
| 410 | -DEF(jb_subl, 3) | ||
| 411 | -DEF(jz_subl, 3) | ||
| 412 | -DEF(jbe_subl, 3) | ||
| 413 | -DEF(js_subl, 3) | ||
| 414 | -DEF(jl_subl, 3) | ||
| 415 | -DEF(jle_subl, 3) | ||
| 416 | -DEF(loopnzl, 2) | ||
| 417 | -DEF(loopzl, 2) | ||
| 418 | -DEF(loopl, 2) | ||
| 419 | -DEF(jecxzl, 2) | ||
| 420 | -DEF(setb_T0_subl, 0) | ||
| 421 | -DEF(setz_T0_subl, 0) | ||
| 422 | -DEF(setbe_T0_subl, 0) | ||
| 423 | -DEF(sets_T0_subl, 0) | ||
| 424 | -DEF(setl_T0_subl, 0) | ||
| 425 | -DEF(setle_T0_subl, 0) | ||
| 426 | -DEF(roll_T0_T1_cc, 0) | ||
| 427 | -DEF(roll_T0_T1, 0) | ||
| 428 | -DEF(rorl_T0_T1_cc, 0) | ||
| 429 | -DEF(rorl_T0_T1, 0) | ||
| 430 | -DEF(rcll_T0_T1_cc, 0) | ||
| 431 | -DEF(rcrl_T0_T1_cc, 0) | ||
| 432 | -DEF(shll_T0_T1_cc, 0) | ||
| 433 | -DEF(shll_T0_T1, 0) | ||
| 434 | -DEF(shrl_T0_T1_cc, 0) | ||
| 435 | -DEF(shrl_T0_T1, 0) | ||
| 436 | -DEF(sarl_T0_T1_cc, 0) | ||
| 437 | -DEF(sarl_T0_T1, 0) | ||
| 438 | -DEF(shldl_T0_T1_im_cc, 1) | ||
| 439 | -DEF(shldl_T0_T1_ECX_cc, 0) | ||
| 440 | -DEF(shrdl_T0_T1_im_cc, 1) | ||
| 441 | -DEF(shrdl_T0_T1_ECX_cc, 0) | ||
| 442 | -DEF(adcl_T0_T1_cc, 0) | ||
| 443 | -DEF(sbbl_T0_T1_cc, 0) | ||
| 444 | -DEF(cmpxchgl_T0_T1_EAX_cc, 0) | ||
| 445 | -DEF(btl_T0_T1_cc, 0) | ||
| 446 | -DEF(btsl_T0_T1_cc, 0) | ||
| 447 | -DEF(btrl_T0_T1_cc, 0) | ||
| 448 | -DEF(btcl_T0_T1_cc, 0) | ||
| 449 | -DEF(bsfl_T0_cc, 0) | ||
| 450 | -DEF(bsrl_T0_cc, 0) | ||
| 451 | -DEF(movsl_fast, 0) | ||
| 452 | -DEF(rep_movsl_fast, 0) | ||
| 453 | -DEF(stosl_fast, 0) | ||
| 454 | -DEF(rep_stosl_fast, 0) | ||
| 455 | -DEF(lodsl_fast, 0) | ||
| 456 | -DEF(rep_lodsl_fast, 0) | ||
| 457 | -DEF(scasl_fast, 0) | ||
| 458 | -DEF(repz_scasl_fast, 0) | ||
| 459 | -DEF(repnz_scasl_fast, 0) | ||
| 460 | -DEF(cmpsl_fast, 0) | ||
| 461 | -DEF(repz_cmpsl_fast, 0) | ||
| 462 | -DEF(repnz_cmpsl_fast, 0) | ||
| 463 | -DEF(outsl_fast, 0) | ||
| 464 | -DEF(rep_outsl_fast, 0) | ||
| 465 | -DEF(insl_fast, 0) | ||
| 466 | -DEF(rep_insl_fast, 0) | ||
| 467 | -DEF(movsl_a32, 0) | ||
| 468 | -DEF(rep_movsl_a32, 0) | ||
| 469 | -DEF(stosl_a32, 0) | ||
| 470 | -DEF(rep_stosl_a32, 0) | ||
| 471 | -DEF(lodsl_a32, 0) | ||
| 472 | -DEF(rep_lodsl_a32, 0) | ||
| 473 | -DEF(scasl_a32, 0) | ||
| 474 | -DEF(repz_scasl_a32, 0) | ||
| 475 | -DEF(repnz_scasl_a32, 0) | ||
| 476 | -DEF(cmpsl_a32, 0) | ||
| 477 | -DEF(repz_cmpsl_a32, 0) | ||
| 478 | -DEF(repnz_cmpsl_a32, 0) | ||
| 479 | -DEF(outsl_a32, 0) | ||
| 480 | -DEF(rep_outsl_a32, 0) | ||
| 481 | -DEF(insl_a32, 0) | ||
| 482 | -DEF(rep_insl_a32, 0) | ||
| 483 | -DEF(movsl_a16, 0) | ||
| 484 | -DEF(rep_movsl_a16, 0) | ||
| 485 | -DEF(stosl_a16, 0) | ||
| 486 | -DEF(rep_stosl_a16, 0) | ||
| 487 | -DEF(lodsl_a16, 0) | ||
| 488 | -DEF(rep_lodsl_a16, 0) | ||
| 489 | -DEF(scasl_a16, 0) | ||
| 490 | -DEF(repz_scasl_a16, 0) | ||
| 491 | -DEF(repnz_scasl_a16, 0) | ||
| 492 | -DEF(cmpsl_a16, 0) | ||
| 493 | -DEF(repz_cmpsl_a16, 0) | ||
| 494 | -DEF(repnz_cmpsl_a16, 0) | ||
| 495 | -DEF(outsl_a16, 0) | ||
| 496 | -DEF(rep_outsl_a16, 0) | ||
| 497 | -DEF(insl_a16, 0) | ||
| 498 | -DEF(rep_insl_a16, 0) | ||
| 499 | -DEF(outl_T0_T1, 0) | ||
| 500 | -DEF(inl_T0_T1, 0) | ||
| 501 | -DEF(movsbl_T0_T0, 0) | ||
| 502 | -DEF(movzbl_T0_T0, 0) | ||
| 503 | -DEF(movswl_T0_T0, 0) | ||
| 504 | -DEF(movzwl_T0_T0, 0) | ||
| 505 | -DEF(movswl_EAX_AX, 0) | ||
| 506 | -DEF(movsbw_AX_AL, 0) | ||
| 507 | -DEF(movslq_EDX_EAX, 0) | ||
| 508 | -DEF(movswl_DX_AX, 0) | ||
| 509 | -DEF(pushl_T0, 0) | ||
| 510 | -DEF(pushw_T0, 0) | ||
| 511 | -DEF(pushl_ss32_T0, 0) | ||
| 512 | -DEF(pushw_ss32_T0, 0) | ||
| 513 | -DEF(pushl_ss16_T0, 0) | ||
| 514 | -DEF(pushw_ss16_T0, 0) | ||
| 515 | -DEF(popl_T0, 0) | ||
| 516 | -DEF(popw_T0, 0) | ||
| 517 | -DEF(popl_ss32_T0, 0) | ||
| 518 | -DEF(popw_ss32_T0, 0) | ||
| 519 | -DEF(popl_ss16_T0, 0) | ||
| 520 | -DEF(popw_ss16_T0, 0) | ||
| 521 | -DEF(addl_ESP_4, 0) | ||
| 522 | -DEF(addl_ESP_2, 0) | ||
| 523 | -DEF(addw_ESP_4, 0) | ||
| 524 | -DEF(addw_ESP_2, 0) | ||
| 525 | -DEF(addl_ESP_im, 1) | ||
| 526 | -DEF(addw_ESP_im, 1) | ||
| 527 | -DEF(rdtsc, 0) | ||
| 528 | -DEF(cpuid, 0) | ||
| 529 | -DEF(aam, 1) | ||
| 530 | -DEF(aad, 1) | ||
| 531 | -DEF(aaa, 0) | ||
| 532 | -DEF(aas, 0) | ||
| 533 | -DEF(daa, 0) | ||
| 534 | -DEF(das, 0) | ||
| 535 | -DEF(movl_seg_T0, 1) | ||
| 536 | -DEF(movl_T0_seg, 1) | ||
| 537 | -DEF(movl_A0_seg, 1) | ||
| 538 | -DEF(addl_A0_seg, 1) | ||
| 539 | -DEF(lsl, 0) | ||
| 540 | -DEF(lar, 0) | ||
| 541 | -DEF(jcc, 3) | ||
| 542 | -DEF(seto_T0_cc, 0) | ||
| 543 | -DEF(setb_T0_cc, 0) | ||
| 544 | -DEF(setz_T0_cc, 0) | ||
| 545 | -DEF(setbe_T0_cc, 0) | ||
| 546 | -DEF(sets_T0_cc, 0) | ||
| 547 | -DEF(setp_T0_cc, 0) | ||
| 548 | -DEF(setl_T0_cc, 0) | ||
| 549 | -DEF(setle_T0_cc, 0) | ||
| 550 | -DEF(xor_T0_1, 0) | ||
| 551 | -DEF(set_cc_op, 1) | ||
| 552 | -DEF(movl_eflags_T0, 0) | ||
| 553 | -DEF(movw_eflags_T0, 0) | ||
| 554 | -DEF(movb_eflags_T0, 0) | ||
| 555 | -DEF(movl_T0_eflags, 0) | ||
| 556 | -DEF(cld, 0) | ||
| 557 | -DEF(std, 0) | ||
| 558 | -DEF(clc, 0) | ||
| 559 | -DEF(stc, 0) | ||
| 560 | -DEF(cmc, 0) | ||
| 561 | -DEF(salc, 0) | ||
| 562 | -DEF(flds_FT0_A0, 0) | ||
| 563 | -DEF(fldl_FT0_A0, 0) | ||
| 564 | -DEF(fild_FT0_A0, 0) | ||
| 565 | -DEF(fildl_FT0_A0, 0) | ||
| 566 | -DEF(fildll_FT0_A0, 0) | ||
| 567 | -DEF(flds_ST0_A0, 0) | ||
| 568 | -DEF(fldl_ST0_A0, 0) | ||
| 569 | -DEF(fldt_ST0_A0, 0) | ||
| 570 | -DEF(fild_ST0_A0, 0) | ||
| 571 | -DEF(fildl_ST0_A0, 0) | ||
| 572 | -DEF(fildll_ST0_A0, 0) | ||
| 573 | -DEF(fsts_ST0_A0, 0) | ||
| 574 | -DEF(fstl_ST0_A0, 0) | ||
| 575 | -DEF(fstt_ST0_A0, 0) | ||
| 576 | -DEF(fist_ST0_A0, 0) | ||
| 577 | -DEF(fistl_ST0_A0, 0) | ||
| 578 | -DEF(fistll_ST0_A0, 0) | ||
| 579 | -DEF(fbld_ST0_A0, 0) | ||
| 580 | -DEF(fbst_ST0_A0, 0) | ||
| 581 | -DEF(fpush, 0) | ||
| 582 | -DEF(fpop, 0) | ||
| 583 | -DEF(fdecstp, 0) | ||
| 584 | -DEF(fincstp, 0) | ||
| 585 | -DEF(fmov_ST0_FT0, 0) | ||
| 586 | -DEF(fmov_FT0_STN, 1) | ||
| 587 | -DEF(fmov_ST0_STN, 1) | ||
| 588 | -DEF(fmov_STN_ST0, 1) | ||
| 589 | -DEF(fxchg_ST0_STN, 1) | ||
| 590 | -DEF(fcom_ST0_FT0, 0) | ||
| 591 | -DEF(fucom_ST0_FT0, 0) | ||
| 592 | -DEF(fadd_ST0_FT0, 0) | ||
| 593 | -DEF(fmul_ST0_FT0, 0) | ||
| 594 | -DEF(fsub_ST0_FT0, 0) | ||
| 595 | -DEF(fsubr_ST0_FT0, 0) | ||
| 596 | -DEF(fdiv_ST0_FT0, 0) | ||
| 597 | -DEF(fdivr_ST0_FT0, 0) | ||
| 598 | -DEF(fadd_STN_ST0, 1) | ||
| 599 | -DEF(fmul_STN_ST0, 1) | ||
| 600 | -DEF(fsub_STN_ST0, 1) | ||
| 601 | -DEF(fsubr_STN_ST0, 1) | ||
| 602 | -DEF(fdiv_STN_ST0, 1) | ||
| 603 | -DEF(fdivr_STN_ST0, 1) | ||
| 604 | -DEF(fchs_ST0, 0) | ||
| 605 | -DEF(fabs_ST0, 0) | ||
| 606 | -DEF(fxam_ST0, 0) | ||
| 607 | -DEF(fld1_ST0, 0) | ||
| 608 | -DEF(fldl2t_ST0, 0) | ||
| 609 | -DEF(fldl2e_ST0, 0) | ||
| 610 | -DEF(fldpi_ST0, 0) | ||
| 611 | -DEF(fldlg2_ST0, 0) | ||
| 612 | -DEF(fldln2_ST0, 0) | ||
| 613 | -DEF(fldz_ST0, 0) | ||
| 614 | -DEF(fldz_FT0, 0) | ||
| 615 | -DEF(f2xm1, 0) | ||
| 616 | -DEF(fyl2x, 0) | ||
| 617 | -DEF(fptan, 0) | ||
| 618 | -DEF(fpatan, 0) | ||
| 619 | -DEF(fxtract, 0) | ||
| 620 | -DEF(fprem1, 0) | ||
| 621 | -DEF(fprem, 0) | ||
| 622 | -DEF(fyl2xp1, 0) | ||
| 623 | -DEF(fsqrt, 0) | ||
| 624 | -DEF(fsincos, 0) | ||
| 625 | -DEF(frndint, 0) | ||
| 626 | -DEF(fscale, 0) | ||
| 627 | -DEF(fsin, 0) | ||
| 628 | -DEF(fcos, 0) | ||
| 629 | -DEF(fnstsw_A0, 0) | ||
| 630 | -DEF(fnstsw_EAX, 0) | ||
| 631 | -DEF(fnstcw_A0, 0) | ||
| 632 | -DEF(fldcw_A0, 0) | ||
| 633 | -DEF(fclex, 0) | ||
| 634 | -DEF(fninit, 0) | ||
| 635 | -DEF(lock, 0) | ||
| 636 | -DEF(unlock, 0) |