gwj / at91sam9263 · Commits

Commit d64477afa1e2589febd78a681809b361330f2ca9

Authored by bellard
1 parent f6bac380

imul imm8 fix - 0x82 opcode support (Hidemi KAWAI) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@735 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 5 additions and 1 deletions
target-i386/translate-copy.c
  View file @d64477a
@@ -389,6 +389,7 @@ static int disas_insn(DisasContext *s) @@ -389,6 +389,7 @@ static int disas_insn(DisasContext *s)
389 389
390 case 0x80: /* GRP1 */ 390 case 0x80: /* GRP1 */
391 case 0x81: 391 case 0x81:
  392 + case 0x82:
392 case 0x83: 393 case 0x83:
393 { 394 {
394 if ((b & 1) == 0) 395 if ((b & 1) == 0)
@@ -403,6 +404,7 @@ static int disas_insn(DisasContext *s) @@ -403,6 +404,7 @@ static int disas_insn(DisasContext *s)
403 default: 404 default:
404 case 0x80: 405 case 0x80:
405 case 0x81: 406 case 0x81:
  407 + case 0x82:
406 insn_get(s, ot); 408 insn_get(s, ot);
407 break; 409 break;
408 case 0x83: 410 case 0x83:
target-i386/translate.c
  View file @d64477a
@@ -1938,6 +1938,7 @@ static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start) @@ -1938,6 +1938,7 @@ static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1938 1938
1939 case 0x80: /* GRP1 */ 1939 case 0x80: /* GRP1 */
1940 case 0x81: 1940 case 0x81:
  1941 + case 0x82:
1941 case 0x83: 1942 case 0x83:
1942 { 1943 {
1943 int val; 1944 int val;
@@ -1963,6 +1964,7 @@ static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start) @@ -1963,6 +1964,7 @@ static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1963 default: 1964 default:
1964 case 0x80: 1965 case 0x80:
1965 case 0x81: 1966 case 0x81:
  1967 + case 0x82:
1966 val = insn_get(s, ot); 1968 val = insn_get(s, ot);
1967 break; 1969 break;
1968 case 0x83: 1970 case 0x83:
@@ -2242,7 +2244,7 @@ static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start) @@ -2242,7 +2244,7 @@ static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
2242 val = insn_get(s, ot); 2244 val = insn_get(s, ot);
2243 gen_op_movl_T1_im(val); 2245 gen_op_movl_T1_im(val);
2244 } else if (b == 0x6b) { 2246 } else if (b == 0x6b) {
2245 - val = insn_get(s, OT_BYTE); 2247 + val = (int8_t)insn_get(s, OT_BYTE);
2246 gen_op_movl_T1_im(val); 2248 gen_op_movl_T1_im(val);
2247 } else { 2249 } else {
2248 gen_op_mov_TN_reg[ot][1][reg](); 2250 gen_op_mov_TN_reg[ot][1][reg]();