gwj / at91sam9263 · Commits

Commit d63001d11434fc6bf217255b51f625a75d05fb35

Authored by j_mayer
1 parent 06403421

Make PowerPC cache line size implementation dependant. 

Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 7 changed files with 620 additions and 60 deletions
target-ppc/cpu.h
  View file @d63001d
... ... @@ -82,12 +82,6 @@ typedef uint32_t ppc_gpr_t;
82 82 #define ELF_MACHINE EM_PPC
83 83 #endif
84 84  
85   -/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
86   - * have different cache line sizes
87   - */
88   -#define ICACHE_LINE_SIZE 32
89   -#define DCACHE_LINE_SIZE 32
90   -
91 85 /*****************************************************************************/
92 86 /* MMU model */
93 87 enum {
... ... @@ -521,6 +515,9 @@ struct CPUPPCState {
521 515 /* 403 dedicated access protection registers */
522 516 target_ulong pb[4];
523 517  
  518 + int dcache_line_size;
  519 + int icache_line_size;
  520 +
524 521 /* Those resources are used during exception processing */
525 522 /* CPU model definition */
526 523 target_ulong msr_mask;
... ... @@ -546,6 +543,7 @@ struct CPUPPCState {
546 543 target_ulong excp_prefix;
547 544 target_ulong ivor_mask;
548 545 target_ulong ivpr_mask;
  546 + target_ulong hreset_vector;
549 547 #endif
550 548  
551 549 /* Those resources are used only during code translation */
... ... @@ -1052,6 +1050,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1052 1050 #define SPR_601_HID5 (0x3F5)
1053 1051 #define SPR_40x_DAC1 (0x3F6)
1054 1052 #define SPR_MSSCR0 (0x3F6)
  1053 +#define SPR_970_HID5 (0x3F6)
1055 1054 #define SPR_MSSSR0 (0x3F7)
1056 1055 #define SPR_DABRX (0x3F7)
1057 1056 #define SPR_40x_DAC2 (0x3F7)
... ...
target-ppc/op_helper.c
  View file @d63001d
... ... @@ -1061,21 +1061,21 @@ void do_POWER_clcs (void)
1061 1061 switch (T0) {
1062 1062 case 0x0CUL:
1063 1063 /* Instruction cache line size */
1064   - T0 = ICACHE_LINE_SIZE;
  1064 + T0 = env->icache_line_size;
1065 1065 break;
1066 1066 case 0x0DUL:
1067 1067 /* Data cache line size */
1068   - T0 = DCACHE_LINE_SIZE;
  1068 + T0 = env->dcache_line_size;
1069 1069 break;
1070 1070 case 0x0EUL:
1071 1071 /* Minimum cache line size */
1072   - T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
1073   - ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
  1072 + T0 = env->icache_line_size < env->dcache_line_size ?
  1073 + env->icache_line_size : env->dcache_line_size;
1074 1074 break;
1075 1075 case 0x0FUL:
1076 1076 /* Maximum cache line size */
1077   - T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
1078   - ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
  1077 + T0 = env->icache_line_size > env->dcache_line_size ?
  1078 + env->icache_line_size : env->dcache_line_size;
1079 1079 break;
1080 1080 default:
1081 1081 /* Undefined */
... ...
target-ppc/op_helper.h
  View file @d63001d
... ... @@ -30,6 +30,7 @@ void glue(do_lmw_le, MEMSUFFIX) (int dst);
30 30 void glue(do_stmw, MEMSUFFIX) (int src);
31 31 void glue(do_stmw_le, MEMSUFFIX) (int src);
32 32 void glue(do_icbi, MEMSUFFIX) (void);
  33 +void glue(do_dcbz, MEMSUFFIX) (void);
33 34 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb);
34 35 void glue(do_POWER2_lfq, MEMSUFFIX) (void);
35 36 void glue(do_POWER2_lfq_le, MEMSUFFIX) (void);
... ... @@ -46,6 +47,7 @@ void glue(do_lmw_le_64, MEMSUFFIX) (int dst);
46 47 void glue(do_stmw_64, MEMSUFFIX) (int src);
47 48 void glue(do_stmw_le_64, MEMSUFFIX) (int src);
48 49 void glue(do_icbi_64, MEMSUFFIX) (void);
  50 +void glue(do_dcbz_64, MEMSUFFIX) (void);
49 51 #endif
50 52  
51 53 #else
... ...
target-ppc/op_helper_mem.h
  View file @d63001d
... ... @@ -252,8 +252,9 @@ void glue(do_icbi, MEMSUFFIX) (void)
252 252 * do the load "by hand".
253 253 */
254 254 tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
255   - T0 &= ~(ICACHE_LINE_SIZE - 1);
256   - tb_invalidate_page_range((uint32_t)T0, (uint32_t)(T0 + ICACHE_LINE_SIZE));
  255 + T0 &= ~(env->icache_line_size - 1);
  256 + tb_invalidate_page_range((uint32_t)T0,
  257 + (uint32_t)(T0 + env->icache_line_size));
257 258 }
258 259  
259 260 #if defined(TARGET_PPC64)
... ... @@ -266,8 +267,101 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
266 267 * do the load "by hand".
267 268 */
268 269 tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
269   - T0 &= ~(ICACHE_LINE_SIZE - 1);
270   - tb_invalidate_page_range((uint64_t)T0, (uint64_t)(T0 + ICACHE_LINE_SIZE));
  270 + T0 &= ~(env->icache_line_size - 1);
  271 + tb_invalidate_page_range((uint64_t)T0,
  272 + (uint64_t)(T0 + env->icache_line_size));
  273 +}
  274 +#endif
  275 +
  276 +void glue(do_dcbz, MEMSUFFIX) (void)
  277 +{
  278 + int dcache_line_size = env->dcache_line_size;
  279 +
  280 + /* XXX: should be 970 specific (?) */
  281 + if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
  282 + dcache_line_size = 32;
  283 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
  284 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
  285 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
  286 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
  287 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
  288 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
  289 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
  290 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
  291 + if (dcache_line_size >= 64) {
  292 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
  293 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
  294 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
  295 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
  296 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
  297 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
  298 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
  299 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
  300 + if (dcache_line_size >= 128) {
  301 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
  302 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
  303 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
  304 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
  305 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
  306 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
  307 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
  308 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
  309 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
  310 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
  311 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
  312 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
  313 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
  314 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
  315 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
  316 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
  317 + }
  318 + }
  319 +}
  320 +
  321 +#if defined(TARGET_PPC64)
  322 +void glue(do_dcbz_64, MEMSUFFIX) (void)
  323 +{
  324 + int dcache_line_size = env->dcache_line_size;
  325 +
  326 + /* XXX: should be 970 specific (?) */
  327 + if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
  328 + dcache_line_size = 32;
  329 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
  330 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
  331 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
  332 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
  333 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
  334 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
  335 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
  336 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
  337 + if (dcache_line_size >= 64) {
  338 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
  339 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
  340 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
  341 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
  342 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
  343 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
  344 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
  345 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
  346 + if (dcache_line_size >= 128) {
  347 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
  348 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
  349 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
  350 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
  351 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
  352 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
  353 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
  354 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
  355 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
  356 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
  357 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
  358 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
  359 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
  360 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
  361 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
  362 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
  363 + }
  364 + }
271 365 }
272 366 #endif
273 367  
... ...
target-ppc/op_mem.h
  View file @d63001d
... ... @@ -787,7 +787,20 @@ void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
787 787 }
788 788 #endif
789 789  
790   -void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
  790 +void OPPROTO glue(op_dcbz_l32, MEMSUFFIX) (void)
  791 +{
  792 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
  793 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
  794 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
  795 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
  796 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
  797 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
  798 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
  799 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
  800 + RETURN();
  801 +}
  802 +
  803 +void OPPROTO glue(op_dcbz_l64, MEMSUFFIX) (void)
791 804 {
792 805 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
793 806 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
... ... @@ -797,8 +810,6 @@ void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
797 810 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
798 811 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
799 812 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
800   -#if DCACHE_LINE_SIZE == 64
801   - /* XXX: cache line size should be 64 for POWER & PowerPC 601 */
802 813 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
803 814 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
804 815 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
... ... @@ -807,12 +818,67 @@ void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
807 818 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
808 819 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
809 820 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
810   -#endif
  821 + RETURN();
  822 +}
  823 +
  824 +void OPPROTO glue(op_dcbz_l128, MEMSUFFIX) (void)
  825 +{
  826 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
  827 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
  828 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
  829 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
  830 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
  831 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
  832 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
  833 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
  834 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
  835 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
  836 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
  837 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
  838 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
  839 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
  840 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
  841 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
  842 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
  843 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
  844 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
  845 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
  846 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
  847 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
  848 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
  849 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
  850 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
  851 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
  852 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
  853 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
  854 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
  855 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
  856 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
  857 + glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
  858 + RETURN();
  859 +}
  860 +
  861 +void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
  862 +{
  863 + glue(do_dcbz, MEMSUFFIX)();
811 864 RETURN();
812 865 }
813 866  
814 867 #if defined(TARGET_PPC64)
815   -void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
  868 +void OPPROTO glue(op_dcbz_l32_64, MEMSUFFIX) (void)
  869 +{
  870 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
  871 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
  872 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
  873 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
  874 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
  875 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
  876 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
  877 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
  878 + RETURN();
  879 +}
  880 +
  881 +void OPPROTO glue(op_dcbz_l64_64, MEMSUFFIX) (void)
816 882 {
817 883 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
818 884 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
... ... @@ -822,8 +888,6 @@ void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
822 888 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
823 889 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
824 890 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
825   -#if DCACHE_LINE_SIZE == 64
826   - /* XXX: cache line size should be 64 for POWER & PowerPC 601 */
827 891 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
828 892 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
829 893 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
... ... @@ -832,7 +896,49 @@ void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
832 896 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
833 897 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
834 898 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
835   -#endif
  899 + RETURN();
  900 +}
  901 +
  902 +void OPPROTO glue(op_dcbz_l128_64, MEMSUFFIX) (void)
  903 +{
  904 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
  905 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
  906 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
  907 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
  908 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
  909 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
  910 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
  911 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
  912 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
  913 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
  914 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
  915 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
  916 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
  917 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
  918 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
  919 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
  920 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
  921 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
  922 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
  923 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
  924 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
  925 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
  926 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
  927 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
  928 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
  929 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
  930 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
  931 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
  932 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
  933 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
  934 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
  935 + glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
  936 + RETURN();
  937 +}
  938 +
  939 +void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
  940 +{
  941 + glue(do_dcbz_64, MEMSUFFIX)();
836 942 RETURN();
837 943 }
838 944 #endif
... ...
target-ppc/translate.c
  View file @d63001d
... ... @@ -169,6 +169,7 @@ typedef struct DisasContext {
169 169 #endif
170 170 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
171 171 int singlestep_enabled;
  172 + int dcache_line_size;
172 173 } DisasContext;
173 174  
174 175 struct opc_handler_t {
... ... @@ -482,6 +483,10 @@ enum {
482 483 PPC_WAIT = 0x0000100000000000ULL,
483 484 /* New 64 bits extensions (PowerPC 2.0x) */
484 485 PPC_64BX = 0x0000200000000000ULL,
  486 + /* dcbz instruction with fixed cache line size */
  487 + PPC_CACHE_DCBZ = 0x0000400000000000ULL,
  488 + /* dcbz instruction with tunable cache line size */
  489 + PPC_CACHE_DCBZT = 0x0000800000000000ULL,
485 490 };
486 491  
487 492 /*****************************************************************************/
... ... @@ -3623,51 +3628,178 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3623 3628 }
3624 3629  
3625 3630 /* dcbz */
3626   -#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
  3631 +#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3627 3632 #if defined(CONFIG_USER_ONLY)
3628 3633 /* User-mode only */
3629   -static GenOpFunc *gen_op_dcbz[] = {
3630   - &gen_op_dcbz_raw,
3631   - &gen_op_dcbz_raw,
  3634 +static GenOpFunc *gen_op_dcbz[4][4] = {
  3635 + {
  3636 + &gen_op_dcbz_l32_raw,
  3637 + &gen_op_dcbz_l32_raw,
3632 3638 #if defined(TARGET_PPC64)
3633   - &gen_op_dcbz_64_raw,
3634   - &gen_op_dcbz_64_raw,
  3639 + &gen_op_dcbz_l32_64_raw,
  3640 + &gen_op_dcbz_l32_64_raw,
3635 3641 #endif
  3642 + },
  3643 + {
  3644 + &gen_op_dcbz_l64_raw,
  3645 + &gen_op_dcbz_l64_raw,
  3646 +#if defined(TARGET_PPC64)
  3647 + &gen_op_dcbz_l64_64_raw,
  3648 + &gen_op_dcbz_l64_64_raw,
  3649 +#endif
  3650 + },
  3651 + {
  3652 + &gen_op_dcbz_l128_raw,
  3653 + &gen_op_dcbz_l128_raw,
  3654 +#if defined(TARGET_PPC64)
  3655 + &gen_op_dcbz_l128_64_raw,
  3656 + &gen_op_dcbz_l128_64_raw,
  3657 +#endif
  3658 + },
  3659 + {
  3660 + &gen_op_dcbz_raw,
  3661 + &gen_op_dcbz_raw,
  3662 +#if defined(TARGET_PPC64)
  3663 + &gen_op_dcbz_64_raw,
  3664 + &gen_op_dcbz_64_raw,
  3665 +#endif
  3666 + },
3636 3667 };
3637 3668 #else
3638 3669 #if defined(TARGET_PPC64)
3639 3670 /* Full system - 64 bits mode */
3640   -static GenOpFunc *gen_op_dcbz[] = {
3641   - &gen_op_dcbz_user,
3642   - &gen_op_dcbz_user,
3643   - &gen_op_dcbz_64_user,
3644   - &gen_op_dcbz_64_user,
3645   - &gen_op_dcbz_kernel,
3646   - &gen_op_dcbz_kernel,
3647   - &gen_op_dcbz_64_kernel,
3648   - &gen_op_dcbz_64_kernel,
  3671 +static GenOpFunc *gen_op_dcbz[4][12] = {
  3672 + {
  3673 + &gen_op_dcbz_l32_user,
  3674 + &gen_op_dcbz_l32_user,
  3675 + &gen_op_dcbz_l32_64_user,
  3676 + &gen_op_dcbz_l32_64_user,
  3677 + &gen_op_dcbz_l32_kernel,
  3678 + &gen_op_dcbz_l32_kernel,
  3679 + &gen_op_dcbz_l32_64_kernel,
  3680 + &gen_op_dcbz_l32_64_kernel,
  3681 +#if defined(TARGET_PPC64H)
  3682 + &gen_op_dcbz_l32_hypv,
  3683 + &gen_op_dcbz_l32_hypv,
  3684 + &gen_op_dcbz_l32_64_hypv,
  3685 + &gen_op_dcbz_l32_64_hypv,
  3686 +#endif
  3687 + },
  3688 + {
  3689 + &gen_op_dcbz_l64_user,
  3690 + &gen_op_dcbz_l64_user,
  3691 + &gen_op_dcbz_l64_64_user,
  3692 + &gen_op_dcbz_l64_64_user,
  3693 + &gen_op_dcbz_l64_kernel,
  3694 + &gen_op_dcbz_l64_kernel,
  3695 + &gen_op_dcbz_l64_64_kernel,
  3696 + &gen_op_dcbz_l64_64_kernel,
3649 3697 #if defined(TARGET_PPC64H)
3650   - &gen_op_dcbz_hypv,
3651   - &gen_op_dcbz_hypv,
3652   - &gen_op_dcbz_64_hypv,
3653   - &gen_op_dcbz_64_hypv,
  3698 + &gen_op_dcbz_l64_hypv,
  3699 + &gen_op_dcbz_l64_hypv,
  3700 + &gen_op_dcbz_l64_64_hypv,
  3701 + &gen_op_dcbz_l64_64_hypv,
  3702 +#endif
  3703 + },
  3704 + {
  3705 + &gen_op_dcbz_l128_user,
  3706 + &gen_op_dcbz_l128_user,
  3707 + &gen_op_dcbz_l128_64_user,
  3708 + &gen_op_dcbz_l128_64_user,
  3709 + &gen_op_dcbz_l128_kernel,
  3710 + &gen_op_dcbz_l128_kernel,
  3711 + &gen_op_dcbz_l128_64_kernel,
  3712 + &gen_op_dcbz_l128_64_kernel,
  3713 +#if defined(TARGET_PPC64H)
  3714 + &gen_op_dcbz_l128_hypv,
  3715 + &gen_op_dcbz_l128_hypv,
  3716 + &gen_op_dcbz_l128_64_hypv,
  3717 + &gen_op_dcbz_l128_64_hypv,
  3718 +#endif
  3719 + },
  3720 + {
  3721 + &gen_op_dcbz_user,
  3722 + &gen_op_dcbz_user,
  3723 + &gen_op_dcbz_64_user,
  3724 + &gen_op_dcbz_64_user,
  3725 + &gen_op_dcbz_kernel,
  3726 + &gen_op_dcbz_kernel,
  3727 + &gen_op_dcbz_64_kernel,
  3728 + &gen_op_dcbz_64_kernel,
  3729 +#if defined(TARGET_PPC64H)
  3730 + &gen_op_dcbz_hypv,
  3731 + &gen_op_dcbz_hypv,
  3732 + &gen_op_dcbz_64_hypv,
  3733 + &gen_op_dcbz_64_hypv,
3654 3734 #endif
  3735 + },
3655 3736 };
3656 3737 #else
3657 3738 /* Full system - 32 bits mode */
3658   -static GenOpFunc *gen_op_dcbz[] = {
3659   - &gen_op_dcbz_user,
3660   - &gen_op_dcbz_user,
3661   - &gen_op_dcbz_kernel,
3662   - &gen_op_dcbz_kernel,
  3739 +static GenOpFunc *gen_op_dcbz[4][4] = {
  3740 + {
  3741 + &gen_op_dcbz_l32_user,
  3742 + &gen_op_dcbz_l32_user,
  3743 + &gen_op_dcbz_l32_kernel,
  3744 + &gen_op_dcbz_l32_kernel,
  3745 + },
  3746 + {
  3747 + &gen_op_dcbz_l64_user,
  3748 + &gen_op_dcbz_l64_user,
  3749 + &gen_op_dcbz_l64_kernel,
  3750 + &gen_op_dcbz_l64_kernel,
  3751 + },
  3752 + {
  3753 + &gen_op_dcbz_l128_user,
  3754 + &gen_op_dcbz_l128_user,
  3755 + &gen_op_dcbz_l128_kernel,
  3756 + &gen_op_dcbz_l128_kernel,
  3757 + },
  3758 + {
  3759 + &gen_op_dcbz_user,
  3760 + &gen_op_dcbz_user,
  3761 + &gen_op_dcbz_kernel,
  3762 + &gen_op_dcbz_kernel,
  3763 + },
3663 3764 };
3664 3765 #endif
3665 3766 #endif
3666 3767  
3667   -GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
  3768 +static inline void handler_dcbz (DisasContext *ctx, int dcache_line_size)
  3769 +{
  3770 + int n;
  3771 +
  3772 + switch (dcache_line_size) {
  3773 + case 32:
  3774 + n = 0;
  3775 + break;
  3776 + case 64:
  3777 + n = 1;
  3778 + break;
  3779 + case 128:
  3780 + n = 2;
  3781 + break;
  3782 + default:
  3783 + n = 3;
  3784 + break;
  3785 + }
  3786 + op_dcbz(n);
  3787 +}
  3788 +
  3789 +GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3668 3790 {
3669 3791 gen_addr_reg_index(ctx);
3670   - op_dcbz();
  3792 + handler_dcbz(ctx, ctx->dcache_line_size);
  3793 + gen_op_check_reservation();
  3794 +}
  3795 +
  3796 +GEN_HANDLER(dcbz_970, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
  3797 +{
  3798 + gen_addr_reg_index(ctx);
  3799 + if (ctx->opcode & 0x00200000)
  3800 + handler_dcbz(ctx, ctx->dcache_line_size);
  3801 + else
  3802 + handler_dcbz(ctx, -1);
3671 3803 gen_op_check_reservation();
3672 3804 }
3673 3805  
... ... @@ -6341,6 +6473,7 @@ static inline int gen_intermediate_code_internal (CPUState *env,
6341 6473 #else
6342 6474 ctx.mem_idx = (supervisor << 1) | msr_le;
6343 6475 #endif
  6476 + ctx.dcache_line_size = env->dcache_line_size;
6344 6477 ctx.fpu_enabled = msr_fp;
6345 6478 #if defined(TARGET_PPCEMB)
6346 6479 ctx.spe_enabled = msr_spe;
... ...
target-ppc/translate_init.c
  View file @d63001d
... ... @@ -2542,7 +2542,7 @@ static void init_excp_970 (CPUPPCState *env)
2542 2542 /* PowerPC implementations definitions */
2543 2543  
2544 2544 /* PowerPC 40x instruction set */
2545   -#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
  2545 +#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2546 2546  
2547 2547 /* PowerPC 401 */
2548 2548 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
... ... @@ -2560,8 +2560,14 @@ static void init_proc_401 (CPUPPCState *env)
2560 2560 gen_spr_401_403(env);
2561 2561 gen_spr_401(env);
2562 2562 init_excp_4xx_real(env);
  2563 + env->dcache_line_size = 32;
  2564 + env->icache_line_size = 32;
2563 2565 /* Allocate hardware IRQ controller */
2564 2566 ppc40x_irq_init(env);
  2567 +#if !defined(CONFIG_USER_ONLY)
  2568 + /* Hardware reset vector */
  2569 + env->hreset_vector = 0xFFFFFFFCUL;
  2570 +#endif
2565 2571 }
2566 2572  
2567 2573 /* PowerPC 401x2 */
... ... @@ -2587,8 +2593,14 @@ static void init_proc_401x2 (CPUPPCState *env)
2587 2593 env->nb_ways = 1;
2588 2594 env->id_tlbs = 0;
2589 2595 init_excp_4xx_softmmu(env);
  2596 + env->dcache_line_size = 32;
  2597 + env->icache_line_size = 32;
2590 2598 /* Allocate hardware IRQ controller */
2591 2599 ppc40x_irq_init(env);
  2600 +#if !defined(CONFIG_USER_ONLY)
  2601 + /* Hardware reset vector */
  2602 + env->hreset_vector = 0xFFFFFFFCUL;
  2603 +#endif
2592 2604 }
2593 2605  
2594 2606 /* PowerPC 401x3 */
... ... @@ -2612,8 +2624,14 @@ static void init_proc_401x3 (CPUPPCState *env)
2612 2624 gen_spr_401x2(env);
2613 2625 gen_spr_compress(env);
2614 2626 init_excp_4xx_softmmu(env);
  2627 + env->dcache_line_size = 32;
  2628 + env->icache_line_size = 32;
2615 2629 /* Allocate hardware IRQ controller */
2616 2630 ppc40x_irq_init(env);
  2631 +#if !defined(CONFIG_USER_ONLY)
  2632 + /* Hardware reset vector */
  2633 + env->hreset_vector = 0xFFFFFFFCUL;
  2634 +#endif
2617 2635 }
2618 2636  
2619 2637 /* IOP480 */
... ... @@ -2639,8 +2657,14 @@ static void init_proc_IOP480 (CPUPPCState *env)
2639 2657 env->nb_ways = 1;
2640 2658 env->id_tlbs = 0;
2641 2659 init_excp_4xx_softmmu(env);
  2660 + env->dcache_line_size = 32;
  2661 + env->icache_line_size = 32;
2642 2662 /* Allocate hardware IRQ controller */
2643 2663 ppc40x_irq_init(env);
  2664 +#if !defined(CONFIG_USER_ONLY)
  2665 + /* Hardware reset vector */
  2666 + env->hreset_vector = 0xFFFFFFFCUL;
  2667 +#endif
2644 2668 }
2645 2669  
2646 2670 /* PowerPC 403 */
... ... @@ -2661,8 +2685,14 @@ static void init_proc_403 (CPUPPCState *env)
2661 2685 gen_spr_403(env);
2662 2686 gen_spr_403_real(env);
2663 2687 init_excp_4xx_real(env);
  2688 + env->dcache_line_size = 32;
  2689 + env->icache_line_size = 32;
2664 2690 /* Allocate hardware IRQ controller */
2665 2691 ppc40x_irq_init(env);
  2692 +#if !defined(CONFIG_USER_ONLY)
  2693 + /* Hardware reset vector */
  2694 + env->hreset_vector = 0xFFFFFFFCUL;
  2695 +#endif
2666 2696 }
2667 2697  
2668 2698 /* PowerPC 403 GCX */
... ... @@ -2699,8 +2729,14 @@ static void init_proc_403GCX (CPUPPCState *env)
2699 2729 env->nb_ways = 1;
2700 2730 env->id_tlbs = 0;
2701 2731 init_excp_4xx_softmmu(env);
  2732 + env->dcache_line_size = 32;
  2733 + env->icache_line_size = 32;
2702 2734 /* Allocate hardware IRQ controller */
2703 2735 ppc40x_irq_init(env);
  2736 +#if !defined(CONFIG_USER_ONLY)
  2737 + /* Hardware reset vector */
  2738 + env->hreset_vector = 0xFFFFFFFCUL;
  2739 +#endif
2704 2740 }
2705 2741  
2706 2742 /* PowerPC 405 */
... ... @@ -2737,8 +2773,14 @@ static void init_proc_405 (CPUPPCState *env)
2737 2773 env->nb_ways = 1;
2738 2774 env->id_tlbs = 0;
2739 2775 init_excp_4xx_softmmu(env);
  2776 + env->dcache_line_size = 32;
  2777 + env->icache_line_size = 32;
2740 2778 /* Allocate hardware IRQ controller */
2741 2779 ppc40x_irq_init(env);
  2780 +#if !defined(CONFIG_USER_ONLY)
  2781 + /* Hardware reset vector */
  2782 + env->hreset_vector = 0xFFFFFFFCUL;
  2783 +#endif
2742 2784 }
2743 2785  
2744 2786 /* PowerPC 440 EP */
... ... @@ -2781,7 +2823,13 @@ static void init_proc_440EP (CPUPPCState *env)
2781 2823 env->nb_ways = 1;
2782 2824 env->id_tlbs = 0;
2783 2825 init_excp_BookE(env);
  2826 + env->dcache_line_size = 32;
  2827 + env->icache_line_size = 32;
2784 2828 /* XXX: TODO: allocate internal IRQ controller */
  2829 +#if !defined(CONFIG_USER_ONLY)
  2830 + /* Hardware reset vector */
  2831 + env->hreset_vector = 0xFFFFFFFCUL;
  2832 +#endif
2785 2833 }
2786 2834  
2787 2835 /* PowerPC 440 GP */
... ... @@ -2806,7 +2854,13 @@ static void init_proc_440GP (CPUPPCState *env)
2806 2854 env->nb_ways = 1;
2807 2855 env->id_tlbs = 0;
2808 2856 init_excp_BookE(env);
  2857 + env->dcache_line_size = 32;
  2858 + env->icache_line_size = 32;
2809 2859 /* XXX: TODO: allocate internal IRQ controller */
  2860 +#if !defined(CONFIG_USER_ONLY)
  2861 + /* Hardware reset vector */
  2862 + env->hreset_vector = 0xFFFFFFFCUL;
  2863 +#endif
2810 2864 }
2811 2865  
2812 2866 /* PowerPC 440x4 */
... ... @@ -2832,7 +2886,13 @@ static void init_proc_440x4 (CPUPPCState *env)
2832 2886 env->nb_ways = 1;
2833 2887 env->id_tlbs = 0;
2834 2888 init_excp_BookE(env);
  2889 + env->dcache_line_size = 32;
  2890 + env->icache_line_size = 32;
2835 2891 /* XXX: TODO: allocate internal IRQ controller */
  2892 +#if !defined(CONFIG_USER_ONLY)
  2893 + /* Hardware reset vector */
  2894 + env->hreset_vector = 0xFFFFFFFCUL;
  2895 +#endif
2836 2896 }
2837 2897  
2838 2898 /* PowerPC 440x5 */
... ... @@ -2875,7 +2935,13 @@ static void init_proc_440x5 (CPUPPCState *env)
2875 2935 env->nb_ways = 1;
2876 2936 env->id_tlbs = 0;
2877 2937 init_excp_BookE(env);
  2938 + env->dcache_line_size = 32;
  2939 + env->icache_line_size = 32;
2878 2940 /* XXX: TODO: allocate internal IRQ controller */
  2941 +#if !defined(CONFIG_USER_ONLY)
  2942 + /* Hardware reset vector */
  2943 + env->hreset_vector = 0xFFFFFFFCUL;
  2944 +#endif
2879 2945 }
2880 2946  
2881 2947 /* PowerPC 460 (guessed) */
... ... @@ -2924,7 +2990,13 @@ static void init_proc_460 (CPUPPCState *env)
2924 2990 env->nb_ways = 1;
2925 2991 env->id_tlbs = 0;
2926 2992 init_excp_BookE(env);
  2993 + env->dcache_line_size = 32;
  2994 + env->icache_line_size = 32;
2927 2995 /* XXX: TODO: allocate internal IRQ controller */
  2996 +#if !defined(CONFIG_USER_ONLY)
  2997 + /* Hardware reset vector */
  2998 + env->hreset_vector = 0xFFFFFFFCUL;
  2999 +#endif
2928 3000 }
2929 3001  
2930 3002 /* PowerPC 460F (guessed) */
... ... @@ -2976,7 +3048,13 @@ static void init_proc_460F (CPUPPCState *env)
2976 3048 env->nb_ways = 1;
2977 3049 env->id_tlbs = 0;
2978 3050 init_excp_BookE(env);
  3051 + env->dcache_line_size = 32;
  3052 + env->icache_line_size = 32;
2979 3053 /* XXX: TODO: allocate internal IRQ controller */
  3054 +#if !defined(CONFIG_USER_ONLY)
  3055 + /* Hardware reset vector */
  3056 + env->hreset_vector = 0xFFFFFFFCUL;
  3057 +#endif
2980 3058 }
2981 3059  
2982 3060 /* Generic BookE PowerPC */
... ... @@ -2997,6 +3075,12 @@ __attribute__ (( unused ))
2997 3075 static void init_proc_BookE (CPUPPCState *env)
2998 3076 {
2999 3077 init_excp_BookE(env);
  3078 + env->dcache_line_size = 32;
  3079 + env->icache_line_size = 32;
  3080 +#if !defined(CONFIG_USER_ONLY)
  3081 + /* Hardware reset vector */
  3082 + env->hreset_vector = 0xFFFFFFFCUL;
  3083 +#endif
3000 3084 }
3001 3085  
3002 3086 /* e200 core */
... ... @@ -3025,7 +3109,13 @@ static void init_proc_e500 (CPUPPCState *env)
3025 3109 env->nb_ways = 1;
3026 3110 env->id_tlbs = 0;
3027 3111 init_excp_BookE(env);
  3112 + env->dcache_line_size = 32;
  3113 + env->icache_line_size = 32;
3028 3114 /* XXX: TODO: allocate internal IRQ controller */
  3115 +#if !defined(CONFIG_USER_ONLY)
  3116 + /* Hardware reset vector */
  3117 + env->hreset_vector = 0xFFFFFFFCUL;
  3118 +#endif
3029 3119 }
3030 3120  
3031 3121 /* e600 core */
... ... @@ -3038,7 +3128,7 @@ static void init_proc_e500 (CPUPPCState *env)
3038 3128 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3039 3129 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3040 3130 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3041   - PPC_MEM_TLBSYNC | PPC_MFTB)
  3131 + PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB)
3042 3132  
3043 3133 /* POWER : same as 601, without mfmsr, mfsr */
3044 3134 #if defined(TODO)
... ... @@ -3048,7 +3138,8 @@ static void init_proc_e500 (CPUPPCState *env)
3048 3138 #endif /* TODO */
3049 3139  
3050 3140 /* PowerPC 601 */
3051   -#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
  3141 +#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
  3142 + PPC_EXTERN | PPC_POWER_BR)
3052 3143 #define POWERPC_MSRM_601 (0x000000000000FE70ULL)
3053 3144 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3054 3145 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
... ... @@ -3091,14 +3182,21 @@ static void init_proc_601 (CPUPPCState *env)
3091 3182 env->id_tlbs = 0;
3092 3183 env->id_tlbs = 0;
3093 3184 init_excp_601(env);
  3185 + env->dcache_line_size = 64;
  3186 + env->icache_line_size = 64;
3094 3187 /* XXX: TODO: allocate internal IRQ controller */
  3188 +#if !defined(CONFIG_USER_ONLY)
  3189 + /* Hardware reset vector */
  3190 + env->hreset_vector = 0xFFFFFFFCUL;
  3191 +#endif
3095 3192 }
3096 3193  
3097 3194 /* PowerPC 602 */
3098 3195 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3099 3196 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3100 3197 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3101   - PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
  3198 + PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
  3199 + PPC_602_SPEC)
3102 3200 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3103 3201 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3104 3202 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
... ... @@ -3126,8 +3224,14 @@ static void init_proc_602 (CPUPPCState *env)
3126 3224 gen_low_BATs(env);
3127 3225 gen_6xx_7xx_soft_tlb(env, 64, 2);
3128 3226 init_excp_602(env);
  3227 + env->dcache_line_size = 32;
  3228 + env->icache_line_size = 32;
3129 3229 /* Allocate hardware IRQ controller */
3130 3230 ppc6xx_irq_init(env);
  3231 +#if !defined(CONFIG_USER_ONLY)
  3232 + /* Hardware reset vector */
  3233 + env->hreset_vector = 0xFFFFFFFCUL;
  3234 +#endif
3131 3235 }
3132 3236  
3133 3237 /* PowerPC 603 */
... ... @@ -3159,8 +3263,14 @@ static void init_proc_603 (CPUPPCState *env)
3159 3263 gen_low_BATs(env);
3160 3264 gen_6xx_7xx_soft_tlb(env, 64, 2);
3161 3265 init_excp_603(env);
  3266 + env->dcache_line_size = 32;
  3267 + env->icache_line_size = 32;
3162 3268 /* Allocate hardware IRQ controller */
3163 3269 ppc6xx_irq_init(env);
  3270 +#if !defined(CONFIG_USER_ONLY)
  3271 + /* Hardware reset vector */
  3272 + env->hreset_vector = 0xFFFFFFFCUL;
  3273 +#endif
3164 3274 }
3165 3275  
3166 3276 /* PowerPC 603e */
... ... @@ -3197,8 +3307,14 @@ static void init_proc_603E (CPUPPCState *env)
3197 3307 gen_low_BATs(env);
3198 3308 gen_6xx_7xx_soft_tlb(env, 64, 2);
3199 3309 init_excp_603(env);
  3310 + env->dcache_line_size = 32;
  3311 + env->icache_line_size = 32;
3200 3312 /* Allocate hardware IRQ controller */
3201 3313 ppc6xx_irq_init(env);
  3314 +#if !defined(CONFIG_USER_ONLY)
  3315 + /* Hardware reset vector */
  3316 + env->hreset_vector = 0xFFFFFFFCUL;
  3317 +#endif
3202 3318 }
3203 3319  
3204 3320 /* PowerPC G2 */
... ... @@ -3237,8 +3353,14 @@ static void init_proc_G2 (CPUPPCState *env)
3237 3353 gen_high_BATs(env);
3238 3354 gen_6xx_7xx_soft_tlb(env, 64, 2);
3239 3355 init_excp_G2(env);
  3356 + env->dcache_line_size = 32;
  3357 + env->icache_line_size = 32;
3240 3358 /* Allocate hardware IRQ controller */
3241 3359 ppc6xx_irq_init(env);
  3360 +#if !defined(CONFIG_USER_ONLY)
  3361 + /* Hardware reset vector */
  3362 + env->hreset_vector = 0xFFFFFFFCUL;
  3363 +#endif
3242 3364 }
3243 3365  
3244 3366 /* PowerPC G2LE */
... ... @@ -3277,8 +3399,14 @@ static void init_proc_G2LE (CPUPPCState *env)
3277 3399 gen_high_BATs(env);
3278 3400 gen_6xx_7xx_soft_tlb(env, 64, 2);
3279 3401 init_excp_G2(env);
  3402 + env->dcache_line_size = 32;
  3403 + env->icache_line_size = 32;
3280 3404 /* Allocate hardware IRQ controller */
3281 3405 ppc6xx_irq_init(env);
  3406 +#if !defined(CONFIG_USER_ONLY)
  3407 + /* Hardware reset vector */
  3408 + env->hreset_vector = 0xFFFFFFFCUL;
  3409 +#endif
3282 3410 }
3283 3411  
3284 3412 /* PowerPC 604 */
... ... @@ -3309,8 +3437,14 @@ static void init_proc_604 (CPUPPCState *env)
3309 3437 /* Memory management */
3310 3438 gen_low_BATs(env);
3311 3439 init_excp_604(env);
  3440 + env->dcache_line_size = 32;
  3441 + env->icache_line_size = 32;
3312 3442 /* Allocate hardware IRQ controller */
3313 3443 ppc6xx_irq_init(env);
  3444 +#if !defined(CONFIG_USER_ONLY)
  3445 + /* Hardware reset vector */
  3446 + env->hreset_vector = 0xFFFFFFFCUL;
  3447 +#endif
3314 3448 }
3315 3449  
3316 3450 /* PowerPC 740/750 (aka G3) */
... ... @@ -3343,8 +3477,14 @@ static void init_proc_7x0 (CPUPPCState *env)
3343 3477 /* Memory management */
3344 3478 gen_low_BATs(env);
3345 3479 init_excp_7x0(env);
  3480 + env->dcache_line_size = 32;
  3481 + env->icache_line_size = 32;
3346 3482 /* Allocate hardware IRQ controller */
3347 3483 ppc6xx_irq_init(env);
  3484 +#if !defined(CONFIG_USER_ONLY)
  3485 + /* Hardware reset vector */
  3486 + env->hreset_vector = 0xFFFFFFFCUL;
  3487 +#endif
3348 3488 }
3349 3489  
3350 3490 /* PowerPC 750FX/GX */
... ... @@ -3384,8 +3524,14 @@ static void init_proc_750fx (CPUPPCState *env)
3384 3524 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3385 3525 gen_high_BATs(env);
3386 3526 init_excp_750FX(env);
  3527 + env->dcache_line_size = 32;
  3528 + env->icache_line_size = 32;
3387 3529 /* Allocate hardware IRQ controller */
3388 3530 ppc6xx_irq_init(env);
  3531 +#if !defined(CONFIG_USER_ONLY)
  3532 + /* Hardware reset vector */
  3533 + env->hreset_vector = 0xFFFFFFFCUL;
  3534 +#endif
3389 3535 }
3390 3536  
3391 3537 /* PowerPC 745/755 */
... ... @@ -3433,8 +3579,14 @@ static void init_proc_7x5 (CPUPPCState *env)
3433 3579 gen_low_BATs(env);
3434 3580 gen_high_BATs(env);
3435 3581 gen_6xx_7xx_soft_tlb(env, 64, 2);
  3582 + env->dcache_line_size = 32;
  3583 + env->icache_line_size = 32;
3436 3584 /* Allocate hardware IRQ controller */
3437 3585 ppc6xx_irq_init(env);
  3586 +#if !defined(CONFIG_USER_ONLY)
  3587 + /* Hardware reset vector */
  3588 + env->hreset_vector = 0xFFFFFFFCUL;
  3589 +#endif
3438 3590 }
3439 3591  
3440 3592 /* PowerPC 7400 (aka G4) */
... ... @@ -3460,8 +3612,14 @@ static void init_proc_7400 (CPUPPCState *env)
3460 3612 /* Memory management */
3461 3613 gen_low_BATs(env);
3462 3614 init_excp_7400(env);
  3615 + env->dcache_line_size = 32;
  3616 + env->icache_line_size = 32;
3463 3617 /* Allocate hardware IRQ controller */
3464 3618 ppc6xx_irq_init(env);
  3619 +#if !defined(CONFIG_USER_ONLY)
  3620 + /* Hardware reset vector */
  3621 + env->hreset_vector = 0xFFFFFFFCUL;
  3622 +#endif
3465 3623 }
3466 3624  
3467 3625 /* PowerPC 7410 (aka G4) */
... ... @@ -3499,8 +3657,14 @@ static void init_proc_7410 (CPUPPCState *env)
3499 3657 /* Memory management */
3500 3658 gen_low_BATs(env);
3501 3659 init_excp_7400(env);
  3660 + env->dcache_line_size = 32;
  3661 + env->icache_line_size = 32;
3502 3662 /* Allocate hardware IRQ controller */
3503 3663 ppc6xx_irq_init(env);
  3664 +#if !defined(CONFIG_USER_ONLY)
  3665 + /* Hardware reset vector */
  3666 + env->hreset_vector = 0xFFFFFFFCUL;
  3667 +#endif
3504 3668 }
3505 3669  
3506 3670 /* PowerPC 7440 (aka G4) */
... ... @@ -3564,8 +3728,14 @@ static void init_proc_7440 (CPUPPCState *env)
3564 3728 /* Memory management */
3565 3729 gen_low_BATs(env);
3566 3730 gen_74xx_soft_tlb(env, 128, 2);
  3731 + env->dcache_line_size = 32;
  3732 + env->icache_line_size = 32;
3567 3733 /* Allocate hardware IRQ controller */
3568 3734 ppc6xx_irq_init(env);
  3735 +#if !defined(CONFIG_USER_ONLY)
  3736 + /* Hardware reset vector */
  3737 + env->hreset_vector = 0xFFFFFFFCUL;
  3738 +#endif
3569 3739 }
3570 3740  
3571 3741 /* PowerPC 7450 (aka G4) */
... ... @@ -3632,8 +3802,14 @@ static void init_proc_7450 (CPUPPCState *env)
3632 3802 gen_low_BATs(env);
3633 3803 gen_74xx_soft_tlb(env, 128, 2);
3634 3804 init_excp_7450(env);
  3805 + env->dcache_line_size = 32;
  3806 + env->icache_line_size = 32;
3635 3807 /* Allocate hardware IRQ controller */
3636 3808 ppc6xx_irq_init(env);
  3809 +#if !defined(CONFIG_USER_ONLY)
  3810 + /* Hardware reset vector */
  3811 + env->hreset_vector = 0xFFFFFFFCUL;
  3812 +#endif
3637 3813 }
3638 3814  
3639 3815 /* PowerPC 7445 (aka G4) */
... ... @@ -3732,8 +3908,14 @@ static void init_proc_7445 (CPUPPCState *env)
3732 3908 gen_high_BATs(env);
3733 3909 gen_74xx_soft_tlb(env, 128, 2);
3734 3910 init_excp_7450(env);
  3911 + env->dcache_line_size = 32;
  3912 + env->icache_line_size = 32;
3735 3913 /* Allocate hardware IRQ controller */
3736 3914 ppc6xx_irq_init(env);
  3915 +#if !defined(CONFIG_USER_ONLY)
  3916 + /* Hardware reset vector */
  3917 + env->hreset_vector = 0xFFFFFFFCUL;
  3918 +#endif
3737 3919 }
3738 3920  
3739 3921 /* PowerPC 7455 (aka G4) */
... ... @@ -3834,13 +4016,23 @@ static void init_proc_7455 (CPUPPCState *env)
3834 4016 gen_high_BATs(env);
3835 4017 gen_74xx_soft_tlb(env, 128, 2);
3836 4018 init_excp_7450(env);
  4019 + env->dcache_line_size = 32;
  4020 + env->icache_line_size = 32;
3837 4021 /* Allocate hardware IRQ controller */
3838 4022 ppc6xx_irq_init(env);
  4023 +#if !defined(CONFIG_USER_ONLY)
  4024 + /* Hardware reset vector */
  4025 + env->hreset_vector = 0xFFFFFFFCUL;
  4026 +#endif
3839 4027 }
3840 4028  
3841 4029 #if defined (TARGET_PPC64)
  4030 +#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
  4031 + PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
  4032 + PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
  4033 + PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
3842 4034 /* PowerPC 970 */
3843   -#define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
  4035 +#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
3844 4036 PPC_64B | PPC_ALTIVEC | \
3845 4037 PPC_64_BRIDGE | PPC_SLBI)
3846 4038 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
... ... @@ -3860,7 +4052,7 @@ static void init_proc_970 (CPUPPCState *env)
3860 4052 spr_register(env, SPR_HID0, "HID0",
3861 4053 SPR_NOACCESS, SPR_NOACCESS,
3862 4054 &spr_read_generic, &spr_write_clear,
3863   - 0x00000000);
  4055 + 0x60000000);
3864 4056 /* XXX : not implemented */
3865 4057 spr_register(env, SPR_HID1, "HID1",
3866 4058 SPR_NOACCESS, SPR_NOACCESS,
... ... @@ -3878,12 +4070,18 @@ static void init_proc_970 (CPUPPCState *env)
3878 4070 env->slb_nr = 32;
3879 4071 #endif
3880 4072 init_excp_970(env);
  4073 + env->dcache_line_size = 128;
  4074 + env->icache_line_size = 128;
3881 4075 /* Allocate hardware IRQ controller */
3882 4076 ppc970_irq_init(env);
  4077 +#if !defined(CONFIG_USER_ONLY)
  4078 + /* Hardware reset vector */
  4079 + env->hreset_vector = 0x0000000000000100ULL;
  4080 +#endif
3883 4081 }
3884 4082  
3885 4083 /* PowerPC 970FX (aka G5) */
3886   -#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
  4084 +#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
3887 4085 PPC_64B | PPC_ALTIVEC | \
3888 4086 PPC_64_BRIDGE | PPC_SLBI)
3889 4087 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
... ... @@ -3903,7 +4101,7 @@ static void init_proc_970FX (CPUPPCState *env)
3903 4101 spr_register(env, SPR_HID0, "HID0",
3904 4102 SPR_NOACCESS, SPR_NOACCESS,
3905 4103 &spr_read_generic, &spr_write_clear,
3906   - 0x00000000);
  4104 + 0x60000000);
3907 4105 /* XXX : not implemented */
3908 4106 spr_register(env, SPR_HID1, "HID1",
3909 4107 SPR_NOACCESS, SPR_NOACCESS,
... ... @@ -3914,6 +4112,11 @@ static void init_proc_970FX (CPUPPCState *env)
3914 4112 SPR_NOACCESS, SPR_NOACCESS,
3915 4113 &spr_read_generic, &spr_write_generic,
3916 4114 0x00000000);
  4115 + /* XXX : not implemented */
  4116 + spr_register(env, SPR_970_HID5, "HID5",
  4117 + SPR_NOACCESS, SPR_NOACCESS,
  4118 + &spr_read_generic, &spr_write_generic,
  4119 + 0x00000000);
3917 4120 /* Memory management */
3918 4121 /* XXX: not correct */
3919 4122 gen_low_BATs(env);
... ... @@ -3921,12 +4124,18 @@ static void init_proc_970FX (CPUPPCState *env)
3921 4124 env->slb_nr = 32;
3922 4125 #endif
3923 4126 init_excp_970(env);
  4127 + env->dcache_line_size = 128;
  4128 + env->icache_line_size = 128;
3924 4129 /* Allocate hardware IRQ controller */
3925 4130 ppc970_irq_init(env);
  4131 +#if !defined(CONFIG_USER_ONLY)
  4132 + /* Hardware reset vector */
  4133 + env->hreset_vector = 0x0000000000000100ULL;
  4134 +#endif
3926 4135 }
3927 4136  
3928 4137 /* PowerPC 970 GX */
3929   -#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
  4138 +#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
3930 4139 PPC_64B | PPC_ALTIVEC | \
3931 4140 PPC_64_BRIDGE | PPC_SLBI)
3932 4141 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
... ... @@ -3946,7 +4155,7 @@ static void init_proc_970GX (CPUPPCState *env)
3946 4155 spr_register(env, SPR_HID0, "HID0",
3947 4156 SPR_NOACCESS, SPR_NOACCESS,
3948 4157 &spr_read_generic, &spr_write_clear,
3949   - 0x00000000);
  4158 + 0x60000000);
3950 4159 /* XXX : not implemented */
3951 4160 spr_register(env, SPR_HID1, "HID1",
3952 4161 SPR_NOACCESS, SPR_NOACCESS,
... ... @@ -3957,6 +4166,11 @@ static void init_proc_970GX (CPUPPCState *env)
3957 4166 SPR_NOACCESS, SPR_NOACCESS,
3958 4167 &spr_read_generic, &spr_write_generic,
3959 4168 0x00000000);
  4169 + /* XXX : not implemented */
  4170 + spr_register(env, SPR_970_HID5, "HID5",
  4171 + SPR_NOACCESS, SPR_NOACCESS,
  4172 + &spr_read_generic, &spr_write_generic,
  4173 + 0x00000000);
3960 4174 /* Memory management */
3961 4175 /* XXX: not correct */
3962 4176 gen_low_BATs(env);
... ... @@ -3964,8 +4178,14 @@ static void init_proc_970GX (CPUPPCState *env)
3964 4178 env->slb_nr = 32;
3965 4179 #endif
3966 4180 init_excp_970(env);
  4181 + env->dcache_line_size = 128;
  4182 + env->icache_line_size = 128;
3967 4183 /* Allocate hardware IRQ controller */
3968 4184 ppc970_irq_init(env);
  4185 +#if !defined(CONFIG_USER_ONLY)
  4186 + /* Hardware reset vector */
  4187 + env->hreset_vector = 0x0000000000000100ULL;
  4188 +#endif
3969 4189 }
3970 4190  
3971 4191 /* PowerPC 620 */
... ... @@ -3994,7 +4214,13 @@ static void init_proc_620 (CPUPPCState *env)
3994 4214 gen_low_BATs(env);
3995 4215 gen_high_BATs(env);
3996 4216 init_excp_620(env);
  4217 + env->dcache_line_size = 64;
  4218 + env->icache_line_size = 64;
3997 4219 /* XXX: TODO: initialize internal interrupt controller */
  4220 +#if !defined(CONFIG_USER_ONLY)
  4221 + /* Hardware reset vector */
  4222 + env->hreset_vector = 0x0000000000000100ULL; /* ? */
  4223 +#endif
3998 4224 }
3999 4225 #endif /* defined (TARGET_PPC64) */
4000 4226  
... ...