gwj / at91sam9263 · Commits

Commit d60532ca8f551d226b2a1cab46fb4d6611ee0ea8

Authored by ths
1 parent 630530a6

Add parallel memory mapped interface, by Herve Poussineau. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2988 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 95 additions and 13 deletions
hw/mips_pica61.c
  View file @d60532c
... ... @@ -151,11 +151,8 @@ void mips_pica61_init (int ram_size, int vga_ram_size, int boot_device,
151 151 serial_mm_init(serial_base[i], 0, i8259[serial_irq[i]], serial_hds[i], 1);
152 152 }
153 153 }
154   - for (i = 0; i < MAX_PARALLEL_PORTS; i++) {
155   - if (parallel_hds[i]) {
156   - /* FIXME: memory mapped! parallel_init(0x80008000, i8259[17], parallel_hds[i]); */
157   - }
158   - }
  154 + /* Parallel port */
  155 + if (parallel_hds[0]) parallel_mm_init(0x80008000, 0, i8259[1], parallel_hds[0]);
159 156  
160 157 /* Sound card */
161 158 /* FIXME: missing Jazz sound, IRQ 18 */
... ...
hw/parallel.c
  View file @d60532c
... ... @@ -71,6 +71,9 @@ struct ParallelState {
71 71 int hw_driver;
72 72 int epp_timeout;
73 73 uint32_t last_read_offset; /* For debugging */
  74 + /* Memory-mapped interface */
  75 + target_phys_addr_t base;
  76 + int it_shift;
74 77 };
75 78  
76 79 static void parallel_update_irq(ParallelState *s)
... ... @@ -400,15 +403,8 @@ static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
400 403 return ret;
401 404 }
402 405  
403   -/* If fd is zero, it means that the parallel device uses the console */
404   -ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
  406 +static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
405 407 {
406   - ParallelState *s;
407   - uint8_t dummy;
408   -
409   - s = qemu_mallocz(sizeof(ParallelState));
410   - if (!s)
411   - return NULL;
412 408 s->datar = ~0;
413 409 s->dataw = ~0;
414 410 s->status = PARA_STS_BUSY;
... ... @@ -423,6 +419,18 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
423 419 s->hw_driver = 0;
424 420 s->epp_timeout = 0;
425 421 s->last_read_offset = ~0U;
  422 +}
  423 +
  424 +/* If fd is zero, it means that the parallel device uses the console */
  425 +ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
  426 +{
  427 + ParallelState *s;
  428 + uint8_t dummy;
  429 +
  430 + s = qemu_mallocz(sizeof(ParallelState));
  431 + if (!s)
  432 + return NULL;
  433 + parallel_reset(s, irq, chr);
426 434  
427 435 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
428 436 s->hw_driver = 1;
... ... @@ -445,3 +453,79 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
445 453 }
446 454 return s;
447 455 }
  456 +
  457 +/* Memory mapped interface */
  458 +uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
  459 +{
  460 + ParallelState *s = opaque;
  461 +
  462 + return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
  463 +}
  464 +
  465 +void parallel_mm_writeb (void *opaque,
  466 + target_phys_addr_t addr, uint32_t value)
  467 +{
  468 + ParallelState *s = opaque;
  469 +
  470 + parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
  471 +}
  472 +
  473 +uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
  474 +{
  475 + ParallelState *s = opaque;
  476 +
  477 + return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
  478 +}
  479 +
  480 +void parallel_mm_writew (void *opaque,
  481 + target_phys_addr_t addr, uint32_t value)
  482 +{
  483 + ParallelState *s = opaque;
  484 +
  485 + parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
  486 +}
  487 +
  488 +uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
  489 +{
  490 + ParallelState *s = opaque;
  491 +
  492 + return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
  493 +}
  494 +
  495 +void parallel_mm_writel (void *opaque,
  496 + target_phys_addr_t addr, uint32_t value)
  497 +{
  498 + ParallelState *s = opaque;
  499 +
  500 + parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
  501 +}
  502 +
  503 +static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
  504 + &parallel_mm_readb,
  505 + &parallel_mm_readw,
  506 + &parallel_mm_readl,
  507 +};
  508 +
  509 +static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
  510 + &parallel_mm_writeb,
  511 + &parallel_mm_writew,
  512 + &parallel_mm_writel,
  513 +};
  514 +
  515 +/* If fd is zero, it means that the parallel device uses the console */
  516 +ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
  517 +{
  518 + ParallelState *s;
  519 + int io_sw;
  520 +
  521 + s = qemu_mallocz(sizeof(ParallelState));
  522 + if (!s)
  523 + return NULL;
  524 + parallel_reset(s, irq, chr);
  525 + s->base = base;
  526 + s->it_shift = it_shift;
  527 +
  528 + io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
  529 + cpu_register_physical_memory(base, 8 << it_shift, io_sw);
  530 + return s;
  531 +}
... ...
... ... @@ -1089,6 +1089,7 @@ void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1089 1089  
1090 1090 typedef struct ParallelState ParallelState;
1091 1091 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
  1092 +ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1092 1093  
1093 1094 /* i8259.c */
1094 1095  
... ...