gwj / at91sam9263 · Commits

Commit d4a9eb1fc6fff9346963ef67629d1b232f01789c

Authored by blueswir1
1 parent d9b630fd

Add some missing static and const qualifiers, reg_names only used if NDEBUG set 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 7 changed files with 32 additions and 15 deletions
tcg/arm/tcg-target.c
  View file @d4a9eb1
... ... @@ -21,7 +21,9 @@
21 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 22 * THE SOFTWARE.
23 23 */
24   -const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  24 +
  25 +#ifndef NDEBUG
  26 +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
25 27 "%r0",
26 28 "%r1",
27 29 "%r2",
... ... @@ -38,8 +40,9 @@ const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
38 40 "%r13",
39 41 "%r14",
40 42 };
  43 +#endif
41 44  
42   -int tcg_target_reg_alloc_order[] = {
  45 +static const int tcg_target_reg_alloc_order[] = {
43 46 TCG_REG_R0,
44 47 TCG_REG_R1,
45 48 TCG_REG_R2,
... ... @@ -57,10 +60,10 @@ int tcg_target_reg_alloc_order[] = {
57 60 TCG_REG_R14,
58 61 };
59 62  
60   -const int tcg_target_call_iarg_regs[4] = {
  63 +static const int tcg_target_call_iarg_regs[4] = {
61 64 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
62 65 };
63   -const int tcg_target_call_oarg_regs[2] = {
  66 +static const int tcg_target_call_oarg_regs[2] = {
64 67 TCG_REG_R0, TCG_REG_R1
65 68 };
66 69  
... ... @@ -91,7 +94,7 @@ static inline int tcg_target_get_call_iarg_regs_count(int flags)
91 94 }
92 95  
93 96 /* parse target specific constraints */
94   -int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
  97 +static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
95 98 {
96 99 const char *ct_str;
97 100  
... ...
tcg/hppa/tcg-target.c
  View file @d4a9eb1
... ... @@ -22,6 +22,7 @@
22 22 * THE SOFTWARE.
23 23 */
24 24  
  25 +#ifndef NDEBUG
25 26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
26 27 "%r0",
27 28 "%r1",
... ... @@ -56,6 +57,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
56 57 "%sp",
57 58 "%r31",
58 59 };
  60 +#endif
59 61  
60 62 static const int tcg_target_reg_alloc_order[] = {
61 63 TCG_REG_R4,
... ... @@ -106,7 +108,7 @@ static inline int tcg_target_get_call_iarg_regs_count(int flags)
106 108 }
107 109  
108 110 /* parse target specific constraints */
109   -int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
  111 +static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
110 112 {
111 113 const char *ct_str;
112 114  
... ...
tcg/i386/tcg-target.c
  View file @d4a9eb1
... ... @@ -21,7 +21,9 @@
21 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 22 * THE SOFTWARE.
23 23 */
24   -const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  24 +
  25 +#ifndef NDEBUG
  26 +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
25 27 "%eax",
26 28 "%ecx",
27 29 "%edx",
... ... @@ -31,8 +33,9 @@ const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
31 33 "%esi",
32 34 "%edi",
33 35 };
  36 +#endif
34 37  
35   -int tcg_target_reg_alloc_order[] = {
  38 +static const int tcg_target_reg_alloc_order[] = {
36 39 TCG_REG_EAX,
37 40 TCG_REG_EDX,
38 41 TCG_REG_ECX,
... ... @@ -42,8 +45,8 @@ int tcg_target_reg_alloc_order[] = {
42 45 TCG_REG_EBP,
43 46 };
44 47  
45   -const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
46   -const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
  48 +static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
  49 +static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
47 50  
48 51 static uint8_t *tb_ret_addr;
49 52  
... ... @@ -80,7 +83,7 @@ static inline int tcg_target_get_call_iarg_regs_count(int flags)
80 83 }
81 84  
82 85 /* parse target specific constraints */
83   -int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
  86 +static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
84 87 {
85 88 const char *ct_str;
86 89  
... ...
tcg/ppc/tcg-target.c
  View file @d4a9eb1
... ... @@ -39,6 +39,7 @@ static uint8_t *tb_ret_addr;
39 39 #define ADDEND_OFFSET 4
40 40 #endif
41 41  
  42 +#ifndef NDEBUG
42 43 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
43 44 "r0",
44 45 "r1",
... ... @@ -73,6 +74,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
73 74 "r30",
74 75 "r31"
75 76 };
  77 +#endif
76 78  
77 79 static const int tcg_target_reg_alloc_order[] = {
78 80 TCG_REG_R14,
... ...
tcg/ppc64/tcg-target.c
  View file @d4a9eb1
... ... @@ -42,6 +42,7 @@ static uint8_t *tb_ret_addr;
42 42 #define CMP_L (1<<21)
43 43 #endif
44 44  
  45 +#ifndef NDEBUG
45 46 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 47 "r0",
47 48 "r1",
... ... @@ -76,6 +77,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
76 77 "r30",
77 78 "r31"
78 79 };
  80 +#endif
79 81  
80 82 static const int tcg_target_reg_alloc_order[] = {
81 83 TCG_REG_R14,
... ...
tcg/sparc/tcg-target.c
  View file @d4a9eb1
... ... @@ -22,6 +22,7 @@
22 22 * THE SOFTWARE.
23 23 */
24 24  
  25 +#ifndef NDEBUG
25 26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
26 27 "%g0",
27 28 "%g1",
... ... @@ -56,6 +57,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
56 57 "%i6",
57 58 "%i7",
58 59 };
  60 +#endif
59 61  
60 62 static const int tcg_target_reg_alloc_order[] = {
61 63 TCG_REG_L0,
... ...
tcg/x86_64/tcg-target.c
  View file @d4a9eb1
... ... @@ -21,7 +21,9 @@
21 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 22 * THE SOFTWARE.
23 23 */
24   -const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  24 +
  25 +#ifndef NDEBUG
  26 +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
25 27 "%rax",
26 28 "%rcx",
27 29 "%rdx",
... ... @@ -39,8 +41,9 @@ const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
39 41 "%r14",
40 42 "%r15",
41 43 };
  44 +#endif
42 45  
43   -int tcg_target_reg_alloc_order[] = {
  46 +static const int tcg_target_reg_alloc_order[] = {
44 47 TCG_REG_RDI,
45 48 TCG_REG_RSI,
46 49 TCG_REG_RDX,
... ... @@ -59,7 +62,7 @@ int tcg_target_reg_alloc_order[] = {
59 62 TCG_REG_R15,
60 63 };
61 64  
62   -const int tcg_target_call_iarg_regs[6] = {
  65 +static const int tcg_target_call_iarg_regs[6] = {
63 66 TCG_REG_RDI,
64 67 TCG_REG_RSI,
65 68 TCG_REG_RDX,
... ... @@ -68,7 +71,7 @@ const int tcg_target_call_iarg_regs[6] = {
68 71 TCG_REG_R9,
69 72 };
70 73  
71   -const int tcg_target_call_oarg_regs[2] = {
  74 +static const int tcg_target_call_oarg_regs[2] = {
72 75 TCG_REG_RAX,
73 76 TCG_REG_RDX
74 77 };
... ...