gwj / at91sam9263 · Commits

Commit d34defbc216cb3ebb2faa73df32841faf1bf45ca

Authored by aurel32
1 parent 2fbc4095

target-ppc: add support for reading/writing spefscr 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 23 additions and 8 deletions
target-ppc/translate_init.c
  View file @d34defb
... ... @@ -448,6 +448,23 @@ static void spr_write_pir (void *opaque, int sprn, int gprn)
448 448 }
449 449 #endif
450 450  
  451 +/* SPE specific registers */
  452 +static void spr_read_spefscr (void *opaque, int gprn, int sprn)
  453 +{
  454 + TCGv_i32 t0 = tcg_temp_new_i32();
  455 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spe_fscr));
  456 + tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
  457 + tcg_temp_free_i32(t0);
  458 +}
  459 +
  460 +static void spr_write_spefscr (void *opaque, int sprn, int gprn)
  461 +{
  462 + TCGv_i32 t0 = tcg_temp_new_i32();
  463 + tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
  464 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spe_fscr));
  465 + tcg_temp_free_i32(t0);
  466 +}
  467 +
451 468 #if !defined(CONFIG_USER_ONLY)
452 469 /* Callback used to write the exception vector base */
453 470 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
... ... @@ -2565,7 +2582,6 @@ static void gen_spr_8xx (CPUPPCState *env)
2565 2582 * HSRR1 => SPR 315 (Power 2.04 hypv)
2566 2583 * LPCR => SPR 316 (970)
2567 2584 * LPIDR => SPR 317 (970)
2568   - * SPEFSCR => SPR 512 (Power 2.04 emb)
2569 2585 * EPR => SPR 702 (Power 2.04 emb)
2570 2586 * perf => 768-783 (Power 2.04)
2571 2587 * perf => 784-799 (Power 2.04)
... ... @@ -4021,8 +4037,8 @@ static void init_proc_e200 (CPUPPCState *env)
4021 4037 gen_spr_BookE(env, 0x000000070000FFFFULL);
4022 4038 /* XXX : not implemented */
4023 4039 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4024   - SPR_NOACCESS, SPR_NOACCESS,
4025   - &spr_read_generic, &spr_write_generic,
  4040 + &spr_read_spefscr, &spr_write_spefscr,
  4041 + &spr_read_spefscr, &spr_write_spefscr,
4026 4042 0x00000000);
4027 4043 /* Memory management */
4028 4044 gen_spr_BookE_FSL(env, 0x0000005D);
... ... @@ -4210,8 +4226,8 @@ static void init_proc_e500 (CPUPPCState *env)
4210 4226 0x00000000);
4211 4227 /* XXX : not implemented */
4212 4228 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4213   - SPR_NOACCESS, SPR_NOACCESS,
4214   - &spr_read_generic, &spr_write_generic,
  4229 + &spr_read_spefscr, &spr_write_spefscr,
  4230 + &spr_read_spefscr, &spr_write_spefscr,
4215 4231 0x00000000);
4216 4232 /* Memory management */
4217 4233 #if !defined(CONFIG_USER_ONLY)
... ... @@ -9428,8 +9444,7 @@ static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9428 9444 return 8;
9429 9445 }
9430 9446 if (n == 33) {
9431   - /* SPEFSCR not implemented */
9432   - memset(mem_buf, 0, 4);
  9447 + stl_p(mem_buf, env->spe_fscr);
9433 9448 return 4;
9434 9449 }
9435 9450 return 0;
... ... @@ -9452,7 +9467,7 @@ static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9452 9467 return 8;
9453 9468 }
9454 9469 if (n == 33) {
9455   - /* SPEFSCR not implemented */
  9470 + env->spe_fscr = ldl_p(mem_buf);
9456 9471 return 4;
9457 9472 }
9458 9473 return 0;
... ...