Commit d2c38b24d1d9b0b94137b7190f80fd4d0f4a0fb1
1 parent
d5296cb5
Name the magic constants, wrap long lines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3757 c046a42c-6fe2-441c-8c8c-71466251a162
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62 additions
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38 deletions
hw/slavio_timer.c
@@ -69,6 +69,24 @@ typedef struct SLAVIO_TIMERState { | @@ -69,6 +69,24 @@ typedef struct SLAVIO_TIMERState { | ||
69 | #define SYS_TIMER_SIZE 0x14 | 69 | #define SYS_TIMER_SIZE 0x14 |
70 | #define CPU_TIMER_SIZE 0x10 | 70 | #define CPU_TIMER_SIZE 0x10 |
71 | 71 | ||
72 | +#define SYS_TIMER_OFFSET 0x10000ULL | ||
73 | +#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) | ||
74 | + | ||
75 | +#define TIMER_LIMIT 0 | ||
76 | +#define TIMER_COUNTER 1 | ||
77 | +#define TIMER_COUNTER_NORST 2 | ||
78 | +#define TIMER_STATUS 3 | ||
79 | +#define TIMER_MODE 4 | ||
80 | + | ||
81 | +#define TIMER_COUNT_MASK32 0xfffffe00 | ||
82 | +#define TIMER_LIMIT_MASK32 0x7fffffff | ||
83 | +#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL | ||
84 | +#define TIMER_MAX_COUNT32 0x7ffffe00ULL | ||
85 | +#define TIMER_REACHED 0x80000000 | ||
86 | +#define TIMER_PERIOD 500ULL // 500ns | ||
87 | +#define LIMIT_TO_PERIODS(l) ((l) >> 9) | ||
88 | +#define PERIODS_TO_LIMIT(l) ((l) << 9) | ||
89 | + | ||
72 | static int slavio_timer_is_user(SLAVIO_TIMERState *s) | 90 | static int slavio_timer_is_user(SLAVIO_TIMERState *s) |
73 | { | 91 | { |
74 | return s->master && (s->master->slave_mode & (1 << s->slave_index)); | 92 | return s->master && (s->master->slave_mode & (1 << s->slave_index)); |
@@ -80,10 +98,10 @@ static void slavio_timer_get_out(SLAVIO_TIMERState *s) | @@ -80,10 +98,10 @@ static void slavio_timer_get_out(SLAVIO_TIMERState *s) | ||
80 | { | 98 | { |
81 | uint64_t count; | 99 | uint64_t count; |
82 | 100 | ||
83 | - count = s->limit - (ptimer_get_count(s->timer) << 9); | ||
84 | - DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh, | ||
85 | - s->count); | ||
86 | - s->count = count & 0xfffffe00; | 101 | + count = s->limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer)); |
102 | + DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, | ||
103 | + s->counthigh, s->count); | ||
104 | + s->count = count & TIMER_COUNT_MASK32; | ||
87 | s->counthigh = count >> 32; | 105 | s->counthigh = count >> 32; |
88 | } | 106 | } |
89 | 107 | ||
@@ -95,7 +113,7 @@ static void slavio_timer_irq(void *opaque) | @@ -95,7 +113,7 @@ static void slavio_timer_irq(void *opaque) | ||
95 | slavio_timer_get_out(s); | 113 | slavio_timer_get_out(s); |
96 | DPRINTF("callback: count %x%08x\n", s->counthigh, s->count); | 114 | DPRINTF("callback: count %x%08x\n", s->counthigh, s->count); |
97 | if (!slavio_timer_is_user(s)) { | 115 | if (!slavio_timer_is_user(s)) { |
98 | - s->reached = 0x80000000; | 116 | + s->reached = TIMER_REACHED; |
99 | qemu_irq_raise(s->irq); | 117 | qemu_irq_raise(s->irq); |
100 | } | 118 | } |
101 | } | 119 | } |
@@ -107,7 +125,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) | @@ -107,7 +125,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) | ||
107 | 125 | ||
108 | saddr = (addr & TIMER_MAXADDR) >> 2; | 126 | saddr = (addr & TIMER_MAXADDR) >> 2; |
109 | switch (saddr) { | 127 | switch (saddr) { |
110 | - case 0: | 128 | + case TIMER_LIMIT: |
111 | // read limit (system counter mode) or read most signifying | 129 | // read limit (system counter mode) or read most signifying |
112 | // part of counter (user mode) | 130 | // part of counter (user mode) |
113 | if (slavio_timer_is_user(s)) { | 131 | if (slavio_timer_is_user(s)) { |
@@ -119,24 +137,24 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) | @@ -119,24 +137,24 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) | ||
119 | // clear irq | 137 | // clear irq |
120 | qemu_irq_lower(s->irq); | 138 | qemu_irq_lower(s->irq); |
121 | s->reached = 0; | 139 | s->reached = 0; |
122 | - ret = s->limit & 0x7fffffff; | 140 | + ret = s->limit & TIMER_LIMIT_MASK32; |
123 | } | 141 | } |
124 | break; | 142 | break; |
125 | - case 1: | 143 | + case TIMER_COUNTER: |
126 | // read counter and reached bit (system mode) or read lsbits | 144 | // read counter and reached bit (system mode) or read lsbits |
127 | // of counter (user mode) | 145 | // of counter (user mode) |
128 | slavio_timer_get_out(s); | 146 | slavio_timer_get_out(s); |
129 | if (slavio_timer_is_user(s)) // read user timer LSW | 147 | if (slavio_timer_is_user(s)) // read user timer LSW |
130 | - ret = s->count & 0xfffffe00; | 148 | + ret = s->count & TIMER_COUNT_MASK32; |
131 | else // read limit | 149 | else // read limit |
132 | - ret = (s->count & 0x7ffffe00) | s->reached; | 150 | + ret = (s->count & TIMER_MAX_COUNT32) | s->reached; |
133 | break; | 151 | break; |
134 | - case 3: | 152 | + case TIMER_STATUS: |
135 | // only available in processor counter/timer | 153 | // only available in processor counter/timer |
136 | // read start/stop status | 154 | // read start/stop status |
137 | ret = s->running; | 155 | ret = s->running; |
138 | break; | 156 | break; |
139 | - case 4: | 157 | + case TIMER_MODE: |
140 | // only available in system counter | 158 | // only available in system counter |
141 | // read user/system mode | 159 | // read user/system mode |
142 | ret = s->slave_mode; | 160 | ret = s->slave_mode; |
@@ -151,7 +169,8 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) | @@ -151,7 +169,8 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) | ||
151 | return ret; | 169 | return ret; |
152 | } | 170 | } |
153 | 171 | ||
154 | -static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | 172 | +static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
173 | + uint32_t val) | ||
155 | { | 174 | { |
156 | SLAVIO_TIMERState *s = opaque; | 175 | SLAVIO_TIMERState *s = opaque; |
157 | uint32_t saddr; | 176 | uint32_t saddr; |
@@ -160,40 +179,40 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 | @@ -160,40 +179,40 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 | ||
160 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); | 179 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
161 | saddr = (addr & TIMER_MAXADDR) >> 2; | 180 | saddr = (addr & TIMER_MAXADDR) >> 2; |
162 | switch (saddr) { | 181 | switch (saddr) { |
163 | - case 0: | 182 | + case TIMER_LIMIT: |
164 | if (slavio_timer_is_user(s)) { | 183 | if (slavio_timer_is_user(s)) { |
165 | // set user counter MSW, reset counter | 184 | // set user counter MSW, reset counter |
166 | qemu_irq_lower(s->irq); | 185 | qemu_irq_lower(s->irq); |
167 | - s->limit = 0x7ffffffffffffe00ULL; | 186 | + s->limit = TIMER_MAX_COUNT64; |
168 | DPRINTF("processor %d user timer reset\n", s->slave_index); | 187 | DPRINTF("processor %d user timer reset\n", s->slave_index); |
169 | - ptimer_set_limit(s->timer, s->limit >> 9, 1); | 188 | + ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1); |
170 | } else { | 189 | } else { |
171 | // set limit, reset counter | 190 | // set limit, reset counter |
172 | qemu_irq_lower(s->irq); | 191 | qemu_irq_lower(s->irq); |
173 | - s->limit = val & 0x7ffffe00ULL; | 192 | + s->limit = val & TIMER_MAX_COUNT32; |
174 | if (!s->limit) | 193 | if (!s->limit) |
175 | - s->limit = 0x7ffffe00ULL; | 194 | + s->limit = TIMER_MAX_COUNT32; |
176 | ptimer_set_limit(s->timer, s->limit >> 9, 1); | 195 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
177 | } | 196 | } |
178 | break; | 197 | break; |
179 | - case 1: | 198 | + case TIMER_COUNTER: |
180 | if (slavio_timer_is_user(s)) { | 199 | if (slavio_timer_is_user(s)) { |
181 | // set user counter LSW, reset counter | 200 | // set user counter LSW, reset counter |
182 | qemu_irq_lower(s->irq); | 201 | qemu_irq_lower(s->irq); |
183 | - s->limit = 0x7ffffffffffffe00ULL; | 202 | + s->limit = TIMER_MAX_COUNT64; |
184 | DPRINTF("processor %d user timer reset\n", s->slave_index); | 203 | DPRINTF("processor %d user timer reset\n", s->slave_index); |
185 | - ptimer_set_limit(s->timer, s->limit >> 9, 1); | 204 | + ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1); |
186 | } else | 205 | } else |
187 | DPRINTF("not user timer\n"); | 206 | DPRINTF("not user timer\n"); |
188 | break; | 207 | break; |
189 | - case 2: | 208 | + case TIMER_COUNTER_NORST: |
190 | // set limit without resetting counter | 209 | // set limit without resetting counter |
191 | - s->limit = val & 0x7ffffe00ULL; | 210 | + s->limit = val & TIMER_MAX_COUNT32; |
192 | if (!s->limit) | 211 | if (!s->limit) |
193 | - s->limit = 0x7ffffe00ULL; | ||
194 | - ptimer_set_limit(s->timer, s->limit >> 9, reload); | 212 | + s->limit = TIMER_MAX_COUNT32; |
213 | + ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), reload); | ||
195 | break; | 214 | break; |
196 | - case 3: | 215 | + case TIMER_STATUS: |
197 | if (slavio_timer_is_user(s)) { | 216 | if (slavio_timer_is_user(s)) { |
198 | // start/stop user counter | 217 | // start/stop user counter |
199 | if ((val & 1) && !s->running) { | 218 | if ((val & 1) && !s->running) { |
@@ -207,7 +226,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 | @@ -207,7 +226,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 | ||
207 | } | 226 | } |
208 | } | 227 | } |
209 | break; | 228 | break; |
210 | - case 4: | 229 | + case TIMER_MODE: |
211 | if (s->master == NULL) { | 230 | if (s->master == NULL) { |
212 | unsigned int i; | 231 | unsigned int i; |
213 | 232 | ||
@@ -218,8 +237,10 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 | @@ -218,8 +237,10 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 | ||
218 | } | 237 | } |
219 | if ((val & (1 << i)) != (s->slave_mode & (1 << i))) { | 238 | if ((val & (1 << i)) != (s->slave_mode & (1 << i))) { |
220 | ptimer_stop(s->slave[i]->timer); | 239 | ptimer_stop(s->slave[i]->timer); |
221 | - ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9, 1); | ||
222 | - DPRINTF("processor %d timer changed\n", s->slave[i]->slave_index); | 240 | + ptimer_set_limit(s->slave[i]->timer, |
241 | + LIMIT_TO_PERIODS(s->slave[i]->limit), 1); | ||
242 | + DPRINTF("processor %d timer changed\n", | ||
243 | + s->slave[i]->slave_index); | ||
223 | ptimer_run(s->slave[i]->timer, 0); | 244 | ptimer_run(s->slave[i]->timer, 0); |
224 | } | 245 | } |
225 | } | 246 | } |
@@ -284,12 +305,12 @@ static void slavio_timer_reset(void *opaque) | @@ -284,12 +305,12 @@ static void slavio_timer_reset(void *opaque) | ||
284 | SLAVIO_TIMERState *s = opaque; | 305 | SLAVIO_TIMERState *s = opaque; |
285 | 306 | ||
286 | if (slavio_timer_is_user(s)) | 307 | if (slavio_timer_is_user(s)) |
287 | - s->limit = 0x7ffffffffffffe00ULL; | 308 | + s->limit = TIMER_MAX_COUNT64; |
288 | else | 309 | else |
289 | - s->limit = 0x7ffffe00ULL; | 310 | + s->limit = TIMER_MAX_COUNT32; |
290 | s->count = 0; | 311 | s->count = 0; |
291 | s->reached = 0; | 312 | s->reached = 0; |
292 | - ptimer_set_limit(s->timer, s->limit >> 9, 1); | 313 | + ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1); |
293 | ptimer_run(s->timer, 0); | 314 | ptimer_run(s->timer, 0); |
294 | s->running = 1; | 315 | s->running = 1; |
295 | qemu_irq_lower(s->irq); | 316 | qemu_irq_lower(s->irq); |
@@ -312,15 +333,18 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, | @@ -312,15 +333,18 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, | ||
312 | s->slave_index = slave_index; | 333 | s->slave_index = slave_index; |
313 | bh = qemu_bh_new(slavio_timer_irq, s); | 334 | bh = qemu_bh_new(slavio_timer_irq, s); |
314 | s->timer = ptimer_init(bh); | 335 | s->timer = ptimer_init(bh); |
315 | - ptimer_set_period(s->timer, 500ULL); | 336 | + ptimer_set_period(s->timer, TIMER_PERIOD); |
316 | 337 | ||
317 | slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read, | 338 | slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read, |
318 | slavio_timer_mem_write, s); | 339 | slavio_timer_mem_write, s); |
319 | if (master) | 340 | if (master) |
320 | - cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory); | 341 | + cpu_register_physical_memory(addr, CPU_TIMER_SIZE, |
342 | + slavio_timer_io_memory); | ||
321 | else | 343 | else |
322 | - cpu_register_physical_memory(addr, SYS_TIMER_SIZE, slavio_timer_io_memory); | ||
323 | - register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s); | 344 | + cpu_register_physical_memory(addr, SYS_TIMER_SIZE, |
345 | + slavio_timer_io_memory); | ||
346 | + register_savevm("slavio_timer", addr, 2, slavio_timer_save, | ||
347 | + slavio_timer_load, s); | ||
324 | qemu_register_reset(slavio_timer_reset, s); | 348 | qemu_register_reset(slavio_timer_reset, s); |
325 | slavio_timer_reset(s); | 349 | slavio_timer_reset(s); |
326 | 350 | ||
@@ -333,11 +357,11 @@ void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, | @@ -333,11 +357,11 @@ void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, | ||
333 | SLAVIO_TIMERState *master; | 357 | SLAVIO_TIMERState *master; |
334 | unsigned int i; | 358 | unsigned int i; |
335 | 359 | ||
336 | - master = slavio_timer_init(base + 0x10000ULL, master_irq, NULL, 0); | 360 | + master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0); |
337 | 361 | ||
338 | for (i = 0; i < MAX_CPUS; i++) { | 362 | for (i = 0; i < MAX_CPUS; i++) { |
339 | master->slave[i] = slavio_timer_init(base + (target_phys_addr_t) | 363 | master->slave[i] = slavio_timer_init(base + (target_phys_addr_t) |
340 | - (i * TARGET_PAGE_SIZE), | 364 | + CPU_TIMER_OFFSET(i), |
341 | cpu_irqs[i], master, i); | 365 | cpu_irqs[i], master, i); |
342 | } | 366 | } |
343 | } | 367 | } |