Commit d2123ead89bd2d337793dcd739352142ff69007c
1 parent
6276c767
Preliminary MIPS64R2 mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3479 c046a42c-6fe2-441c-8c8c-71466251a162
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target-mips/translate_init.c
| @@ -276,6 +276,27 @@ static mips_def_t mips_defs[] = | @@ -276,6 +276,27 @@ static mips_def_t mips_defs[] = | ||
| 276 | .SEGBITS = 40, | 276 | .SEGBITS = 40, |
| 277 | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, | 277 | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
| 278 | }, | 278 | }, |
| 279 | + { | ||
| 280 | + /* A generic CPU providing MIPS64 Release 2 features. | ||
| 281 | + FIXME: Eventually this should be replaced by a real CPU model. */ | ||
| 282 | + .name = "MIPS64R2-generic", | ||
| 283 | + .CP0_PRid = 0x00000000, | ||
| 284 | + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x1 << CP0C0_AR), | ||
| 285 | + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | | ||
| 286 | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | | ||
| 287 | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | | ||
| 288 | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | ||
| 289 | + .CP0_Config2 = MIPS_CONFIG2, | ||
| 290 | + .CP0_Config3 = MIPS_CONFIG3, | ||
| 291 | + .SYNCI_Step = 32, | ||
| 292 | + .CCRes = 2, | ||
| 293 | + .CP0_Status_rw_bitmask = 0x36FBFFFF, | ||
| 294 | + .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) | | ||
| 295 | + (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | | ||
| 296 | + (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), | ||
| 297 | + .SEGBITS = 40, | ||
| 298 | + .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, | ||
| 299 | + }, | ||
| 279 | #endif | 300 | #endif |
| 280 | }; | 301 | }; |
| 281 | 302 |