gwj / at91sam9263 · Commits

Commit d144d1d9e54eacf021c2cd82b206554977e34b70

Authored by aurel32
1 parent 1eb75d4a

target-mips: optimize gen_op_addr_add() (1/2) 

The user mode can be tested at translation time using ctx->hflags.
This simplifies gen_op_addr_add().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5676 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 7 additions and 10 deletions
target-mips/translate.c
  View file @d144d1d
... ... @@ -894,7 +894,7 @@ generate_exception (DisasContext *ctx, int excp)
894 894 }
895 895  
896 896 /* Addresses computation */
897   -static inline void gen_op_addr_add (TCGv t0, TCGv t1)
  897 +static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
898 898 {
899 899 tcg_gen_add_tl(t0, t0, t1);
900 900  
... ... @@ -902,19 +902,16 @@ static inline void gen_op_addr_add (TCGv t0, TCGv t1)
902 902 /* For compatibility with 32-bit code, data reference in user mode
903 903 with Status_UX = 0 should be casted to 32-bit and sign extended.
904 904 See the MIPS64 PRA manual, section 4.10. */
905   - {
  905 + if ((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) {
906 906 int l1 = gen_new_label();
907   - TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
  907 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
908 908  
909   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
910   - tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
911   - tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
912 909 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
913 910 tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
914 911 tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
915   - tcg_temp_free(r_tmp);
916 912 tcg_gen_ext32s_i64(t0, t0);
917 913 gen_set_label(l1);
  914 + tcg_temp_free(r_tmp);
918 915 }
919 916 #endif
920 917 }
... ... @@ -1070,7 +1067,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1070 1067 } else {
1071 1068 gen_load_gpr(t0, base);
1072 1069 tcg_gen_movi_tl(t1, offset);
1073   - gen_op_addr_add(t0, t1);
  1070 + gen_op_addr_add(ctx, t0, t1);
1074 1071 }
1075 1072 /* Don't do NOP if destination is zero: we must perform the actual
1076 1073 memory access. */
... ... @@ -1235,7 +1232,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1235 1232  
1236 1233 gen_load_gpr(t0, base);
1237 1234 tcg_gen_movi_tl(t1, offset);
1238   - gen_op_addr_add(t0, t1);
  1235 + gen_op_addr_add(ctx, t0, t1);
1239 1236 tcg_temp_free(t1);
1240 1237 }
1241 1238 /* Don't do NOP if destination is zero: we must perform the actual
... ... @@ -7369,7 +7366,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7369 7366 } else {
7370 7367 gen_load_gpr(t0, base);
7371 7368 gen_load_gpr(t1, index);
7372   - gen_op_addr_add(t0, t1);
  7369 + gen_op_addr_add(ctx, t0, t1);
7373 7370 }
7374 7371 /* Don't do NOP if destination is zero: we must perform the actual
7375 7372 memory access. */
... ...