gwj / at91sam9263 · Commits

Commit d12d51d5ba84817e2e7dcc95aeabebb230cc3781

Authored by aliguori
1 parent 40a4539e

Clean up debugging code #ifdefs (Eduardo Habkost) 

Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 15 changed files with 532 additions and 963 deletions
hw/ppc.c
  View file @d12d51d
@@ -31,6 +31,25 @@ @@ -31,6 +31,25 @@
31 //#define PPC_DEBUG_IRQ 31 //#define PPC_DEBUG_IRQ
32 //#define PPC_DEBUG_TB 32 //#define PPC_DEBUG_TB
33 33
  34 +#ifdef PPC_DEBUG_IRQ
  35 +# define LOG_IRQ(...) do { \
  36 + if (loglevel & CPU_LOG_INT) \
  37 + fprintf(logfile, ## __VA_ARGS__); \
  38 + } while (0)
  39 +#else
  40 +# define LOG_IRQ(...) do { } while (0)
  41 +#endif
  42 +
  43 +
  44 +#ifdef PPC_DEBUG_TB
  45 +# define LOG_TB(...) do { \
  46 + if (loglevel) \
  47 + fprintf(logfile, ## __VA_ARGS__); \
  48 + } while (0)
  49 +#else
  50 +# define LOG_TB(...) do { } while (0)
  51 +#endif
  52 +
34 static void cpu_ppc_tb_stop (CPUState *env); 53 static void cpu_ppc_tb_stop (CPUState *env);
35 static void cpu_ppc_tb_start (CPUState *env); 54 static void cpu_ppc_tb_start (CPUState *env);
36 55
@@ -44,13 +63,9 @@ static void ppc_set_irq (CPUState *env, int n_IRQ, int level) @@ -44,13 +63,9 @@ static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
44 if (env->pending_interrupts == 0) 63 if (env->pending_interrupts == 0)
45 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); 64 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
46 } 65 }
47 -#if defined(PPC_DEBUG_IRQ)  
48 - if (loglevel & CPU_LOG_INT) {  
49 - fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08" PRIx32 66 + LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
50 "req %08x\n", __func__, env, n_IRQ, level, 67 "req %08x\n", __func__, env, n_IRQ, level,
51 env->pending_interrupts, env->interrupt_request); 68 env->pending_interrupts, env->interrupt_request);
52 - }  
53 -#endif  
54 } 69 }
55 70
56 /* PowerPC 6xx / 7xx internal IRQ controller */ 71 /* PowerPC 6xx / 7xx internal IRQ controller */
@@ -59,24 +74,16 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) @@ -59,24 +74,16 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
59 CPUState *env = opaque; 74 CPUState *env = opaque;
60 int cur_level; 75 int cur_level;
61 76
62 -#if defined(PPC_DEBUG_IRQ)  
63 - if (loglevel & CPU_LOG_INT) {  
64 - fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, 77 + LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
65 env, pin, level); 78 env, pin, level);
66 - }  
67 -#endif  
68 cur_level = (env->irq_input_state >> pin) & 1; 79 cur_level = (env->irq_input_state >> pin) & 1;
69 /* Don't generate spurious events */ 80 /* Don't generate spurious events */
70 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 81 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
71 switch (pin) { 82 switch (pin) {
72 case PPC6xx_INPUT_TBEN: 83 case PPC6xx_INPUT_TBEN:
73 /* Level sensitive - active high */ 84 /* Level sensitive - active high */
74 -#if defined(PPC_DEBUG_IRQ)  
75 - if (loglevel & CPU_LOG_INT) {  
76 - fprintf(logfile, "%s: %s the time base\n", 85 + LOG_IRQ("%s: %s the time base\n",
77 __func__, level ? "start" : "stop"); 86 __func__, level ? "start" : "stop");
78 - }  
79 -#endif  
80 if (level) { 87 if (level) {
81 cpu_ppc_tb_start(env); 88 cpu_ppc_tb_start(env);
82 } else { 89 } else {
@@ -84,22 +91,14 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) @@ -84,22 +91,14 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
84 } 91 }
85 case PPC6xx_INPUT_INT: 92 case PPC6xx_INPUT_INT:
86 /* Level sensitive - active high */ 93 /* Level sensitive - active high */
87 -#if defined(PPC_DEBUG_IRQ)  
88 - if (loglevel & CPU_LOG_INT) {  
89 - fprintf(logfile, "%s: set the external IRQ state to %d\n", 94 + LOG_IRQ("%s: set the external IRQ state to %d\n",
90 __func__, level); 95 __func__, level);
91 - }  
92 -#endif  
93 ppc_set_irq(env, PPC_INTERRUPT_EXT, level); 96 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
94 break; 97 break;
95 case PPC6xx_INPUT_SMI: 98 case PPC6xx_INPUT_SMI:
96 /* Level sensitive - active high */ 99 /* Level sensitive - active high */
97 -#if defined(PPC_DEBUG_IRQ)  
98 - if (loglevel & CPU_LOG_INT) {  
99 - fprintf(logfile, "%s: set the SMI IRQ state to %d\n", 100 + LOG_IRQ("%s: set the SMI IRQ state to %d\n",
100 __func__, level); 101 __func__, level);
101 - }  
102 -#endif  
103 ppc_set_irq(env, PPC_INTERRUPT_SMI, level); 102 ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
104 break; 103 break;
105 case PPC6xx_INPUT_MCP: 104 case PPC6xx_INPUT_MCP:
@@ -108,12 +107,8 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) @@ -108,12 +107,8 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
108 * 603/604/740/750: check HID0[EMCP] 107 * 603/604/740/750: check HID0[EMCP]
109 */ 108 */
110 if (cur_level == 1 && level == 0) { 109 if (cur_level == 1 && level == 0) {
111 -#if defined(PPC_DEBUG_IRQ)  
112 - if (loglevel & CPU_LOG_INT) {  
113 - fprintf(logfile, "%s: raise machine check state\n", 110 + LOG_IRQ("%s: raise machine check state\n",
114 __func__); 111 __func__);
115 - }  
116 -#endif  
117 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); 112 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
118 } 113 }
119 break; 114 break;
@@ -122,22 +117,14 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) @@ -122,22 +117,14 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
122 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 117 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
123 /* XXX: Note that the only way to restart the CPU is to reset it */ 118 /* XXX: Note that the only way to restart the CPU is to reset it */
124 if (level) { 119 if (level) {
125 -#if defined(PPC_DEBUG_IRQ)  
126 - if (loglevel & CPU_LOG_INT) {  
127 - fprintf(logfile, "%s: stop the CPU\n", __func__);  
128 - }  
129 -#endif 120 + LOG_IRQ("%s: stop the CPU\n", __func__);
130 env->halted = 1; 121 env->halted = 1;
131 } 122 }
132 break; 123 break;
133 case PPC6xx_INPUT_HRESET: 124 case PPC6xx_INPUT_HRESET:
134 /* Level sensitive - active low */ 125 /* Level sensitive - active low */
135 if (level) { 126 if (level) {
136 -#if defined(PPC_DEBUG_IRQ)  
137 - if (loglevel & CPU_LOG_INT) {  
138 - fprintf(logfile, "%s: reset the CPU\n", __func__);  
139 - }  
140 -#endif 127 + LOG_IRQ("%s: reset the CPU\n", __func__);
141 env->interrupt_request |= CPU_INTERRUPT_EXITTB; 128 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
142 /* XXX: TOFIX */ 129 /* XXX: TOFIX */
143 #if 0 130 #if 0
@@ -148,21 +135,13 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) @@ -148,21 +135,13 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
148 } 135 }
149 break; 136 break;
150 case PPC6xx_INPUT_SRESET: 137 case PPC6xx_INPUT_SRESET:
151 -#if defined(PPC_DEBUG_IRQ)  
152 - if (loglevel & CPU_LOG_INT) {  
153 - fprintf(logfile, "%s: set the RESET IRQ state to %d\n", 138 + LOG_IRQ("%s: set the RESET IRQ state to %d\n",
154 __func__, level); 139 __func__, level);
155 - }  
156 -#endif  
157 ppc_set_irq(env, PPC_INTERRUPT_RESET, level); 140 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
158 break; 141 break;
159 default: 142 default:
160 /* Unknown pin - do nothing */ 143 /* Unknown pin - do nothing */
161 -#if defined(PPC_DEBUG_IRQ)  
162 - if (loglevel & CPU_LOG_INT) {  
163 - fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);  
164 - }  
165 -#endif 144 + LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
166 return; 145 return;
167 } 146 }
168 if (level) 147 if (level)
@@ -185,34 +164,22 @@ static void ppc970_set_irq (void *opaque, int pin, int level) @@ -185,34 +164,22 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
185 CPUState *env = opaque; 164 CPUState *env = opaque;
186 int cur_level; 165 int cur_level;
187 166
188 -#if defined(PPC_DEBUG_IRQ)  
189 - if (loglevel & CPU_LOG_INT) {  
190 - fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, 167 + LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
191 env, pin, level); 168 env, pin, level);
192 - }  
193 -#endif  
194 cur_level = (env->irq_input_state >> pin) & 1; 169 cur_level = (env->irq_input_state >> pin) & 1;
195 /* Don't generate spurious events */ 170 /* Don't generate spurious events */
196 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 171 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
197 switch (pin) { 172 switch (pin) {
198 case PPC970_INPUT_INT: 173 case PPC970_INPUT_INT:
199 /* Level sensitive - active high */ 174 /* Level sensitive - active high */
200 -#if defined(PPC_DEBUG_IRQ)  
201 - if (loglevel & CPU_LOG_INT) {  
202 - fprintf(logfile, "%s: set the external IRQ state to %d\n", 175 + LOG_IRQ("%s: set the external IRQ state to %d\n",
203 __func__, level); 176 __func__, level);
204 - }  
205 -#endif  
206 ppc_set_irq(env, PPC_INTERRUPT_EXT, level); 177 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
207 break; 178 break;
208 case PPC970_INPUT_THINT: 179 case PPC970_INPUT_THINT:
209 /* Level sensitive - active high */ 180 /* Level sensitive - active high */
210 -#if defined(PPC_DEBUG_IRQ)  
211 - if (loglevel & CPU_LOG_INT) {  
212 - fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__, 181 + LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
213 level); 182 level);
214 - }  
215 -#endif  
216 ppc_set_irq(env, PPC_INTERRUPT_THERM, level); 183 ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
217 break; 184 break;
218 case PPC970_INPUT_MCP: 185 case PPC970_INPUT_MCP:
@@ -221,12 +188,8 @@ static void ppc970_set_irq (void *opaque, int pin, int level) @@ -221,12 +188,8 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
221 * 603/604/740/750: check HID0[EMCP] 188 * 603/604/740/750: check HID0[EMCP]
222 */ 189 */
223 if (cur_level == 1 && level == 0) { 190 if (cur_level == 1 && level == 0) {
224 -#if defined(PPC_DEBUG_IRQ)  
225 - if (loglevel & CPU_LOG_INT) {  
226 - fprintf(logfile, "%s: raise machine check state\n", 191 + LOG_IRQ("%s: raise machine check state\n",
227 __func__); 192 __func__);
228 - }  
229 -#endif  
230 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); 193 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
231 } 194 }
232 break; 195 break;
@@ -234,18 +197,10 @@ static void ppc970_set_irq (void *opaque, int pin, int level) @@ -234,18 +197,10 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
234 /* Level sensitive - active low */ 197 /* Level sensitive - active low */
235 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 198 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
236 if (level) { 199 if (level) {
237 -#if defined(PPC_DEBUG_IRQ)  
238 - if (loglevel & CPU_LOG_INT) {  
239 - fprintf(logfile, "%s: stop the CPU\n", __func__);  
240 - }  
241 -#endif 200 + LOG_IRQ("%s: stop the CPU\n", __func__);
242 env->halted = 1; 201 env->halted = 1;
243 } else { 202 } else {
244 -#if defined(PPC_DEBUG_IRQ)  
245 - if (loglevel & CPU_LOG_INT) {  
246 - fprintf(logfile, "%s: restart the CPU\n", __func__);  
247 - }  
248 -#endif 203 + LOG_IRQ("%s: restart the CPU\n", __func__);
249 env->halted = 0; 204 env->halted = 0;
250 } 205 }
251 break; 206 break;
@@ -253,40 +208,24 @@ static void ppc970_set_irq (void *opaque, int pin, int level) @@ -253,40 +208,24 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
253 /* Level sensitive - active low */ 208 /* Level sensitive - active low */
254 if (level) { 209 if (level) {
255 #if 0 // XXX: TOFIX 210 #if 0 // XXX: TOFIX
256 -#if defined(PPC_DEBUG_IRQ)  
257 - if (loglevel & CPU_LOG_INT) {  
258 - fprintf(logfile, "%s: reset the CPU\n", __func__);  
259 - }  
260 -#endif 211 + LOG_IRQ("%s: reset the CPU\n", __func__);
261 cpu_reset(env); 212 cpu_reset(env);
262 #endif 213 #endif
263 } 214 }
264 break; 215 break;
265 case PPC970_INPUT_SRESET: 216 case PPC970_INPUT_SRESET:
266 -#if defined(PPC_DEBUG_IRQ)  
267 - if (loglevel & CPU_LOG_INT) {  
268 - fprintf(logfile, "%s: set the RESET IRQ state to %d\n", 217 + LOG_IRQ("%s: set the RESET IRQ state to %d\n",
269 __func__, level); 218 __func__, level);
270 - }  
271 -#endif  
272 ppc_set_irq(env, PPC_INTERRUPT_RESET, level); 219 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
273 break; 220 break;
274 case PPC970_INPUT_TBEN: 221 case PPC970_INPUT_TBEN:
275 -#if defined(PPC_DEBUG_IRQ)  
276 - if (loglevel & CPU_LOG_INT) {  
277 - fprintf(logfile, "%s: set the TBEN state to %d\n", __func__, 222 + LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
278 level); 223 level);
279 - }  
280 -#endif  
281 /* XXX: TODO */ 224 /* XXX: TODO */
282 break; 225 break;
283 default: 226 default:
284 /* Unknown pin - do nothing */ 227 /* Unknown pin - do nothing */
285 -#if defined(PPC_DEBUG_IRQ)  
286 - if (loglevel & CPU_LOG_INT) {  
287 - fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);  
288 - }  
289 -#endif 228 + LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
290 return; 229 return;
291 } 230 }
292 if (level) 231 if (level)
@@ -309,103 +248,63 @@ static void ppc40x_set_irq (void *opaque, int pin, int level) @@ -309,103 +248,63 @@ static void ppc40x_set_irq (void *opaque, int pin, int level)
309 CPUState *env = opaque; 248 CPUState *env = opaque;
310 int cur_level; 249 int cur_level;
311 250
312 -#if defined(PPC_DEBUG_IRQ)  
313 - if (loglevel & CPU_LOG_INT) {  
314 - fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, 251 + LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
315 env, pin, level); 252 env, pin, level);
316 - }  
317 -#endif  
318 cur_level = (env->irq_input_state >> pin) & 1; 253 cur_level = (env->irq_input_state >> pin) & 1;
319 /* Don't generate spurious events */ 254 /* Don't generate spurious events */
320 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 255 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
321 switch (pin) { 256 switch (pin) {
322 case PPC40x_INPUT_RESET_SYS: 257 case PPC40x_INPUT_RESET_SYS:
323 if (level) { 258 if (level) {
324 -#if defined(PPC_DEBUG_IRQ)  
325 - if (loglevel & CPU_LOG_INT) {  
326 - fprintf(logfile, "%s: reset the PowerPC system\n", 259 + LOG_IRQ("%s: reset the PowerPC system\n",
327 __func__); 260 __func__);
328 - }  
329 -#endif  
330 ppc40x_system_reset(env); 261 ppc40x_system_reset(env);
331 } 262 }
332 break; 263 break;
333 case PPC40x_INPUT_RESET_CHIP: 264 case PPC40x_INPUT_RESET_CHIP:
334 if (level) { 265 if (level) {
335 -#if defined(PPC_DEBUG_IRQ)  
336 - if (loglevel & CPU_LOG_INT) {  
337 - fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);  
338 - }  
339 -#endif 266 + LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
340 ppc40x_chip_reset(env); 267 ppc40x_chip_reset(env);
341 } 268 }
342 break; 269 break;
343 case PPC40x_INPUT_RESET_CORE: 270 case PPC40x_INPUT_RESET_CORE:
344 /* XXX: TODO: update DBSR[MRR] */ 271 /* XXX: TODO: update DBSR[MRR] */
345 if (level) { 272 if (level) {
346 -#if defined(PPC_DEBUG_IRQ)  
347 - if (loglevel & CPU_LOG_INT) {  
348 - fprintf(logfile, "%s: reset the PowerPC core\n", __func__);  
349 - }  
350 -#endif 273 + LOG_IRQ("%s: reset the PowerPC core\n", __func__);
351 ppc40x_core_reset(env); 274 ppc40x_core_reset(env);
352 } 275 }
353 break; 276 break;
354 case PPC40x_INPUT_CINT: 277 case PPC40x_INPUT_CINT:
355 /* Level sensitive - active high */ 278 /* Level sensitive - active high */
356 -#if defined(PPC_DEBUG_IRQ)  
357 - if (loglevel & CPU_LOG_INT) {  
358 - fprintf(logfile, "%s: set the critical IRQ state to %d\n", 279 + LOG_IRQ("%s: set the critical IRQ state to %d\n",
359 __func__, level); 280 __func__, level);
360 - }  
361 -#endif  
362 ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); 281 ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
363 break; 282 break;
364 case PPC40x_INPUT_INT: 283 case PPC40x_INPUT_INT:
365 /* Level sensitive - active high */ 284 /* Level sensitive - active high */
366 -#if defined(PPC_DEBUG_IRQ)  
367 - if (loglevel & CPU_LOG_INT) {  
368 - fprintf(logfile, "%s: set the external IRQ state to %d\n", 285 + LOG_IRQ("%s: set the external IRQ state to %d\n",
369 __func__, level); 286 __func__, level);
370 - }  
371 -#endif  
372 ppc_set_irq(env, PPC_INTERRUPT_EXT, level); 287 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
373 break; 288 break;
374 case PPC40x_INPUT_HALT: 289 case PPC40x_INPUT_HALT:
375 /* Level sensitive - active low */ 290 /* Level sensitive - active low */
376 if (level) { 291 if (level) {
377 -#if defined(PPC_DEBUG_IRQ)  
378 - if (loglevel & CPU_LOG_INT) {  
379 - fprintf(logfile, "%s: stop the CPU\n", __func__);  
380 - }  
381 -#endif 292 + LOG_IRQ("%s: stop the CPU\n", __func__);
382 env->halted = 1; 293 env->halted = 1;
383 } else { 294 } else {
384 -#if defined(PPC_DEBUG_IRQ)  
385 - if (loglevel & CPU_LOG_INT) {  
386 - fprintf(logfile, "%s: restart the CPU\n", __func__);  
387 - }  
388 -#endif 295 + LOG_IRQ("%s: restart the CPU\n", __func__);
389 env->halted = 0; 296 env->halted = 0;
390 } 297 }
391 break; 298 break;
392 case PPC40x_INPUT_DEBUG: 299 case PPC40x_INPUT_DEBUG:
393 /* Level sensitive - active high */ 300 /* Level sensitive - active high */
394 -#if defined(PPC_DEBUG_IRQ)  
395 - if (loglevel & CPU_LOG_INT) {  
396 - fprintf(logfile, "%s: set the debug pin state to %d\n", 301 + LOG_IRQ("%s: set the debug pin state to %d\n",
397 __func__, level); 302 __func__, level);
398 - }  
399 -#endif  
400 ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); 303 ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
401 break; 304 break;
402 default: 305 default:
403 /* Unknown pin - do nothing */ 306 /* Unknown pin - do nothing */
404 -#if defined(PPC_DEBUG_IRQ)  
405 - if (loglevel & CPU_LOG_INT) {  
406 - fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);  
407 - }  
408 -#endif 307 + LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
409 return; 308 return;
410 } 309 }
411 if (level) 310 if (level)
@@ -453,11 +352,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env) @@ -453,11 +352,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
453 uint64_t tb; 352 uint64_t tb;
454 353
455 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); 354 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
456 -#if defined(PPC_DEBUG_TB)  
457 - if (loglevel != 0) {  
458 - fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);  
459 - }  
460 -#endif 355 + LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
461 356
462 return tb & 0xFFFFFFFF; 357 return tb & 0xFFFFFFFF;
463 } 358 }
@@ -468,11 +363,7 @@ static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env) @@ -468,11 +363,7 @@ static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
468 uint64_t tb; 363 uint64_t tb;
469 364
470 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); 365 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
471 -#if defined(PPC_DEBUG_TB)  
472 - if (loglevel != 0) {  
473 - fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);  
474 - }  
475 -#endif 366 + LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
476 367
477 return tb >> 32; 368 return tb >> 32;
478 } 369 }
@@ -487,12 +378,8 @@ static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk, @@ -487,12 +378,8 @@ static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,
487 uint64_t value) 378 uint64_t value)
488 { 379 {
489 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); 380 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
490 -#ifdef PPC_DEBUG_TB  
491 - if (loglevel != 0) {  
492 - fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 381 + LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
493 __func__, value, *tb_offsetp); 382 __func__, value, *tb_offsetp);
494 - }  
495 -#endif  
496 } 383 }
497 384
498 void cpu_ppc_store_tbl (CPUState *env, uint32_t value) 385 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
@@ -528,11 +415,7 @@ uint32_t cpu_ppc_load_atbl (CPUState *env) @@ -528,11 +415,7 @@ uint32_t cpu_ppc_load_atbl (CPUState *env)
528 uint64_t tb; 415 uint64_t tb;
529 416
530 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); 417 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
531 -#if defined(PPC_DEBUG_TB)  
532 - if (loglevel != 0) {  
533 - fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);  
534 - }  
535 -#endif 418 + LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
536 419
537 return tb & 0xFFFFFFFF; 420 return tb & 0xFFFFFFFF;
538 } 421 }
@@ -543,11 +426,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env) @@ -543,11 +426,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
543 uint64_t tb; 426 uint64_t tb;
544 427
545 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); 428 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
546 -#if defined(PPC_DEBUG_TB)  
547 - if (loglevel != 0) {  
548 - fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);  
549 - }  
550 -#endif 429 + LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
551 430
552 return tb >> 32; 431 return tb >> 32;
553 } 432 }
@@ -629,11 +508,7 @@ static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, @@ -629,11 +508,7 @@ static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
629 decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); 508 decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec);
630 else 509 else
631 decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); 510 decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);
632 -#if defined(PPC_DEBUG_TB)  
633 - if (loglevel != 0) {  
634 - fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr);  
635 - }  
636 -#endif 511 + LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
637 512
638 return decr; 513 return decr;
639 } 514 }
@@ -668,22 +543,14 @@ uint64_t cpu_ppc_load_purr (CPUState *env) @@ -668,22 +543,14 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
668 static always_inline void cpu_ppc_decr_excp (CPUState *env) 543 static always_inline void cpu_ppc_decr_excp (CPUState *env)
669 { 544 {
670 /* Raise it */ 545 /* Raise it */
671 -#ifdef PPC_DEBUG_TB  
672 - if (loglevel != 0) {  
673 - fprintf(logfile, "raise decrementer exception\n");  
674 - }  
675 -#endif 546 + LOG_TB("raise decrementer exception\n");
676 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); 547 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
677 } 548 }
678 549
679 static always_inline void cpu_ppc_hdecr_excp (CPUState *env) 550 static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
680 { 551 {
681 /* Raise it */ 552 /* Raise it */
682 -#ifdef PPC_DEBUG_TB  
683 - if (loglevel != 0) {  
684 - fprintf(logfile, "raise decrementer exception\n");  
685 - }  
686 -#endif 553 + LOG_TB("raise decrementer exception\n");
687 ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); 554 ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
688 } 555 }
689 556
@@ -696,12 +563,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, @@ -696,12 +563,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
696 ppc_tb_t *tb_env = env->tb_env; 563 ppc_tb_t *tb_env = env->tb_env;
697 uint64_t now, next; 564 uint64_t now, next;
698 565
699 -#ifdef PPC_DEBUG_TB  
700 - if (loglevel != 0) {  
701 - fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, 566 + LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
702 decr, value); 567 decr, value);
703 - }  
704 -#endif  
705 now = qemu_get_clock(vm_clock); 568 now = qemu_get_clock(vm_clock);
706 next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); 569 next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq);
707 if (is_excp) 570 if (is_excp)
@@ -882,13 +745,9 @@ static void cpu_4xx_fit_cb (void *opaque) @@ -882,13 +745,9 @@ static void cpu_4xx_fit_cb (void *opaque)
882 env->spr[SPR_40x_TSR] |= 1 << 26; 745 env->spr[SPR_40x_TSR] |= 1 << 26;
883 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) 746 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
884 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1); 747 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
885 -#ifdef PPC_DEBUG_TB  
886 - if (loglevel != 0) {  
887 - fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, 748 + LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
888 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 749 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
889 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 750 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
890 - }  
891 -#endif  
892 } 751 }
893 752
894 /* Programmable interval timer */ 753 /* Programmable interval timer */
@@ -902,19 +761,11 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) @@ -902,19 +761,11 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
902 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 761 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
903 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 762 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
904 /* Stop PIT */ 763 /* Stop PIT */
905 -#ifdef PPC_DEBUG_TB  
906 - if (loglevel != 0) {  
907 - fprintf(logfile, "%s: stop PIT\n", __func__);  
908 - }  
909 -#endif 764 + LOG_TB("%s: stop PIT\n", __func__);
910 qemu_del_timer(tb_env->decr_timer); 765 qemu_del_timer(tb_env->decr_timer);
911 } else { 766 } else {
912 -#ifdef PPC_DEBUG_TB  
913 - if (loglevel != 0) {  
914 - fprintf(logfile, "%s: start PIT %016" PRIx64 "\n", 767 + LOG_TB("%s: start PIT %016" PRIx64 "\n",
915 __func__, ppcemb_timer->pit_reload); 768 __func__, ppcemb_timer->pit_reload);
916 - }  
917 -#endif  
918 now = qemu_get_clock(vm_clock); 769 now = qemu_get_clock(vm_clock);
919 next = now + muldiv64(ppcemb_timer->pit_reload, 770 next = now + muldiv64(ppcemb_timer->pit_reload,
920 ticks_per_sec, tb_env->decr_freq); 771 ticks_per_sec, tb_env->decr_freq);
@@ -940,16 +791,12 @@ static void cpu_4xx_pit_cb (void *opaque) @@ -940,16 +791,12 @@ static void cpu_4xx_pit_cb (void *opaque)
940 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) 791 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
941 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1); 792 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
942 start_stop_pit(env, tb_env, 1); 793 start_stop_pit(env, tb_env, 1);
943 -#ifdef PPC_DEBUG_TB  
944 - if (loglevel != 0) {  
945 - fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " 794 + LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
946 "%016" PRIx64 "\n", __func__, 795 "%016" PRIx64 "\n", __func__,
947 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 796 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
948 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 797 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
949 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 798 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
950 ppcemb_timer->pit_reload); 799 ppcemb_timer->pit_reload);
951 - }  
952 -#endif  
953 } 800 }
954 801
955 /* Watchdog timer */ 802 /* Watchdog timer */
@@ -984,12 +831,8 @@ static void cpu_4xx_wdt_cb (void *opaque) @@ -984,12 +831,8 @@ static void cpu_4xx_wdt_cb (void *opaque)
984 next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); 831 next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);
985 if (next == now) 832 if (next == now)
986 next++; 833 next++;
987 -#ifdef PPC_DEBUG_TB  
988 - if (loglevel != 0) {  
989 - fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, 834 + LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
990 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 835 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
991 - }  
992 -#endif  
993 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 836 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
994 case 0x0: 837 case 0x0:
995 case 0x1: 838 case 0x1:
@@ -1031,11 +874,7 @@ void store_40x_pit (CPUState *env, target_ulong val) @@ -1031,11 +874,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
1031 874
1032 tb_env = env->tb_env; 875 tb_env = env->tb_env;
1033 ppcemb_timer = tb_env->opaque; 876 ppcemb_timer = tb_env->opaque;
1034 -#ifdef PPC_DEBUG_TB  
1035 - if (loglevel != 0) {  
1036 - fprintf(logfile, "%s val" ADDRX "\n", __func__, val);  
1037 - }  
1038 -#endif 877 + LOG_TB("%s val" ADDRX "\n", __func__, val);
1039 ppcemb_timer->pit_reload = val; 878 ppcemb_timer->pit_reload = val;
1040 start_stop_pit(env, tb_env, 0); 879 start_stop_pit(env, tb_env, 0);
1041 } 880 }
@@ -1047,11 +886,7 @@ target_ulong load_40x_pit (CPUState *env) @@ -1047,11 +886,7 @@ target_ulong load_40x_pit (CPUState *env)
1047 886
1048 void store_booke_tsr (CPUState *env, target_ulong val) 887 void store_booke_tsr (CPUState *env, target_ulong val)
1049 { 888 {
1050 -#ifdef PPC_DEBUG_TB  
1051 - if (loglevel != 0) {  
1052 - fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);  
1053 - }  
1054 -#endif 889 + LOG_TB("%s: val " ADDRX "\n", __func__, val);
1055 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); 890 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
1056 if (val & 0x80000000) 891 if (val & 0x80000000)
1057 ppc_set_irq(env, PPC_INTERRUPT_PIT, 0); 892 ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
@@ -1062,11 +897,7 @@ void store_booke_tcr (CPUState *env, target_ulong val) @@ -1062,11 +897,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
1062 ppc_tb_t *tb_env; 897 ppc_tb_t *tb_env;
1063 898
1064 tb_env = env->tb_env; 899 tb_env = env->tb_env;
1065 -#ifdef PPC_DEBUG_TB  
1066 - if (loglevel != 0) {  
1067 - fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);  
1068 - }  
1069 -#endif 900 + LOG_TB("%s: val " ADDRX "\n", __func__, val);
1070 env->spr[SPR_40x_TCR] = val & 0xFFC00000; 901 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
1071 start_stop_pit(env, tb_env, 1); 902 start_stop_pit(env, tb_env, 1);
1072 cpu_4xx_wdt_cb(env); 903 cpu_4xx_wdt_cb(env);
@@ -1077,12 +908,8 @@ static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) @@ -1077,12 +908,8 @@ static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
1077 CPUState *env = opaque; 908 CPUState *env = opaque;
1078 ppc_tb_t *tb_env = env->tb_env; 909 ppc_tb_t *tb_env = env->tb_env;
1079 910
1080 -#ifdef PPC_DEBUG_TB  
1081 - if (loglevel != 0) {  
1082 - fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__, 911 + LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1083 freq); 912 freq);
1084 - }  
1085 -#endif  
1086 tb_env->tb_freq = freq; 913 tb_env->tb_freq = freq;
1087 tb_env->decr_freq = freq; 914 tb_env->decr_freq = freq;
1088 /* XXX: we should also update all timers */ 915 /* XXX: we should also update all timers */
@@ -1102,11 +929,7 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) @@ -1102,11 +929,7 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
1102 tb_env->tb_freq = freq; 929 tb_env->tb_freq = freq;
1103 tb_env->decr_freq = freq; 930 tb_env->decr_freq = freq;
1104 tb_env->opaque = ppcemb_timer; 931 tb_env->opaque = ppcemb_timer;
1105 -#ifdef PPC_DEBUG_TB  
1106 - if (loglevel != 0) {  
1107 - fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq);  
1108 - }  
1109 -#endif 932 + LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1110 if (ppcemb_timer != NULL) { 933 if (ppcemb_timer != NULL) {
1111 /* We use decr timer for PIT */ 934 /* We use decr timer for PIT */
1112 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); 935 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
hw/ppc4xx_devs.c
  View file @d12d51d
@@ -31,6 +31,16 @@ @@ -31,6 +31,16 @@
31 //#define DEBUG_UNASSIGNED 31 //#define DEBUG_UNASSIGNED
32 #define DEBUG_UIC 32 #define DEBUG_UIC
33 33
  34 +
  35 +#ifdef DEBUG_UIC
  36 +# define LOG_UIC(...) do { \
  37 + if (loglevel & CPU_LOG_INT) \
  38 + fprintf(logfile, ## __VA_ARGS__); \
  39 + } while (0)
  40 +#else
  41 +# define LOG_UIC(...) do { } while (0)
  42 +#endif
  43 +
34 /*****************************************************************************/ 44 /*****************************************************************************/
35 /* Generic PowerPC 4xx processor instanciation */ 45 /* Generic PowerPC 4xx processor instanciation */
36 CPUState *ppc4xx_init (const char *cpu_model, 46 CPUState *ppc4xx_init (const char *cpu_model,
@@ -294,28 +304,16 @@ static void ppcuic_trigger_irq (ppcuic_t *uic) @@ -294,28 +304,16 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
294 /* Trigger interrupt if any is pending */ 304 /* Trigger interrupt if any is pending */
295 ir = uic->uicsr & uic->uicer & (~uic->uiccr); 305 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
296 cr = uic->uicsr & uic->uicer & uic->uiccr; 306 cr = uic->uicsr & uic->uicer & uic->uiccr;
297 -#ifdef DEBUG_UIC  
298 - if (loglevel & CPU_LOG_INT) {  
299 - fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32 307 + LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
300 " uiccr %08" PRIx32 "\n" 308 " uiccr %08" PRIx32 "\n"
301 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", 309 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
302 __func__, uic->uicsr, uic->uicer, uic->uiccr, 310 __func__, uic->uicsr, uic->uicer, uic->uiccr,
303 uic->uicsr & uic->uicer, ir, cr); 311 uic->uicsr & uic->uicer, ir, cr);
304 - }  
305 -#endif  
306 if (ir != 0x0000000) { 312 if (ir != 0x0000000) {
307 -#ifdef DEBUG_UIC  
308 - if (loglevel & CPU_LOG_INT) {  
309 - fprintf(logfile, "Raise UIC interrupt\n");  
310 - }  
311 -#endif 313 + LOG_UIC("Raise UIC interrupt\n");
312 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); 314 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
313 } else { 315 } else {
314 -#ifdef DEBUG_UIC  
315 - if (loglevel & CPU_LOG_INT) {  
316 - fprintf(logfile, "Lower UIC interrupt\n");  
317 - }  
318 -#endif 316 + LOG_UIC("Lower UIC interrupt\n");
319 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); 317 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
320 } 318 }
321 /* Trigger critical interrupt if any is pending and update vector */ 319 /* Trigger critical interrupt if any is pending and update vector */
@@ -340,18 +338,10 @@ static void ppcuic_trigger_irq (ppcuic_t *uic) @@ -340,18 +338,10 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
340 } 338 }
341 } 339 }
342 } 340 }
343 -#ifdef DEBUG_UIC  
344 - if (loglevel & CPU_LOG_INT) {  
345 - fprintf(logfile, "Raise UIC critical interrupt - " 341 + LOG_UIC("Raise UIC critical interrupt - "
346 "vector %08" PRIx32 "\n", uic->uicvr); 342 "vector %08" PRIx32 "\n", uic->uicvr);
347 - }  
348 -#endif  
349 } else { 343 } else {
350 -#ifdef DEBUG_UIC  
351 - if (loglevel & CPU_LOG_INT) {  
352 - fprintf(logfile, "Lower UIC critical interrupt\n");  
353 - }  
354 -#endif 344 + LOG_UIC("Lower UIC critical interrupt\n");
355 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); 345 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
356 uic->uicvr = 0x00000000; 346 uic->uicvr = 0x00000000;
357 } 347 }
@@ -364,14 +354,10 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) @@ -364,14 +354,10 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
364 354
365 uic = opaque; 355 uic = opaque;
366 mask = 1 << (31-irq_num); 356 mask = 1 << (31-irq_num);
367 -#ifdef DEBUG_UIC  
368 - if (loglevel & CPU_LOG_INT) {  
369 - fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32 357 + LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
370 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", 358 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
371 __func__, irq_num, level, 359 __func__, irq_num, level,
372 uic->uicsr, mask, uic->uicsr & mask, level << irq_num); 360 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
373 - }  
374 -#endif  
375 if (irq_num < 0 || irq_num > 31) 361 if (irq_num < 0 || irq_num > 31)
376 return; 362 return;
377 sr = uic->uicsr; 363 sr = uic->uicsr;
@@ -391,12 +377,8 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) @@ -391,12 +377,8 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
391 uic->level &= ~mask; 377 uic->level &= ~mask;
392 } 378 }
393 } 379 }
394 -#ifdef DEBUG_UIC  
395 - if (loglevel & CPU_LOG_INT) {  
396 - fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => " 380 + LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
397 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); 381 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
398 - }  
399 -#endif  
400 if (sr != uic->uicsr) 382 if (sr != uic->uicsr)
401 ppcuic_trigger_irq(uic); 383 ppcuic_trigger_irq(uic);
402 } 384 }
@@ -453,11 +435,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) @@ -453,11 +435,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
453 435
454 uic = opaque; 436 uic = opaque;
455 dcrn -= uic->dcr_base; 437 dcrn -= uic->dcr_base;
456 -#ifdef DEBUG_UIC  
457 - if (loglevel & CPU_LOG_INT) {  
458 - fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);  
459 - }  
460 -#endif 438 + LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
461 switch (dcrn) { 439 switch (dcrn) {
462 case DCR_UICSR: 440 case DCR_UICSR:
463 uic->uicsr &= ~val; 441 uic->uicsr &= ~val;
@@ -47,6 +47,22 @@ @@ -47,6 +47,22 @@
47 #define DEBUG 47 #define DEBUG
48 //#define PROFILE 48 //#define PROFILE
49 49
  50 +
  51 +#ifdef DEBUG
  52 +# define LOG_INT(...) do { \
  53 + if (loglevel & CPU_LOG_INT) \
  54 + fprintf(logfile, ## __VA_ARGS__); \
  55 + } while (0)
  56 +# define LOG_INT_STATE(env) \
  57 + do { \
  58 + if (loglevel & CPU_LOG_INT) \
  59 + cpu_dump_state(env, logfile, fprintf, 0); \
  60 + } while (0)
  61 +#else
  62 +# define LOG_INT(...) do { } while (0)
  63 +# define LOG_INT_STATE(env) do { } while (0)
  64 +#endif
  65 +
50 #include <unistd.h> 66 #include <unistd.h>
51 #include <fcntl.h> 67 #include <fcntl.h>
52 #include "kqemu.h" 68 #include "kqemu.h"
@@ -241,11 +257,7 @@ int kqemu_init(CPUState *env) @@ -241,11 +257,7 @@ int kqemu_init(CPUState *env)
241 257
242 void kqemu_flush_page(CPUState *env, target_ulong addr) 258 void kqemu_flush_page(CPUState *env, target_ulong addr)
243 { 259 {
244 -#if defined(DEBUG)  
245 - if (loglevel & CPU_LOG_INT) {  
246 - fprintf(logfile, "kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);  
247 - }  
248 -#endif 260 + LOG_INT("kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);
249 if (nb_pages_to_flush >= KQEMU_MAX_PAGES_TO_FLUSH) 261 if (nb_pages_to_flush >= KQEMU_MAX_PAGES_TO_FLUSH)
250 nb_pages_to_flush = KQEMU_FLUSH_ALL; 262 nb_pages_to_flush = KQEMU_FLUSH_ALL;
251 else 263 else
@@ -254,22 +266,14 @@ void kqemu_flush_page(CPUState *env, target_ulong addr) @@ -254,22 +266,14 @@ void kqemu_flush_page(CPUState *env, target_ulong addr)
254 266
255 void kqemu_flush(CPUState *env, int global) 267 void kqemu_flush(CPUState *env, int global)
256 { 268 {
257 -#ifdef DEBUG  
258 - if (loglevel & CPU_LOG_INT) {  
259 - fprintf(logfile, "kqemu_flush:\n");  
260 - }  
261 -#endif 269 + LOG_INT("kqemu_flush:\n");
262 nb_pages_to_flush = KQEMU_FLUSH_ALL; 270 nb_pages_to_flush = KQEMU_FLUSH_ALL;
263 } 271 }
264 272
265 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr) 273 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr)
266 { 274 {
267 -#ifdef DEBUG  
268 - if (loglevel & CPU_LOG_INT) {  
269 - fprintf(logfile, "kqemu_set_notdirty: addr=%08lx\n", 275 + LOG_INT("kqemu_set_notdirty: addr=%08lx\n",
270 (unsigned long)ram_addr); 276 (unsigned long)ram_addr);
271 - }  
272 -#endif  
273 /* we only track transitions to dirty state */ 277 /* we only track transitions to dirty state */
274 if (phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] != 0xff) 278 if (phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] != 0xff)
275 return; 279 return;
@@ -703,12 +707,8 @@ int kqemu_cpu_exec(CPUState *env) @@ -703,12 +707,8 @@ int kqemu_cpu_exec(CPUState *env)
703 #ifdef CONFIG_PROFILER 707 #ifdef CONFIG_PROFILER
704 ti = profile_getclock(); 708 ti = profile_getclock();
705 #endif 709 #endif
706 -#ifdef DEBUG  
707 - if (loglevel & CPU_LOG_INT) {  
708 - fprintf(logfile, "kqemu: cpu_exec: enter\n");  
709 - cpu_dump_state(env, logfile, fprintf, 0);  
710 - }  
711 -#endif 710 + LOG_INT("kqemu: cpu_exec: enter\n");
  711 + LOG_INT_STATE(env);
712 for(i = 0; i < CPU_NB_REGS; i++) 712 for(i = 0; i < CPU_NB_REGS; i++)
713 kenv->regs[i] = env->regs[i]; 713 kenv->regs[i] = env->regs[i];
714 kenv->eip = env->eip; 714 kenv->eip = env->eip;
@@ -867,11 +867,7 @@ int kqemu_cpu_exec(CPUState *env) @@ -867,11 +867,7 @@ int kqemu_cpu_exec(CPUState *env)
867 else 867 else
868 env->hflags &= ~HF_OSFXSR_MASK; 868 env->hflags &= ~HF_OSFXSR_MASK;
869 869
870 -#ifdef DEBUG  
871 - if (loglevel & CPU_LOG_INT) {  
872 - fprintf(logfile, "kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);  
873 - }  
874 -#endif 870 + LOG_INT("kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
875 if (ret == KQEMU_RET_SYSCALL) { 871 if (ret == KQEMU_RET_SYSCALL) {
876 /* syscall instruction */ 872 /* syscall instruction */
877 return do_syscall(env, kenv); 873 return do_syscall(env, kenv);
@@ -884,13 +880,8 @@ int kqemu_cpu_exec(CPUState *env) @@ -884,13 +880,8 @@ int kqemu_cpu_exec(CPUState *env)
884 #ifdef CONFIG_PROFILER 880 #ifdef CONFIG_PROFILER
885 kqemu_ret_int_count++; 881 kqemu_ret_int_count++;
886 #endif 882 #endif
887 -#ifdef DEBUG  
888 - if (loglevel & CPU_LOG_INT) {  
889 - fprintf(logfile, "kqemu: interrupt v=%02x:\n",  
890 - env->exception_index);  
891 - cpu_dump_state(env, logfile, fprintf, 0);  
892 - }  
893 -#endif 883 + LOG_INT("kqemu: interrupt v=%02x:\n", env->exception_index);
  884 + LOG_INT_STATE(env);
894 return 1; 885 return 1;
895 } else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) { 886 } else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) {
896 env->exception_index = ret & 0xff; 887 env->exception_index = ret & 0xff;
@@ -900,23 +891,15 @@ int kqemu_cpu_exec(CPUState *env) @@ -900,23 +891,15 @@ int kqemu_cpu_exec(CPUState *env)
900 #ifdef CONFIG_PROFILER 891 #ifdef CONFIG_PROFILER
901 kqemu_ret_excp_count++; 892 kqemu_ret_excp_count++;
902 #endif 893 #endif
903 -#ifdef DEBUG  
904 - if (loglevel & CPU_LOG_INT) {  
905 - fprintf(logfile, "kqemu: exception v=%02x e=%04x:\n", 894 + LOG_INT("kqemu: exception v=%02x e=%04x:\n",
906 env->exception_index, env->error_code); 895 env->exception_index, env->error_code);
907 - cpu_dump_state(env, logfile, fprintf, 0);  
908 - }  
909 -#endif 896 + LOG_INT_STATE(env);
910 return 1; 897 return 1;
911 } else if (ret == KQEMU_RET_INTR) { 898 } else if (ret == KQEMU_RET_INTR) {
912 #ifdef CONFIG_PROFILER 899 #ifdef CONFIG_PROFILER
913 kqemu_ret_intr_count++; 900 kqemu_ret_intr_count++;
914 #endif 901 #endif
915 -#ifdef DEBUG  
916 - if (loglevel & CPU_LOG_INT) {  
917 - cpu_dump_state(env, logfile, fprintf, 0);  
918 - }  
919 -#endif 902 + LOG_INT_STATE(env);
920 return 0; 903 return 0;
921 } else if (ret == KQEMU_RET_SOFTMMU) { 904 } else if (ret == KQEMU_RET_SOFTMMU) {
922 #ifdef CONFIG_PROFILER 905 #ifdef CONFIG_PROFILER
@@ -925,11 +908,7 @@ int kqemu_cpu_exec(CPUState *env) @@ -925,11 +908,7 @@ int kqemu_cpu_exec(CPUState *env)
925 kqemu_record_pc(pc); 908 kqemu_record_pc(pc);
926 } 909 }
927 #endif 910 #endif
928 -#ifdef DEBUG  
929 - if (loglevel & CPU_LOG_INT) {  
930 - cpu_dump_state(env, logfile, fprintf, 0);  
931 - }  
932 -#endif 911 + LOG_INT_STATE(env);
933 return 2; 912 return 2;
934 } else { 913 } else {
935 cpu_dump_state(env, stderr, fprintf, 0); 914 cpu_dump_state(env, stderr, fprintf, 0);
linux-user/vm86.c
  View file @d12d51d
@@ -29,6 +29,13 @@ @@ -29,6 +29,13 @@
29 29
30 //#define DEBUG_VM86 30 //#define DEBUG_VM86
31 31
  32 +#ifdef DEBUG_VM86
  33 +# define LOG_VM86(...) fprintf(logfile, ## __VA_ARGS__);
  34 +#else
  35 +# define LOG_VM86(...) do { } while (0)
  36 +#endif
  37 +
  38 +
32 #define set_flags(X,new,mask) \ 39 #define set_flags(X,new,mask) \
33 ((X) = ((X) & ~(mask)) | ((new) & (mask))) 40 ((X) = ((X) & ~(mask)) | ((new) & (mask)))
34 41
@@ -92,10 +99,8 @@ void save_v86_state(CPUX86State *env) @@ -92,10 +99,8 @@ void save_v86_state(CPUX86State *env)
92 set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask); 99 set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
93 target_v86->regs.eflags = tswap32(env->eflags); 100 target_v86->regs.eflags = tswap32(env->eflags);
94 unlock_user_struct(target_v86, ts->target_v86, 1); 101 unlock_user_struct(target_v86, ts->target_v86, 1);
95 -#ifdef DEBUG_VM86  
96 - fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",  
97 - env->eflags, env->segs[R_CS].selector, env->eip);  
98 -#endif 102 + LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
  103 + env->eflags, env->segs[R_CS].selector, env->eip);
99 104
100 /* restore 32 bit registers */ 105 /* restore 32 bit registers */
101 env->regs[R_EAX] = ts->vm86_saved_regs.eax; 106 env->regs[R_EAX] = ts->vm86_saved_regs.eax;
@@ -121,9 +126,7 @@ void save_v86_state(CPUX86State *env) @@ -121,9 +126,7 @@ void save_v86_state(CPUX86State *env)
121 'retval' */ 126 'retval' */
122 static inline void return_to_32bit(CPUX86State *env, int retval) 127 static inline void return_to_32bit(CPUX86State *env, int retval)
123 { 128 {
124 -#ifdef DEBUG_VM86  
125 - fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval);  
126 -#endif 129 + LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
127 save_v86_state(env); 130 save_v86_state(env);
128 env->regs[R_EAX] = retval; 131 env->regs[R_EAX] = retval;
129 } 132 }
@@ -216,10 +219,8 @@ static void do_int(CPUX86State *env, int intno) @@ -216,10 +219,8 @@ static void do_int(CPUX86State *env, int intno)
216 segoffs = ldl(int_addr); 219 segoffs = ldl(int_addr);
217 if ((segoffs >> 16) == TARGET_BIOSSEG) 220 if ((segoffs >> 16) == TARGET_BIOSSEG)
218 goto cannot_handle; 221 goto cannot_handle;
219 -#if defined(DEBUG_VM86)  
220 - fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",  
221 - intno, segoffs >> 16, segoffs & 0xffff);  
222 -#endif 222 + LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
  223 + intno, segoffs >> 16, segoffs & 0xffff);
223 /* save old state */ 224 /* save old state */
224 ssp = env->segs[R_SS].selector << 4; 225 ssp = env->segs[R_SS].selector << 4;
225 sp = env->regs[R_ESP] & 0xffff; 226 sp = env->regs[R_ESP] & 0xffff;
@@ -235,9 +236,7 @@ static void do_int(CPUX86State *env, int intno) @@ -235,9 +236,7 @@ static void do_int(CPUX86State *env, int intno)
235 clear_AC(env); 236 clear_AC(env);
236 return; 237 return;
237 cannot_handle: 238 cannot_handle:
238 -#if defined(DEBUG_VM86)  
239 - fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno);  
240 -#endif 239 + LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
241 return_to_32bit(env, TARGET_VM86_INTx | (intno << 8)); 240 return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
242 } 241 }
243 242
@@ -274,10 +273,8 @@ void handle_vm86_fault(CPUX86State *env) @@ -274,10 +273,8 @@ void handle_vm86_fault(CPUX86State *env)
274 ssp = env->segs[R_SS].selector << 4; 273 ssp = env->segs[R_SS].selector << 4;
275 sp = env->regs[R_ESP] & 0xffff; 274 sp = env->regs[R_ESP] & 0xffff;
276 275
277 -#if defined(DEBUG_VM86)  
278 - fprintf(logfile, "VM86 exception %04x:%08x\n",  
279 - env->segs[R_CS].selector, env->eip);  
280 -#endif 276 + LOG_VM86("VM86 exception %04x:%08x\n",
  277 + env->segs[R_CS].selector, env->eip);
281 278
282 data32 = 0; 279 data32 = 0;
283 pref_done = 0; 280 pref_done = 0;
@@ -478,10 +475,8 @@ int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) @@ -478,10 +475,8 @@ int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
478 target_v86->vm86plus.vm86dbg_intxxtab, 32); 475 target_v86->vm86plus.vm86dbg_intxxtab, 32);
479 unlock_user_struct(target_v86, vm86_addr, 0); 476 unlock_user_struct(target_v86, vm86_addr, 0);
480 477
481 -#ifdef DEBUG_VM86  
482 - fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n",  
483 - env->segs[R_CS].selector, env->eip);  
484 -#endif 478 + LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
  479 + env->segs[R_CS].selector, env->eip);
485 /* now the virtual CPU is ready for vm86 execution ! */ 480 /* now the virtual CPU is ready for vm86 execution ! */
486 out: 481 out:
487 return ret; 482 return ret;
target-alpha/translate.c
  View file @d12d51d
@@ -37,6 +37,16 @@ @@ -37,6 +37,16 @@
37 #define ALPHA_DEBUG_DISAS 37 #define ALPHA_DEBUG_DISAS
38 /* #define DO_TB_FLUSH */ 38 /* #define DO_TB_FLUSH */
39 39
  40 +
  41 +#ifdef ALPHA_DEBUG_DISAS
  42 +# define LOG_DISAS(...) do { \
  43 + if (logfile) \
  44 + fprintf(logfile, ## __VA_ARGS__); \
  45 + } while (0)
  46 +#else
  47 +# define LOG_DISAS(...) do { } while (0)
  48 +#endif
  49 +
40 typedef struct DisasContext DisasContext; 50 typedef struct DisasContext DisasContext;
41 struct DisasContext { 51 struct DisasContext {
42 uint64_t pc; 52 uint64_t pc;
@@ -671,12 +681,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) @@ -671,12 +681,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
671 fn7 = (insn >> 5) & 0x0000007F; 681 fn7 = (insn >> 5) & 0x0000007F;
672 fn2 = (insn >> 5) & 0x00000003; 682 fn2 = (insn >> 5) & 0x00000003;
673 ret = 0; 683 ret = 0;
674 -#if defined ALPHA_DEBUG_DISAS  
675 - if (logfile != NULL) {  
676 - fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",  
677 - opc, ra, rb, rc, disp16);  
678 - }  
679 -#endif 684 + LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n",
  685 + opc, ra, rb, rc, disp16);
680 switch (opc) { 686 switch (opc) {
681 case 0x00: 687 case 0x00:
682 /* CALL_PAL */ 688 /* CALL_PAL */
@@ -2386,17 +2392,13 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -2386,17 +2392,13 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
2386 gen_io_start(); 2392 gen_io_start();
2387 #if defined ALPHA_DEBUG_DISAS 2393 #if defined ALPHA_DEBUG_DISAS
2388 insn_count++; 2394 insn_count++;
2389 - if (logfile != NULL) {  
2390 - fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",  
2391 - ctx.pc, ctx.mem_idx);  
2392 - } 2395 + LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n",
  2396 + ctx.pc, ctx.mem_idx);
2393 #endif 2397 #endif
2394 insn = ldl_code(ctx.pc); 2398 insn = ldl_code(ctx.pc);
2395 #if defined ALPHA_DEBUG_DISAS 2399 #if defined ALPHA_DEBUG_DISAS
2396 insn_count++; 2400 insn_count++;
2397 - if (logfile != NULL) {  
2398 - fprintf(logfile, "opcode %08x %d\n", insn, insn_count);  
2399 - } 2401 + LOG_DISAS("opcode %08x %d\n", insn, insn_count);
2400 #endif 2402 #endif
2401 num_insns++; 2403 num_insns++;
2402 ctx.pc += 4; 2404 ctx.pc += 4;
target-cris/helper.c
  View file @d12d51d
@@ -28,7 +28,17 @@ @@ -28,7 +28,17 @@
28 #include "exec-all.h" 28 #include "exec-all.h"
29 #include "host-utils.h" 29 #include "host-utils.h"
30 30
  31 +
  32 +//#define CRIS_HELPER_DEBUG
  33 +
  34 +
  35 +#ifdef CRIS_HELPER_DEBUG
  36 +#define D(x) x
  37 +#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
  38 +#else
31 #define D(x) 39 #define D(x)
  40 +#define D_LOG(...) do { } while (0)
  41 +#endif
32 42
33 #if defined(CONFIG_USER_ONLY) 43 #if defined(CONFIG_USER_ONLY)
34 44
@@ -98,10 +108,10 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, @@ -98,10 +108,10 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
98 r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); 108 r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
99 } 109 }
100 if (r > 0) 110 if (r > 0)
101 - D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x" 111 + D_LOG("%s returns %d irqreq=%x addr=%x"
102 " phy=%x ismmu=%d vec=%x pc=%x\n", 112 " phy=%x ismmu=%d vec=%x pc=%x\n",
103 __func__, r, env->interrupt_request, 113 __func__, r, env->interrupt_request,
104 - address, res.phy, is_softmmu, res.bf_vec, env->pc)); 114 + address, res.phy, is_softmmu, res.bf_vec, env->pc);
105 return r; 115 return r;
106 } 116 }
107 117
@@ -109,9 +119,9 @@ void do_interrupt(CPUState *env) @@ -109,9 +119,9 @@ void do_interrupt(CPUState *env)
109 { 119 {
110 int ex_vec = -1; 120 int ex_vec = -1;
111 121
112 - D(fprintf (logfile, "exception index=%d interrupt_req=%d\n", 122 + D_LOG( "exception index=%d interrupt_req=%d\n",
113 env->exception_index, 123 env->exception_index,
114 - env->interrupt_request)); 124 + env->interrupt_request);
115 125
116 switch (env->exception_index) 126 switch (env->exception_index)
117 { 127 {
@@ -147,13 +157,13 @@ void do_interrupt(CPUState *env) @@ -147,13 +157,13 @@ void do_interrupt(CPUState *env)
147 env->pregs[PR_EXS] = (ex_vec & 0xff) << 8; 157 env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
148 158
149 if (env->dslot) { 159 if (env->dslot) {
150 - D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x" 160 + D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
151 " ERP=%x pid=%x ccs=%x cc=%d %x\n", 161 " ERP=%x pid=%x ccs=%x cc=%d %x\n",
152 ex_vec, env->pc, env->dslot, 162 ex_vec, env->pc, env->dslot,
153 env->regs[R_SP], 163 env->regs[R_SP],
154 env->pregs[PR_ERP], env->pregs[PR_PID], 164 env->pregs[PR_ERP], env->pregs[PR_PID],
155 env->pregs[PR_CCS], 165 env->pregs[PR_CCS],
156 - env->cc_op, env->cc_mask)); 166 + env->cc_op, env->cc_mask);
157 /* We loose the btarget, btaken state here so rexec the 167 /* We loose the btarget, btaken state here so rexec the
158 branch. */ 168 branch. */
159 env->pregs[PR_ERP] -= env->dslot; 169 env->pregs[PR_ERP] -= env->dslot;
@@ -171,11 +181,11 @@ void do_interrupt(CPUState *env) @@ -171,11 +181,11 @@ void do_interrupt(CPUState *env)
171 181
172 /* Apply the CRIS CCS shift. Clears U if set. */ 182 /* Apply the CRIS CCS shift. Clears U if set. */
173 cris_shift_ccs(env); 183 cris_shift_ccs(env);
174 - D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", 184 + D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
175 __func__, env->pc, ex_vec, 185 __func__, env->pc, ex_vec,
176 env->pregs[PR_CCS], 186 env->pregs[PR_CCS],
177 env->pregs[PR_PID], 187 env->pregs[PR_PID],
178 - env->pregs[PR_ERP])); 188 + env->pregs[PR_ERP]);
179 } 189 }
180 190
181 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) 191 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
target-cris/mmu.c
  View file @d12d51d
@@ -32,8 +32,10 @@ @@ -32,8 +32,10 @@
32 32
33 #ifdef DEBUG 33 #ifdef DEBUG
34 #define D(x) x 34 #define D(x) x
  35 +#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
35 #else 36 #else
36 #define D(x) 37 #define D(x)
  38 +#define D_LOG(...) do { } while (0)
37 #endif 39 #endif
38 40
39 void cris_mmu_init(CPUState *env) 41 void cris_mmu_init(CPUState *env)
@@ -180,9 +182,8 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res, @@ -180,9 +182,8 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
180 tlb_pid = EXTRACT_FIELD(hi, 0, 7); 182 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
181 tlb_g = EXTRACT_FIELD(lo, 4, 4); 183 tlb_g = EXTRACT_FIELD(lo, 4, 4);
182 184
183 - D(fprintf(logfile,  
184 - "TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",  
185 - mmu, set, idx, tlb_vpn, vpage, lo, hi)); 185 + D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
  186 + mmu, set, idx, tlb_vpn, vpage, lo, hi);
186 if ((tlb_g || (tlb_pid == pid)) 187 if ((tlb_g || (tlb_pid == pid))
187 && tlb_vpn == vpage) { 188 && tlb_vpn == vpage) {
188 match = 1; 189 match = 1;
@@ -314,9 +315,8 @@ void cris_mmu_flush_pid(CPUState *env, uint32_t pid) @@ -314,9 +315,8 @@ void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
314 315
315 if (tlb_v && !tlb_g && (tlb_pid == pid)) { 316 if (tlb_v && !tlb_g && (tlb_pid == pid)) {
316 vaddr = tlb_vpn << TARGET_PAGE_BITS; 317 vaddr = tlb_vpn << TARGET_PAGE_BITS;
317 - D(fprintf(logfile,  
318 - "flush pid=%x vaddr=%x\n",  
319 - pid, vaddr)); 318 + D_LOG("flush pid=%x vaddr=%x\n",
  319 + pid, vaddr);
320 tlb_flush_page(env, vaddr); 320 tlb_flush_page(env, vaddr);
321 } 321 }
322 } 322 }
target-cris/op_helper.c
  View file @d12d51d
@@ -25,7 +25,16 @@ @@ -25,7 +25,16 @@
25 #include "helper.h" 25 #include "helper.h"
26 #include "host-utils.h" 26 #include "host-utils.h"
27 27
  28 +//#define CRIS_OP_HELPER_DEBUG
  29 +
  30 +
  31 +#ifdef CRIS_OP_HELPER_DEBUG
  32 +#define D(x) x
  33 +#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
  34 +#else
28 #define D(x) 35 #define D(x)
  36 +#define D_LOG(...) do { } while (0)
  37 +#endif
29 38
30 #if !defined(CONFIG_USER_ONLY) 39 #if !defined(CONFIG_USER_ONLY)
31 40
@@ -59,8 +68,8 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) @@ -59,8 +68,8 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
59 saved_env = env; 68 saved_env = env;
60 env = cpu_single_env; 69 env = cpu_single_env;
61 70
62 - D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__,  
63 - env->pc, env->debug1, retaddr)); 71 + D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
  72 + env->pc, env->debug1, retaddr);
64 ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); 73 ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
65 if (unlikely(ret)) { 74 if (unlikely(ret)) {
66 if (retaddr) { 75 if (retaddr) {
@@ -155,9 +164,8 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg) @@ -155,9 +164,8 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
155 env->tlbsets[srs - 1][set][idx].lo = lo; 164 env->tlbsets[srs - 1][set][idx].lo = lo;
156 env->tlbsets[srs - 1][set][idx].hi = hi; 165 env->tlbsets[srs - 1][set][idx].hi = hi;
157 166
158 - D(fprintf(logfile,  
159 - "tlb flush vaddr=%x v=%d pc=%x\n",  
160 - vaddr, tlb_v, env->pc)); 167 + D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
  168 + vaddr, tlb_v, env->pc);
161 tlb_flush_page(env, vaddr); 169 tlb_flush_page(env, vaddr);
162 } 170 }
163 } 171 }
@@ -213,10 +221,10 @@ void helper_rfe(void) @@ -213,10 +221,10 @@ void helper_rfe(void)
213 { 221 {
214 int rflag = env->pregs[PR_CCS] & R_FLAG; 222 int rflag = env->pregs[PR_CCS] & R_FLAG;
215 223
216 - D(fprintf(logfile, "rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 224 + D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
217 env->pregs[PR_ERP], env->pregs[PR_PID], 225 env->pregs[PR_ERP], env->pregs[PR_PID],
218 env->pregs[PR_CCS], 226 env->pregs[PR_CCS],
219 - env->btarget)); 227 + env->btarget);
220 228
221 cris_ccs_rshift(env); 229 cris_ccs_rshift(env);
222 230
@@ -229,10 +237,10 @@ void helper_rfn(void) @@ -229,10 +237,10 @@ void helper_rfn(void)
229 { 237 {
230 int rflag = env->pregs[PR_CCS] & R_FLAG; 238 int rflag = env->pregs[PR_CCS] & R_FLAG;
231 239
232 - D(fprintf(logfile, "rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 240 + D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
233 env->pregs[PR_ERP], env->pregs[PR_PID], 241 env->pregs[PR_ERP], env->pregs[PR_PID],
234 env->pregs[PR_CCS], 242 env->pregs[PR_CCS],
235 - env->btarget)); 243 + env->btarget);
236 244
237 cris_ccs_rshift(env); 245 cris_ccs_rshift(env);
238 246
target-cris/translate.c
  View file @d12d51d
@@ -44,9 +44,12 @@ @@ -44,9 +44,12 @@
44 44
45 #define DISAS_CRIS 0 45 #define DISAS_CRIS 0
46 #if DISAS_CRIS 46 #if DISAS_CRIS
47 -#define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x 47 +# define LOG_DIS(...) do { \
  48 + if (loglevel & CPU_LOG_TB_IN_ASM) \
  49 + fprintf(logfile, ## __VA_ARGS__); \
  50 + } while (0)
48 #else 51 #else
49 -#define DIS(x) 52 +# define LOG_DIS(...) do { } while (0)
50 #endif 53 #endif
51 54
52 #define D(x) 55 #define D(x)
@@ -1344,7 +1347,7 @@ static unsigned int dec_bccq(DisasContext *dc) @@ -1344,7 +1347,7 @@ static unsigned int dec_bccq(DisasContext *dc)
1344 tmp = offset; 1347 tmp = offset;
1345 offset = sign_extend(offset, 8); 1348 offset = sign_extend(offset, 8);
1346 1349
1347 - DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset)); 1350 + LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1348 1351
1349 /* op2 holds the condition-code. */ 1352 /* op2 holds the condition-code. */
1350 cris_cc_mask(dc, 0); 1353 cris_cc_mask(dc, 0);
@@ -1358,7 +1361,7 @@ static unsigned int dec_addoq(DisasContext *dc) @@ -1358,7 +1361,7 @@ static unsigned int dec_addoq(DisasContext *dc)
1358 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); 1361 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1359 imm = sign_extend(dc->op1, 7); 1362 imm = sign_extend(dc->op1, 7);
1360 1363
1361 - DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2)); 1364 + LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1362 cris_cc_mask(dc, 0); 1365 cris_cc_mask(dc, 0);
1363 /* Fetch register operand, */ 1366 /* Fetch register operand, */
1364 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); 1367 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
@@ -1367,7 +1370,7 @@ static unsigned int dec_addoq(DisasContext *dc) @@ -1367,7 +1370,7 @@ static unsigned int dec_addoq(DisasContext *dc)
1367 } 1370 }
1368 static unsigned int dec_addq(DisasContext *dc) 1371 static unsigned int dec_addq(DisasContext *dc)
1369 { 1372 {
1370 - DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2)); 1373 + LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1371 1374
1372 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1375 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1373 1376
@@ -1383,7 +1386,7 @@ static unsigned int dec_moveq(DisasContext *dc) @@ -1383,7 +1386,7 @@ static unsigned int dec_moveq(DisasContext *dc)
1383 1386
1384 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1387 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1385 imm = sign_extend(dc->op1, 5); 1388 imm = sign_extend(dc->op1, 5);
1386 - DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2)); 1389 + LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1387 1390
1388 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm)); 1391 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1389 return 2; 1392 return 2;
@@ -1392,7 +1395,7 @@ static unsigned int dec_subq(DisasContext *dc) @@ -1392,7 +1395,7 @@ static unsigned int dec_subq(DisasContext *dc)
1392 { 1395 {
1393 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1396 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1394 1397
1395 - DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2)); 1398 + LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1396 1399
1397 cris_cc_mask(dc, CC_MASK_NZVC); 1400 cris_cc_mask(dc, CC_MASK_NZVC);
1398 cris_alu(dc, CC_OP_SUB, 1401 cris_alu(dc, CC_OP_SUB,
@@ -1405,7 +1408,7 @@ static unsigned int dec_cmpq(DisasContext *dc) @@ -1405,7 +1408,7 @@ static unsigned int dec_cmpq(DisasContext *dc)
1405 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1408 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1406 imm = sign_extend(dc->op1, 5); 1409 imm = sign_extend(dc->op1, 5);
1407 1410
1408 - DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2)); 1411 + LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1409 cris_cc_mask(dc, CC_MASK_NZVC); 1412 cris_cc_mask(dc, CC_MASK_NZVC);
1410 1413
1411 cris_alu(dc, CC_OP_CMP, 1414 cris_alu(dc, CC_OP_CMP,
@@ -1418,7 +1421,7 @@ static unsigned int dec_andq(DisasContext *dc) @@ -1418,7 +1421,7 @@ static unsigned int dec_andq(DisasContext *dc)
1418 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1421 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1419 imm = sign_extend(dc->op1, 5); 1422 imm = sign_extend(dc->op1, 5);
1420 1423
1421 - DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2)); 1424 + LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1422 cris_cc_mask(dc, CC_MASK_NZ); 1425 cris_cc_mask(dc, CC_MASK_NZ);
1423 1426
1424 cris_alu(dc, CC_OP_AND, 1427 cris_alu(dc, CC_OP_AND,
@@ -1430,7 +1433,7 @@ static unsigned int dec_orq(DisasContext *dc) @@ -1430,7 +1433,7 @@ static unsigned int dec_orq(DisasContext *dc)
1430 uint32_t imm; 1433 uint32_t imm;
1431 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1434 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1432 imm = sign_extend(dc->op1, 5); 1435 imm = sign_extend(dc->op1, 5);
1433 - DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2)); 1436 + LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1434 cris_cc_mask(dc, CC_MASK_NZ); 1437 cris_cc_mask(dc, CC_MASK_NZ);
1435 1438
1436 cris_alu(dc, CC_OP_OR, 1439 cris_alu(dc, CC_OP_OR,
@@ -1440,7 +1443,7 @@ static unsigned int dec_orq(DisasContext *dc) @@ -1440,7 +1443,7 @@ static unsigned int dec_orq(DisasContext *dc)
1440 static unsigned int dec_btstq(DisasContext *dc) 1443 static unsigned int dec_btstq(DisasContext *dc)
1441 { 1444 {
1442 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1443 - DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2)); 1446 + LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1444 1447
1445 cris_cc_mask(dc, CC_MASK_NZ); 1448 cris_cc_mask(dc, CC_MASK_NZ);
1446 cris_evaluate_flags(dc); 1449 cris_evaluate_flags(dc);
@@ -1455,7 +1458,7 @@ static unsigned int dec_btstq(DisasContext *dc) @@ -1455,7 +1458,7 @@ static unsigned int dec_btstq(DisasContext *dc)
1455 static unsigned int dec_asrq(DisasContext *dc) 1458 static unsigned int dec_asrq(DisasContext *dc)
1456 { 1459 {
1457 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1460 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1458 - DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2)); 1461 + LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1459 cris_cc_mask(dc, CC_MASK_NZ); 1462 cris_cc_mask(dc, CC_MASK_NZ);
1460 1463
1461 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); 1464 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
@@ -1467,7 +1470,7 @@ static unsigned int dec_asrq(DisasContext *dc) @@ -1467,7 +1470,7 @@ static unsigned int dec_asrq(DisasContext *dc)
1467 static unsigned int dec_lslq(DisasContext *dc) 1470 static unsigned int dec_lslq(DisasContext *dc)
1468 { 1471 {
1469 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1472 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1470 - DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2)); 1473 + LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1471 1474
1472 cris_cc_mask(dc, CC_MASK_NZ); 1475 cris_cc_mask(dc, CC_MASK_NZ);
1473 1476
@@ -1481,7 +1484,7 @@ static unsigned int dec_lslq(DisasContext *dc) @@ -1481,7 +1484,7 @@ static unsigned int dec_lslq(DisasContext *dc)
1481 static unsigned int dec_lsrq(DisasContext *dc) 1484 static unsigned int dec_lsrq(DisasContext *dc)
1482 { 1485 {
1483 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1486 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1484 - DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2)); 1487 + LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1485 1488
1486 cris_cc_mask(dc, CC_MASK_NZ); 1489 cris_cc_mask(dc, CC_MASK_NZ);
1487 1490
@@ -1496,8 +1499,8 @@ static unsigned int dec_move_r(DisasContext *dc) @@ -1496,8 +1499,8 @@ static unsigned int dec_move_r(DisasContext *dc)
1496 { 1499 {
1497 int size = memsize_zz(dc); 1500 int size = memsize_zz(dc);
1498 1501
1499 - DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",  
1500 - memsize_char(size), dc->op1, dc->op2)); 1502 + LOG_DIS("move.%c $r%u, $r%u\n",
  1503 + memsize_char(size), dc->op1, dc->op2);
1501 1504
1502 cris_cc_mask(dc, CC_MASK_NZ); 1505 cris_cc_mask(dc, CC_MASK_NZ);
1503 if (size == 4) { 1506 if (size == 4) {
@@ -1524,8 +1527,8 @@ static unsigned int dec_scc_r(DisasContext *dc) @@ -1524,8 +1527,8 @@ static unsigned int dec_scc_r(DisasContext *dc)
1524 { 1527 {
1525 int cond = dc->op2; 1528 int cond = dc->op2;
1526 1529
1527 - DIS(fprintf (logfile, "s%s $r%u\n",  
1528 - cc_name(cond), dc->op1)); 1530 + LOG_DIS("s%s $r%u\n",
  1531 + cc_name(cond), dc->op1);
1529 1532
1530 if (cond != CC_A) 1533 if (cond != CC_A)
1531 { 1534 {
@@ -1568,8 +1571,8 @@ static unsigned int dec_and_r(DisasContext *dc) @@ -1568,8 +1571,8 @@ static unsigned int dec_and_r(DisasContext *dc)
1568 TCGv t[2]; 1571 TCGv t[2];
1569 int size = memsize_zz(dc); 1572 int size = memsize_zz(dc);
1570 1573
1571 - DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",  
1572 - memsize_char(size), dc->op1, dc->op2)); 1574 + LOG_DIS("and.%c $r%u, $r%u\n",
  1575 + memsize_char(size), dc->op1, dc->op2);
1573 1576
1574 cris_cc_mask(dc, CC_MASK_NZ); 1577 cris_cc_mask(dc, CC_MASK_NZ);
1575 1578
@@ -1583,8 +1586,8 @@ static unsigned int dec_and_r(DisasContext *dc) @@ -1583,8 +1586,8 @@ static unsigned int dec_and_r(DisasContext *dc)
1583 static unsigned int dec_lz_r(DisasContext *dc) 1586 static unsigned int dec_lz_r(DisasContext *dc)
1584 { 1587 {
1585 TCGv t0; 1588 TCGv t0;
1586 - DIS(fprintf (logfile, "lz $r%u, $r%u\n",  
1587 - dc->op1, dc->op2)); 1589 + LOG_DIS("lz $r%u, $r%u\n",
  1590 + dc->op1, dc->op2);
1588 cris_cc_mask(dc, CC_MASK_NZ); 1591 cris_cc_mask(dc, CC_MASK_NZ);
1589 t0 = tcg_temp_new(); 1592 t0 = tcg_temp_new();
1590 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); 1593 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
@@ -1598,8 +1601,8 @@ static unsigned int dec_lsl_r(DisasContext *dc) @@ -1598,8 +1601,8 @@ static unsigned int dec_lsl_r(DisasContext *dc)
1598 TCGv t[2]; 1601 TCGv t[2];
1599 int size = memsize_zz(dc); 1602 int size = memsize_zz(dc);
1600 1603
1601 - DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",  
1602 - memsize_char(size), dc->op1, dc->op2)); 1604 + LOG_DIS("lsl.%c $r%u, $r%u\n",
  1605 + memsize_char(size), dc->op1, dc->op2);
1603 1606
1604 cris_cc_mask(dc, CC_MASK_NZ); 1607 cris_cc_mask(dc, CC_MASK_NZ);
1605 cris_alu_alloc_temps(dc, size, t); 1608 cris_alu_alloc_temps(dc, size, t);
@@ -1615,8 +1618,8 @@ static unsigned int dec_lsr_r(DisasContext *dc) @@ -1615,8 +1618,8 @@ static unsigned int dec_lsr_r(DisasContext *dc)
1615 TCGv t[2]; 1618 TCGv t[2];
1616 int size = memsize_zz(dc); 1619 int size = memsize_zz(dc);
1617 1620
1618 - DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",  
1619 - memsize_char(size), dc->op1, dc->op2)); 1621 + LOG_DIS("lsr.%c $r%u, $r%u\n",
  1622 + memsize_char(size), dc->op1, dc->op2);
1620 1623
1621 cris_cc_mask(dc, CC_MASK_NZ); 1624 cris_cc_mask(dc, CC_MASK_NZ);
1622 cris_alu_alloc_temps(dc, size, t); 1625 cris_alu_alloc_temps(dc, size, t);
@@ -1632,8 +1635,8 @@ static unsigned int dec_asr_r(DisasContext *dc) @@ -1632,8 +1635,8 @@ static unsigned int dec_asr_r(DisasContext *dc)
1632 TCGv t[2]; 1635 TCGv t[2];
1633 int size = memsize_zz(dc); 1636 int size = memsize_zz(dc);
1634 1637
1635 - DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",  
1636 - memsize_char(size), dc->op1, dc->op2)); 1638 + LOG_DIS("asr.%c $r%u, $r%u\n",
  1639 + memsize_char(size), dc->op1, dc->op2);
1637 1640
1638 cris_cc_mask(dc, CC_MASK_NZ); 1641 cris_cc_mask(dc, CC_MASK_NZ);
1639 cris_alu_alloc_temps(dc, size, t); 1642 cris_alu_alloc_temps(dc, size, t);
@@ -1649,8 +1652,8 @@ static unsigned int dec_muls_r(DisasContext *dc) @@ -1649,8 +1652,8 @@ static unsigned int dec_muls_r(DisasContext *dc)
1649 TCGv t[2]; 1652 TCGv t[2];
1650 int size = memsize_zz(dc); 1653 int size = memsize_zz(dc);
1651 1654
1652 - DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",  
1653 - memsize_char(size), dc->op1, dc->op2)); 1655 + LOG_DIS("muls.%c $r%u, $r%u\n",
  1656 + memsize_char(size), dc->op1, dc->op2);
1654 cris_cc_mask(dc, CC_MASK_NZV); 1657 cris_cc_mask(dc, CC_MASK_NZV);
1655 cris_alu_alloc_temps(dc, size, t); 1658 cris_alu_alloc_temps(dc, size, t);
1656 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); 1659 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
@@ -1665,8 +1668,8 @@ static unsigned int dec_mulu_r(DisasContext *dc) @@ -1665,8 +1668,8 @@ static unsigned int dec_mulu_r(DisasContext *dc)
1665 TCGv t[2]; 1668 TCGv t[2];
1666 int size = memsize_zz(dc); 1669 int size = memsize_zz(dc);
1667 1670
1668 - DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",  
1669 - memsize_char(size), dc->op1, dc->op2)); 1671 + LOG_DIS("mulu.%c $r%u, $r%u\n",
  1672 + memsize_char(size), dc->op1, dc->op2);
1670 cris_cc_mask(dc, CC_MASK_NZV); 1673 cris_cc_mask(dc, CC_MASK_NZV);
1671 cris_alu_alloc_temps(dc, size, t); 1674 cris_alu_alloc_temps(dc, size, t);
1672 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1675 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@@ -1679,7 +1682,7 @@ static unsigned int dec_mulu_r(DisasContext *dc) @@ -1679,7 +1682,7 @@ static unsigned int dec_mulu_r(DisasContext *dc)
1679 1682
1680 static unsigned int dec_dstep_r(DisasContext *dc) 1683 static unsigned int dec_dstep_r(DisasContext *dc)
1681 { 1684 {
1682 - DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2)); 1685 + LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1683 cris_cc_mask(dc, CC_MASK_NZ); 1686 cris_cc_mask(dc, CC_MASK_NZ);
1684 cris_alu(dc, CC_OP_DSTEP, 1687 cris_alu(dc, CC_OP_DSTEP,
1685 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); 1688 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
@@ -1690,8 +1693,8 @@ static unsigned int dec_xor_r(DisasContext *dc) @@ -1690,8 +1693,8 @@ static unsigned int dec_xor_r(DisasContext *dc)
1690 { 1693 {
1691 TCGv t[2]; 1694 TCGv t[2];
1692 int size = memsize_zz(dc); 1695 int size = memsize_zz(dc);
1693 - DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",  
1694 - memsize_char(size), dc->op1, dc->op2)); 1696 + LOG_DIS("xor.%c $r%u, $r%u\n",
  1697 + memsize_char(size), dc->op1, dc->op2);
1695 BUG_ON(size != 4); /* xor is dword. */ 1698 BUG_ON(size != 4); /* xor is dword. */
1696 cris_cc_mask(dc, CC_MASK_NZ); 1699 cris_cc_mask(dc, CC_MASK_NZ);
1697 cris_alu_alloc_temps(dc, size, t); 1700 cris_alu_alloc_temps(dc, size, t);
@@ -1706,8 +1709,8 @@ static unsigned int dec_bound_r(DisasContext *dc) @@ -1706,8 +1709,8 @@ static unsigned int dec_bound_r(DisasContext *dc)
1706 { 1709 {
1707 TCGv l0; 1710 TCGv l0;
1708 int size = memsize_zz(dc); 1711 int size = memsize_zz(dc);
1709 - DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",  
1710 - memsize_char(size), dc->op1, dc->op2)); 1712 + LOG_DIS("bound.%c $r%u, $r%u\n",
  1713 + memsize_char(size), dc->op1, dc->op2);
1711 cris_cc_mask(dc, CC_MASK_NZ); 1714 cris_cc_mask(dc, CC_MASK_NZ);
1712 l0 = tcg_temp_local_new(); 1715 l0 = tcg_temp_local_new();
1713 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); 1716 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
@@ -1720,8 +1723,8 @@ static unsigned int dec_cmp_r(DisasContext *dc) @@ -1720,8 +1723,8 @@ static unsigned int dec_cmp_r(DisasContext *dc)
1720 { 1723 {
1721 TCGv t[2]; 1724 TCGv t[2];
1722 int size = memsize_zz(dc); 1725 int size = memsize_zz(dc);
1723 - DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",  
1724 - memsize_char(size), dc->op1, dc->op2)); 1726 + LOG_DIS("cmp.%c $r%u, $r%u\n",
  1727 + memsize_char(size), dc->op1, dc->op2);
1725 cris_cc_mask(dc, CC_MASK_NZVC); 1728 cris_cc_mask(dc, CC_MASK_NZVC);
1726 cris_alu_alloc_temps(dc, size, t); 1729 cris_alu_alloc_temps(dc, size, t);
1727 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1730 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@@ -1735,8 +1738,8 @@ static unsigned int dec_abs_r(DisasContext *dc) @@ -1735,8 +1738,8 @@ static unsigned int dec_abs_r(DisasContext *dc)
1735 { 1738 {
1736 TCGv t0; 1739 TCGv t0;
1737 1740
1738 - DIS(fprintf (logfile, "abs $r%u, $r%u\n",  
1739 - dc->op1, dc->op2)); 1741 + LOG_DIS("abs $r%u, $r%u\n",
  1742 + dc->op1, dc->op2);
1740 cris_cc_mask(dc, CC_MASK_NZ); 1743 cris_cc_mask(dc, CC_MASK_NZ);
1741 1744
1742 t0 = tcg_temp_new(); 1745 t0 = tcg_temp_new();
@@ -1754,8 +1757,8 @@ static unsigned int dec_add_r(DisasContext *dc) @@ -1754,8 +1757,8 @@ static unsigned int dec_add_r(DisasContext *dc)
1754 { 1757 {
1755 TCGv t[2]; 1758 TCGv t[2];
1756 int size = memsize_zz(dc); 1759 int size = memsize_zz(dc);
1757 - DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",  
1758 - memsize_char(size), dc->op1, dc->op2)); 1760 + LOG_DIS("add.%c $r%u, $r%u\n",
  1761 + memsize_char(size), dc->op1, dc->op2);
1759 cris_cc_mask(dc, CC_MASK_NZVC); 1762 cris_cc_mask(dc, CC_MASK_NZVC);
1760 cris_alu_alloc_temps(dc, size, t); 1763 cris_alu_alloc_temps(dc, size, t);
1761 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1764 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@@ -1767,8 +1770,8 @@ static unsigned int dec_add_r(DisasContext *dc) @@ -1767,8 +1770,8 @@ static unsigned int dec_add_r(DisasContext *dc)
1767 1770
1768 static unsigned int dec_addc_r(DisasContext *dc) 1771 static unsigned int dec_addc_r(DisasContext *dc)
1769 { 1772 {
1770 - DIS(fprintf (logfile, "addc $r%u, $r%u\n",  
1771 - dc->op1, dc->op2)); 1773 + LOG_DIS("addc $r%u, $r%u\n",
  1774 + dc->op1, dc->op2);
1772 cris_evaluate_flags(dc); 1775 cris_evaluate_flags(dc);
1773 /* Set for this insn. */ 1776 /* Set for this insn. */
1774 dc->flagx_known = 1; 1777 dc->flagx_known = 1;
@@ -1782,8 +1785,8 @@ static unsigned int dec_addc_r(DisasContext *dc) @@ -1782,8 +1785,8 @@ static unsigned int dec_addc_r(DisasContext *dc)
1782 1785
1783 static unsigned int dec_mcp_r(DisasContext *dc) 1786 static unsigned int dec_mcp_r(DisasContext *dc)
1784 { 1787 {
1785 - DIS(fprintf (logfile, "mcp $p%u, $r%u\n",  
1786 - dc->op2, dc->op1)); 1788 + LOG_DIS("mcp $p%u, $r%u\n",
  1789 + dc->op2, dc->op1);
1787 cris_evaluate_flags(dc); 1790 cris_evaluate_flags(dc);
1788 cris_cc_mask(dc, CC_MASK_RNZV); 1791 cris_cc_mask(dc, CC_MASK_RNZV);
1789 cris_alu(dc, CC_OP_MCP, 1792 cris_alu(dc, CC_OP_MCP,
@@ -1813,8 +1816,8 @@ static unsigned int dec_swap_r(DisasContext *dc) @@ -1813,8 +1816,8 @@ static unsigned int dec_swap_r(DisasContext *dc)
1813 #if DISAS_CRIS 1816 #if DISAS_CRIS
1814 char modename[4]; 1817 char modename[4];
1815 #endif 1818 #endif
1816 - DIS(fprintf (logfile, "swap%s $r%u\n",  
1817 - swapmode_name(dc->op2, modename), dc->op1)); 1819 + LOG_DIS("swap%s $r%u\n",
  1820 + swapmode_name(dc->op2, modename), dc->op1);
1818 1821
1819 cris_cc_mask(dc, CC_MASK_NZ); 1822 cris_cc_mask(dc, CC_MASK_NZ);
1820 t0 = tcg_temp_new(); 1823 t0 = tcg_temp_new();
@@ -1837,8 +1840,8 @@ static unsigned int dec_or_r(DisasContext *dc) @@ -1837,8 +1840,8 @@ static unsigned int dec_or_r(DisasContext *dc)
1837 { 1840 {
1838 TCGv t[2]; 1841 TCGv t[2];
1839 int size = memsize_zz(dc); 1842 int size = memsize_zz(dc);
1840 - DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",  
1841 - memsize_char(size), dc->op1, dc->op2)); 1843 + LOG_DIS("or.%c $r%u, $r%u\n",
  1844 + memsize_char(size), dc->op1, dc->op2);
1842 cris_cc_mask(dc, CC_MASK_NZ); 1845 cris_cc_mask(dc, CC_MASK_NZ);
1843 cris_alu_alloc_temps(dc, size, t); 1846 cris_alu_alloc_temps(dc, size, t);
1844 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1847 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@@ -1850,8 +1853,8 @@ static unsigned int dec_or_r(DisasContext *dc) @@ -1850,8 +1853,8 @@ static unsigned int dec_or_r(DisasContext *dc)
1850 static unsigned int dec_addi_r(DisasContext *dc) 1853 static unsigned int dec_addi_r(DisasContext *dc)
1851 { 1854 {
1852 TCGv t0; 1855 TCGv t0;
1853 - DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",  
1854 - memsize_char(memsize_zz(dc)), dc->op2, dc->op1)); 1856 + LOG_DIS("addi.%c $r%u, $r%u\n",
  1857 + memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1855 cris_cc_mask(dc, 0); 1858 cris_cc_mask(dc, 0);
1856 t0 = tcg_temp_new(); 1859 t0 = tcg_temp_new();
1857 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); 1860 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
@@ -1863,8 +1866,8 @@ static unsigned int dec_addi_r(DisasContext *dc) @@ -1863,8 +1866,8 @@ static unsigned int dec_addi_r(DisasContext *dc)
1863 static unsigned int dec_addi_acr(DisasContext *dc) 1866 static unsigned int dec_addi_acr(DisasContext *dc)
1864 { 1867 {
1865 TCGv t0; 1868 TCGv t0;
1866 - DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",  
1867 - memsize_char(memsize_zz(dc)), dc->op2, dc->op1)); 1869 + LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
  1870 + memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1868 cris_cc_mask(dc, 0); 1871 cris_cc_mask(dc, 0);
1869 t0 = tcg_temp_new(); 1872 t0 = tcg_temp_new();
1870 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); 1873 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
@@ -1877,8 +1880,8 @@ static unsigned int dec_neg_r(DisasContext *dc) @@ -1877,8 +1880,8 @@ static unsigned int dec_neg_r(DisasContext *dc)
1877 { 1880 {
1878 TCGv t[2]; 1881 TCGv t[2];
1879 int size = memsize_zz(dc); 1882 int size = memsize_zz(dc);
1880 - DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",  
1881 - memsize_char(size), dc->op1, dc->op2)); 1883 + LOG_DIS("neg.%c $r%u, $r%u\n",
  1884 + memsize_char(size), dc->op1, dc->op2);
1882 cris_cc_mask(dc, CC_MASK_NZVC); 1885 cris_cc_mask(dc, CC_MASK_NZVC);
1883 cris_alu_alloc_temps(dc, size, t); 1886 cris_alu_alloc_temps(dc, size, t);
1884 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1887 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@@ -1890,8 +1893,8 @@ static unsigned int dec_neg_r(DisasContext *dc) @@ -1890,8 +1893,8 @@ static unsigned int dec_neg_r(DisasContext *dc)
1890 1893
1891 static unsigned int dec_btst_r(DisasContext *dc) 1894 static unsigned int dec_btst_r(DisasContext *dc)
1892 { 1895 {
1893 - DIS(fprintf (logfile, "btst $r%u, $r%u\n",  
1894 - dc->op1, dc->op2)); 1896 + LOG_DIS("btst $r%u, $r%u\n",
  1897 + dc->op1, dc->op2);
1895 cris_cc_mask(dc, CC_MASK_NZ); 1898 cris_cc_mask(dc, CC_MASK_NZ);
1896 cris_evaluate_flags(dc); 1899 cris_evaluate_flags(dc);
1897 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2], 1900 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
@@ -1907,8 +1910,8 @@ static unsigned int dec_sub_r(DisasContext *dc) @@ -1907,8 +1910,8 @@ static unsigned int dec_sub_r(DisasContext *dc)
1907 { 1910 {
1908 TCGv t[2]; 1911 TCGv t[2];
1909 int size = memsize_zz(dc); 1912 int size = memsize_zz(dc);
1910 - DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",  
1911 - memsize_char(size), dc->op1, dc->op2)); 1913 + LOG_DIS("sub.%c $r%u, $r%u\n",
  1914 + memsize_char(size), dc->op1, dc->op2);
1912 cris_cc_mask(dc, CC_MASK_NZVC); 1915 cris_cc_mask(dc, CC_MASK_NZVC);
1913 cris_alu_alloc_temps(dc, size, t); 1916 cris_alu_alloc_temps(dc, size, t);
1914 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1917 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@@ -1922,9 +1925,9 @@ static unsigned int dec_movu_r(DisasContext *dc) @@ -1922,9 +1925,9 @@ static unsigned int dec_movu_r(DisasContext *dc)
1922 { 1925 {
1923 TCGv t0; 1926 TCGv t0;
1924 int size = memsize_z(dc); 1927 int size = memsize_z(dc);
1925 - DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n", 1928 + LOG_DIS("movu.%c $r%u, $r%u\n",
1926 memsize_char(size), 1929 memsize_char(size),
1927 - dc->op1, dc->op2)); 1930 + dc->op1, dc->op2);
1928 1931
1929 cris_cc_mask(dc, CC_MASK_NZ); 1932 cris_cc_mask(dc, CC_MASK_NZ);
1930 t0 = tcg_temp_new(); 1933 t0 = tcg_temp_new();
@@ -1939,9 +1942,9 @@ static unsigned int dec_movs_r(DisasContext *dc) @@ -1939,9 +1942,9 @@ static unsigned int dec_movs_r(DisasContext *dc)
1939 { 1942 {
1940 TCGv t0; 1943 TCGv t0;
1941 int size = memsize_z(dc); 1944 int size = memsize_z(dc);
1942 - DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n", 1945 + LOG_DIS("movs.%c $r%u, $r%u\n",
1943 memsize_char(size), 1946 memsize_char(size),
1944 - dc->op1, dc->op2)); 1947 + dc->op1, dc->op2);
1945 1948
1946 cris_cc_mask(dc, CC_MASK_NZ); 1949 cris_cc_mask(dc, CC_MASK_NZ);
1947 t0 = tcg_temp_new(); 1950 t0 = tcg_temp_new();
@@ -1958,9 +1961,9 @@ static unsigned int dec_addu_r(DisasContext *dc) @@ -1958,9 +1961,9 @@ static unsigned int dec_addu_r(DisasContext *dc)
1958 { 1961 {
1959 TCGv t0; 1962 TCGv t0;
1960 int size = memsize_z(dc); 1963 int size = memsize_z(dc);
1961 - DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n", 1964 + LOG_DIS("addu.%c $r%u, $r%u\n",
1962 memsize_char(size), 1965 memsize_char(size),
1963 - dc->op1, dc->op2)); 1966 + dc->op1, dc->op2);
1964 1967
1965 cris_cc_mask(dc, CC_MASK_NZVC); 1968 cris_cc_mask(dc, CC_MASK_NZVC);
1966 t0 = tcg_temp_new(); 1969 t0 = tcg_temp_new();
@@ -1977,9 +1980,9 @@ static unsigned int dec_adds_r(DisasContext *dc) @@ -1977,9 +1980,9 @@ static unsigned int dec_adds_r(DisasContext *dc)
1977 { 1980 {
1978 TCGv t0; 1981 TCGv t0;
1979 int size = memsize_z(dc); 1982 int size = memsize_z(dc);
1980 - DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n", 1983 + LOG_DIS("adds.%c $r%u, $r%u\n",
1981 memsize_char(size), 1984 memsize_char(size),
1982 - dc->op1, dc->op2)); 1985 + dc->op1, dc->op2);
1983 1986
1984 cris_cc_mask(dc, CC_MASK_NZVC); 1987 cris_cc_mask(dc, CC_MASK_NZVC);
1985 t0 = tcg_temp_new(); 1988 t0 = tcg_temp_new();
@@ -1996,9 +1999,9 @@ static unsigned int dec_subu_r(DisasContext *dc) @@ -1996,9 +1999,9 @@ static unsigned int dec_subu_r(DisasContext *dc)
1996 { 1999 {
1997 TCGv t0; 2000 TCGv t0;
1998 int size = memsize_z(dc); 2001 int size = memsize_z(dc);
1999 - DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n", 2002 + LOG_DIS("subu.%c $r%u, $r%u\n",
2000 memsize_char(size), 2003 memsize_char(size),
2001 - dc->op1, dc->op2)); 2004 + dc->op1, dc->op2);
2002 2005
2003 cris_cc_mask(dc, CC_MASK_NZVC); 2006 cris_cc_mask(dc, CC_MASK_NZVC);
2004 t0 = tcg_temp_new(); 2007 t0 = tcg_temp_new();
@@ -2015,9 +2018,9 @@ static unsigned int dec_subs_r(DisasContext *dc) @@ -2015,9 +2018,9 @@ static unsigned int dec_subs_r(DisasContext *dc)
2015 { 2018 {
2016 TCGv t0; 2019 TCGv t0;
2017 int size = memsize_z(dc); 2020 int size = memsize_z(dc);
2018 - DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n", 2021 + LOG_DIS("subs.%c $r%u, $r%u\n",
2019 memsize_char(size), 2022 memsize_char(size),
2020 - dc->op1, dc->op2)); 2023 + dc->op1, dc->op2);
2021 2024
2022 cris_cc_mask(dc, CC_MASK_NZVC); 2025 cris_cc_mask(dc, CC_MASK_NZVC);
2023 t0 = tcg_temp_new(); 2026 t0 = tcg_temp_new();
@@ -2038,15 +2041,15 @@ static unsigned int dec_setclrf(DisasContext *dc) @@ -2038,15 +2041,15 @@ static unsigned int dec_setclrf(DisasContext *dc)
2038 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4) 2041 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2039 | EXTRACT_FIELD(dc->ir, 0, 3); 2042 | EXTRACT_FIELD(dc->ir, 0, 3);
2040 if (set && flags == 0) { 2043 if (set && flags == 0) {
2041 - DIS(fprintf (logfile, "nop\n")); 2044 + LOG_DIS("nop\n");
2042 return 2; 2045 return 2;
2043 } else if (!set && (flags & 0x20)) { 2046 } else if (!set && (flags & 0x20)) {
2044 - DIS(fprintf (logfile, "di\n")); 2047 + LOG_DIS("di\n");
2045 } 2048 }
2046 else { 2049 else {
2047 - DIS(fprintf (logfile, "%sf %x\n", 2050 + LOG_DIS("%sf %x\n",
2048 set ? "set" : "clr", 2051 set ? "set" : "clr",
2049 - flags)); 2052 + flags);
2050 } 2053 }
2051 2054
2052 /* User space is not allowed to touch these. Silently ignore. */ 2055 /* User space is not allowed to touch these. Silently ignore. */
@@ -2101,14 +2104,14 @@ static unsigned int dec_setclrf(DisasContext *dc) @@ -2101,14 +2104,14 @@ static unsigned int dec_setclrf(DisasContext *dc)
2101 2104
2102 static unsigned int dec_move_rs(DisasContext *dc) 2105 static unsigned int dec_move_rs(DisasContext *dc)
2103 { 2106 {
2104 - DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2)); 2107 + LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2105 cris_cc_mask(dc, 0); 2108 cris_cc_mask(dc, 0);
2106 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1)); 2109 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2107 return 2; 2110 return 2;
2108 } 2111 }
2109 static unsigned int dec_move_sr(DisasContext *dc) 2112 static unsigned int dec_move_sr(DisasContext *dc)
2110 { 2113 {
2111 - DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1)); 2114 + LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2112 cris_cc_mask(dc, 0); 2115 cris_cc_mask(dc, 0);
2113 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2)); 2116 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2114 return 2; 2117 return 2;
@@ -2117,7 +2120,7 @@ static unsigned int dec_move_sr(DisasContext *dc) @@ -2117,7 +2120,7 @@ static unsigned int dec_move_sr(DisasContext *dc)
2117 static unsigned int dec_move_rp(DisasContext *dc) 2120 static unsigned int dec_move_rp(DisasContext *dc)
2118 { 2121 {
2119 TCGv t[2]; 2122 TCGv t[2];
2120 - DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2)); 2123 + LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2121 cris_cc_mask(dc, 0); 2124 cris_cc_mask(dc, 0);
2122 2125
2123 t[0] = tcg_temp_new(); 2126 t[0] = tcg_temp_new();
@@ -2147,7 +2150,7 @@ static unsigned int dec_move_rp(DisasContext *dc) @@ -2147,7 +2150,7 @@ static unsigned int dec_move_rp(DisasContext *dc)
2147 static unsigned int dec_move_pr(DisasContext *dc) 2150 static unsigned int dec_move_pr(DisasContext *dc)
2148 { 2151 {
2149 TCGv t0; 2152 TCGv t0;
2150 - DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2)); 2153 + LOG_DIS("move $p%u, $r%u\n", dc->op1, dc->op2);
2151 cris_cc_mask(dc, 0); 2154 cris_cc_mask(dc, 0);
2152 2155
2153 if (dc->op2 == PR_CCS) 2156 if (dc->op2 == PR_CCS)
@@ -2165,10 +2168,10 @@ static unsigned int dec_move_mr(DisasContext *dc) @@ -2165,10 +2168,10 @@ static unsigned int dec_move_mr(DisasContext *dc)
2165 { 2168 {
2166 int memsize = memsize_zz(dc); 2169 int memsize = memsize_zz(dc);
2167 int insn_len; 2170 int insn_len;
2168 - DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n", 2171 + LOG_DIS("move.%c [$r%u%s, $r%u\n",
2169 memsize_char(memsize), 2172 memsize_char(memsize),
2170 dc->op1, dc->postinc ? "+]" : "]", 2173 dc->op1, dc->postinc ? "+]" : "]",
2171 - dc->op2)); 2174 + dc->op2);
2172 2175
2173 if (memsize == 4) { 2176 if (memsize == 4) {
2174 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]); 2177 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
@@ -2208,10 +2211,10 @@ static unsigned int dec_movs_m(DisasContext *dc) @@ -2208,10 +2211,10 @@ static unsigned int dec_movs_m(DisasContext *dc)
2208 TCGv t[2]; 2211 TCGv t[2];
2209 int memsize = memsize_z(dc); 2212 int memsize = memsize_z(dc);
2210 int insn_len; 2213 int insn_len;
2211 - DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n", 2214 + LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2212 memsize_char(memsize), 2215 memsize_char(memsize),
2213 dc->op1, dc->postinc ? "+]" : "]", 2216 dc->op1, dc->postinc ? "+]" : "]",
2214 - dc->op2)); 2217 + dc->op2);
2215 2218
2216 cris_alu_m_alloc_temps(t); 2219 cris_alu_m_alloc_temps(t);
2217 /* sign extend. */ 2220 /* sign extend. */
@@ -2229,10 +2232,10 @@ static unsigned int dec_addu_m(DisasContext *dc) @@ -2229,10 +2232,10 @@ static unsigned int dec_addu_m(DisasContext *dc)
2229 TCGv t[2]; 2232 TCGv t[2];
2230 int memsize = memsize_z(dc); 2233 int memsize = memsize_z(dc);
2231 int insn_len; 2234 int insn_len;
2232 - DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n", 2235 + LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2233 memsize_char(memsize), 2236 memsize_char(memsize),
2234 dc->op1, dc->postinc ? "+]" : "]", 2237 dc->op1, dc->postinc ? "+]" : "]",
2235 - dc->op2)); 2238 + dc->op2);
2236 2239
2237 cris_alu_m_alloc_temps(t); 2240 cris_alu_m_alloc_temps(t);
2238 /* sign extend. */ 2241 /* sign extend. */
@@ -2250,10 +2253,10 @@ static unsigned int dec_adds_m(DisasContext *dc) @@ -2250,10 +2253,10 @@ static unsigned int dec_adds_m(DisasContext *dc)
2250 TCGv t[2]; 2253 TCGv t[2];
2251 int memsize = memsize_z(dc); 2254 int memsize = memsize_z(dc);
2252 int insn_len; 2255 int insn_len;
2253 - DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n", 2256 + LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2254 memsize_char(memsize), 2257 memsize_char(memsize),
2255 dc->op1, dc->postinc ? "+]" : "]", 2258 dc->op1, dc->postinc ? "+]" : "]",
2256 - dc->op2)); 2259 + dc->op2);
2257 2260
2258 cris_alu_m_alloc_temps(t); 2261 cris_alu_m_alloc_temps(t);
2259 /* sign extend. */ 2262 /* sign extend. */
@@ -2270,10 +2273,10 @@ static unsigned int dec_subu_m(DisasContext *dc) @@ -2270,10 +2273,10 @@ static unsigned int dec_subu_m(DisasContext *dc)
2270 TCGv t[2]; 2273 TCGv t[2];
2271 int memsize = memsize_z(dc); 2274 int memsize = memsize_z(dc);
2272 int insn_len; 2275 int insn_len;
2273 - DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n", 2276 + LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2274 memsize_char(memsize), 2277 memsize_char(memsize),
2275 dc->op1, dc->postinc ? "+]" : "]", 2278 dc->op1, dc->postinc ? "+]" : "]",
2276 - dc->op2)); 2279 + dc->op2);
2277 2280
2278 cris_alu_m_alloc_temps(t); 2281 cris_alu_m_alloc_temps(t);
2279 /* sign extend. */ 2282 /* sign extend. */
@@ -2290,10 +2293,10 @@ static unsigned int dec_subs_m(DisasContext *dc) @@ -2290,10 +2293,10 @@ static unsigned int dec_subs_m(DisasContext *dc)
2290 TCGv t[2]; 2293 TCGv t[2];
2291 int memsize = memsize_z(dc); 2294 int memsize = memsize_z(dc);
2292 int insn_len; 2295 int insn_len;
2293 - DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n", 2296 + LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2294 memsize_char(memsize), 2297 memsize_char(memsize),
2295 dc->op1, dc->postinc ? "+]" : "]", 2298 dc->op1, dc->postinc ? "+]" : "]",
2296 - dc->op2)); 2299 + dc->op2);
2297 2300
2298 cris_alu_m_alloc_temps(t); 2301 cris_alu_m_alloc_temps(t);
2299 /* sign extend. */ 2302 /* sign extend. */
@@ -2311,10 +2314,10 @@ static unsigned int dec_movu_m(DisasContext *dc) @@ -2311,10 +2314,10 @@ static unsigned int dec_movu_m(DisasContext *dc)
2311 int memsize = memsize_z(dc); 2314 int memsize = memsize_z(dc);
2312 int insn_len; 2315 int insn_len;
2313 2316
2314 - DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n", 2317 + LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2315 memsize_char(memsize), 2318 memsize_char(memsize),
2316 dc->op1, dc->postinc ? "+]" : "]", 2319 dc->op1, dc->postinc ? "+]" : "]",
2317 - dc->op2)); 2320 + dc->op2);
2318 2321
2319 cris_alu_m_alloc_temps(t); 2322 cris_alu_m_alloc_temps(t);
2320 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2323 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2330,10 +2333,10 @@ static unsigned int dec_cmpu_m(DisasContext *dc) @@ -2330,10 +2333,10 @@ static unsigned int dec_cmpu_m(DisasContext *dc)
2330 TCGv t[2]; 2333 TCGv t[2];
2331 int memsize = memsize_z(dc); 2334 int memsize = memsize_z(dc);
2332 int insn_len; 2335 int insn_len;
2333 - DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n", 2336 + LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2334 memsize_char(memsize), 2337 memsize_char(memsize),
2335 dc->op1, dc->postinc ? "+]" : "]", 2338 dc->op1, dc->postinc ? "+]" : "]",
2336 - dc->op2)); 2339 + dc->op2);
2337 2340
2338 cris_alu_m_alloc_temps(t); 2341 cris_alu_m_alloc_temps(t);
2339 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2342 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2349,10 +2352,10 @@ static unsigned int dec_cmps_m(DisasContext *dc) @@ -2349,10 +2352,10 @@ static unsigned int dec_cmps_m(DisasContext *dc)
2349 TCGv t[2]; 2352 TCGv t[2];
2350 int memsize = memsize_z(dc); 2353 int memsize = memsize_z(dc);
2351 int insn_len; 2354 int insn_len;
2352 - DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n", 2355 + LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2353 memsize_char(memsize), 2356 memsize_char(memsize),
2354 dc->op1, dc->postinc ? "+]" : "]", 2357 dc->op1, dc->postinc ? "+]" : "]",
2355 - dc->op2)); 2358 + dc->op2);
2356 2359
2357 cris_alu_m_alloc_temps(t); 2360 cris_alu_m_alloc_temps(t);
2358 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]); 2361 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
@@ -2370,10 +2373,10 @@ static unsigned int dec_cmp_m(DisasContext *dc) @@ -2370,10 +2373,10 @@ static unsigned int dec_cmp_m(DisasContext *dc)
2370 TCGv t[2]; 2373 TCGv t[2];
2371 int memsize = memsize_zz(dc); 2374 int memsize = memsize_zz(dc);
2372 int insn_len; 2375 int insn_len;
2373 - DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n", 2376 + LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2374 memsize_char(memsize), 2377 memsize_char(memsize),
2375 dc->op1, dc->postinc ? "+]" : "]", 2378 dc->op1, dc->postinc ? "+]" : "]",
2376 - dc->op2)); 2379 + dc->op2);
2377 2380
2378 cris_alu_m_alloc_temps(t); 2381 cris_alu_m_alloc_temps(t);
2379 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2382 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2391,10 +2394,10 @@ static unsigned int dec_test_m(DisasContext *dc) @@ -2391,10 +2394,10 @@ static unsigned int dec_test_m(DisasContext *dc)
2391 TCGv t[2]; 2394 TCGv t[2];
2392 int memsize = memsize_zz(dc); 2395 int memsize = memsize_zz(dc);
2393 int insn_len; 2396 int insn_len;
2394 - DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n", 2397 + LOG_DIS("test.%d [$r%u%s] op2=%x\n",
2395 memsize_char(memsize), 2398 memsize_char(memsize),
2396 dc->op1, dc->postinc ? "+]" : "]", 2399 dc->op1, dc->postinc ? "+]" : "]",
2397 - dc->op2)); 2400 + dc->op2);
2398 2401
2399 cris_evaluate_flags(dc); 2402 cris_evaluate_flags(dc);
2400 2403
@@ -2415,10 +2418,10 @@ static unsigned int dec_and_m(DisasContext *dc) @@ -2415,10 +2418,10 @@ static unsigned int dec_and_m(DisasContext *dc)
2415 TCGv t[2]; 2418 TCGv t[2];
2416 int memsize = memsize_zz(dc); 2419 int memsize = memsize_zz(dc);
2417 int insn_len; 2420 int insn_len;
2418 - DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n", 2421 + LOG_DIS("and.%d [$r%u%s, $r%u\n",
2419 memsize_char(memsize), 2422 memsize_char(memsize),
2420 dc->op1, dc->postinc ? "+]" : "]", 2423 dc->op1, dc->postinc ? "+]" : "]",
2421 - dc->op2)); 2424 + dc->op2);
2422 2425
2423 cris_alu_m_alloc_temps(t); 2426 cris_alu_m_alloc_temps(t);
2424 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2427 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2434,10 +2437,10 @@ static unsigned int dec_add_m(DisasContext *dc) @@ -2434,10 +2437,10 @@ static unsigned int dec_add_m(DisasContext *dc)
2434 TCGv t[2]; 2437 TCGv t[2];
2435 int memsize = memsize_zz(dc); 2438 int memsize = memsize_zz(dc);
2436 int insn_len; 2439 int insn_len;
2437 - DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n", 2440 + LOG_DIS("add.%d [$r%u%s, $r%u\n",
2438 memsize_char(memsize), 2441 memsize_char(memsize),
2439 dc->op1, dc->postinc ? "+]" : "]", 2442 dc->op1, dc->postinc ? "+]" : "]",
2440 - dc->op2)); 2443 + dc->op2);
2441 2444
2442 cris_alu_m_alloc_temps(t); 2445 cris_alu_m_alloc_temps(t);
2443 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2446 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2454,10 +2457,10 @@ static unsigned int dec_addo_m(DisasContext *dc) @@ -2454,10 +2457,10 @@ static unsigned int dec_addo_m(DisasContext *dc)
2454 TCGv t[2]; 2457 TCGv t[2];
2455 int memsize = memsize_zz(dc); 2458 int memsize = memsize_zz(dc);
2456 int insn_len; 2459 int insn_len;
2457 - DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n", 2460 + LOG_DIS("add.%d [$r%u%s, $r%u\n",
2458 memsize_char(memsize), 2461 memsize_char(memsize),
2459 dc->op1, dc->postinc ? "+]" : "]", 2462 dc->op1, dc->postinc ? "+]" : "]",
2460 - dc->op2)); 2463 + dc->op2);
2461 2464
2462 cris_alu_m_alloc_temps(t); 2465 cris_alu_m_alloc_temps(t);
2463 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]); 2466 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
@@ -2473,10 +2476,10 @@ static unsigned int dec_bound_m(DisasContext *dc) @@ -2473,10 +2476,10 @@ static unsigned int dec_bound_m(DisasContext *dc)
2473 TCGv l[2]; 2476 TCGv l[2];
2474 int memsize = memsize_zz(dc); 2477 int memsize = memsize_zz(dc);
2475 int insn_len; 2478 int insn_len;
2476 - DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n", 2479 + LOG_DIS("bound.%d [$r%u%s, $r%u\n",
2477 memsize_char(memsize), 2480 memsize_char(memsize),
2478 dc->op1, dc->postinc ? "+]" : "]", 2481 dc->op1, dc->postinc ? "+]" : "]",
2479 - dc->op2)); 2482 + dc->op2);
2480 2483
2481 l[0] = tcg_temp_local_new(); 2484 l[0] = tcg_temp_local_new();
2482 l[1] = tcg_temp_local_new(); 2485 l[1] = tcg_temp_local_new();
@@ -2493,9 +2496,9 @@ static unsigned int dec_addc_mr(DisasContext *dc) @@ -2493,9 +2496,9 @@ static unsigned int dec_addc_mr(DisasContext *dc)
2493 { 2496 {
2494 TCGv t[2]; 2497 TCGv t[2];
2495 int insn_len = 2; 2498 int insn_len = 2;
2496 - DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n", 2499 + LOG_DIS("addc [$r%u%s, $r%u\n",
2497 dc->op1, dc->postinc ? "+]" : "]", 2500 dc->op1, dc->postinc ? "+]" : "]",
2498 - dc->op2)); 2501 + dc->op2);
2499 2502
2500 cris_evaluate_flags(dc); 2503 cris_evaluate_flags(dc);
2501 2504
@@ -2517,10 +2520,10 @@ static unsigned int dec_sub_m(DisasContext *dc) @@ -2517,10 +2520,10 @@ static unsigned int dec_sub_m(DisasContext *dc)
2517 TCGv t[2]; 2520 TCGv t[2];
2518 int memsize = memsize_zz(dc); 2521 int memsize = memsize_zz(dc);
2519 int insn_len; 2522 int insn_len;
2520 - DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n", 2523 + LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2521 memsize_char(memsize), 2524 memsize_char(memsize),
2522 dc->op1, dc->postinc ? "+]" : "]", 2525 dc->op1, dc->postinc ? "+]" : "]",
2523 - dc->op2, dc->ir, dc->zzsize)); 2526 + dc->op2, dc->ir, dc->zzsize);
2524 2527
2525 cris_alu_m_alloc_temps(t); 2528 cris_alu_m_alloc_temps(t);
2526 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2529 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2536,10 +2539,10 @@ static unsigned int dec_or_m(DisasContext *dc) @@ -2536,10 +2539,10 @@ static unsigned int dec_or_m(DisasContext *dc)
2536 TCGv t[2]; 2539 TCGv t[2];
2537 int memsize = memsize_zz(dc); 2540 int memsize = memsize_zz(dc);
2538 int insn_len; 2541 int insn_len;
2539 - DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n", 2542 + LOG_DIS("or.%d [$r%u%s, $r%u pc=%x\n",
2540 memsize_char(memsize), 2543 memsize_char(memsize),
2541 dc->op1, dc->postinc ? "+]" : "]", 2544 dc->op1, dc->postinc ? "+]" : "]",
2542 - dc->op2, dc->pc)); 2545 + dc->op2, dc->pc);
2543 2546
2544 cris_alu_m_alloc_temps(t); 2547 cris_alu_m_alloc_temps(t);
2545 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2548 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2557,11 +2560,11 @@ static unsigned int dec_move_mp(DisasContext *dc) @@ -2557,11 +2560,11 @@ static unsigned int dec_move_mp(DisasContext *dc)
2557 int memsize = memsize_zz(dc); 2560 int memsize = memsize_zz(dc);
2558 int insn_len = 2; 2561 int insn_len = 2;
2559 2562
2560 - DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n", 2563 + LOG_DIS("move.%c [$r%u%s, $p%u\n",
2561 memsize_char(memsize), 2564 memsize_char(memsize),
2562 dc->op1, 2565 dc->op1,
2563 dc->postinc ? "+]" : "]", 2566 dc->postinc ? "+]" : "]",
2564 - dc->op2)); 2567 + dc->op2);
2565 2568
2566 cris_alu_m_alloc_temps(t); 2569 cris_alu_m_alloc_temps(t);
2567 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]); 2570 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@@ -2590,9 +2593,9 @@ static unsigned int dec_move_pm(DisasContext *dc) @@ -2590,9 +2593,9 @@ static unsigned int dec_move_pm(DisasContext *dc)
2590 2593
2591 memsize = preg_sizes[dc->op2]; 2594 memsize = preg_sizes[dc->op2];
2592 2595
2593 - DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n", 2596 + LOG_DIS("move.%c $p%u, [$r%u%s\n",
2594 memsize_char(memsize), 2597 memsize_char(memsize),
2595 - dc->op2, dc->op1, dc->postinc ? "+]" : "]")); 2598 + dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2596 2599
2597 /* prepare store. Address in T0, value in T1. */ 2600 /* prepare store. Address in T0, value in T1. */
2598 if (dc->op2 == PR_CCS) 2601 if (dc->op2 == PR_CCS)
@@ -2617,8 +2620,8 @@ static unsigned int dec_movem_mr(DisasContext *dc) @@ -2617,8 +2620,8 @@ static unsigned int dec_movem_mr(DisasContext *dc)
2617 int i; 2620 int i;
2618 int nr = dc->op2 + 1; 2621 int nr = dc->op2 + 1;
2619 2622
2620 - DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,  
2621 - dc->postinc ? "+]" : "]", dc->op2)); 2623 + LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
  2624 + dc->postinc ? "+]" : "]", dc->op2);
2622 2625
2623 addr = tcg_temp_new(); 2626 addr = tcg_temp_new();
2624 /* There are probably better ways of doing this. */ 2627 /* There are probably better ways of doing this. */
@@ -2661,8 +2664,8 @@ static unsigned int dec_movem_rm(DisasContext *dc) @@ -2661,8 +2664,8 @@ static unsigned int dec_movem_rm(DisasContext *dc)
2661 TCGv addr; 2664 TCGv addr;
2662 int i; 2665 int i;
2663 2666
2664 - DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,  
2665 - dc->postinc ? "+]" : "]")); 2667 + LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
  2668 + dc->postinc ? "+]" : "]");
2666 2669
2667 cris_flush_cc_state(dc); 2670 cris_flush_cc_state(dc);
2668 2671
@@ -2690,8 +2693,8 @@ static unsigned int dec_move_rm(DisasContext *dc) @@ -2690,8 +2693,8 @@ static unsigned int dec_move_rm(DisasContext *dc)
2690 2693
2691 memsize = memsize_zz(dc); 2694 memsize = memsize_zz(dc);
2692 2695
2693 - DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",  
2694 - memsize, dc->op2, dc->op1)); 2696 + LOG_DIS("move.%d $r%u, [$r%u]\n",
  2697 + memsize, dc->op2, dc->op1);
2695 2698
2696 /* prepare store. */ 2699 /* prepare store. */
2697 cris_flush_cc_state(dc); 2700 cris_flush_cc_state(dc);
@@ -2705,8 +2708,8 @@ static unsigned int dec_move_rm(DisasContext *dc) @@ -2705,8 +2708,8 @@ static unsigned int dec_move_rm(DisasContext *dc)
2705 2708
2706 static unsigned int dec_lapcq(DisasContext *dc) 2709 static unsigned int dec_lapcq(DisasContext *dc)
2707 { 2710 {
2708 - DIS(fprintf (logfile, "lapcq %x, $r%u\n",  
2709 - dc->pc + dc->op1*2, dc->op2)); 2711 + LOG_DIS("lapcq %x, $r%u\n",
  2712 + dc->pc + dc->op1*2, dc->op2);
2710 cris_cc_mask(dc, 0); 2713 cris_cc_mask(dc, 0);
2711 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2); 2714 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2712 return 2; 2715 return 2;
@@ -2722,7 +2725,7 @@ static unsigned int dec_lapc_im(DisasContext *dc) @@ -2722,7 +2725,7 @@ static unsigned int dec_lapc_im(DisasContext *dc)
2722 2725
2723 cris_cc_mask(dc, 0); 2726 cris_cc_mask(dc, 0);
2724 imm = ldl_code(dc->pc + 2); 2727 imm = ldl_code(dc->pc + 2);
2725 - DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2)); 2728 + LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2726 2729
2727 pc = dc->pc; 2730 pc = dc->pc;
2728 pc += imm; 2731 pc += imm;
@@ -2733,7 +2736,7 @@ static unsigned int dec_lapc_im(DisasContext *dc) @@ -2733,7 +2736,7 @@ static unsigned int dec_lapc_im(DisasContext *dc)
2733 /* Jump to special reg. */ 2736 /* Jump to special reg. */
2734 static unsigned int dec_jump_p(DisasContext *dc) 2737 static unsigned int dec_jump_p(DisasContext *dc)
2735 { 2738 {
2736 - DIS(fprintf (logfile, "jump $p%u\n", dc->op2)); 2739 + LOG_DIS("jump $p%u\n", dc->op2);
2737 2740
2738 if (dc->op2 == PR_CCS) 2741 if (dc->op2 == PR_CCS)
2739 cris_evaluate_flags(dc); 2742 cris_evaluate_flags(dc);
@@ -2748,7 +2751,7 @@ static unsigned int dec_jump_p(DisasContext *dc) @@ -2748,7 +2751,7 @@ static unsigned int dec_jump_p(DisasContext *dc)
2748 /* Jump and save. */ 2751 /* Jump and save. */
2749 static unsigned int dec_jas_r(DisasContext *dc) 2752 static unsigned int dec_jas_r(DisasContext *dc)
2750 { 2753 {
2751 - DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2)); 2754 + LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2752 cris_cc_mask(dc, 0); 2755 cris_cc_mask(dc, 0);
2753 /* Store the return address in Pd. */ 2756 /* Store the return address in Pd. */
2754 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); 2757 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
@@ -2766,7 +2769,7 @@ static unsigned int dec_jas_im(DisasContext *dc) @@ -2766,7 +2769,7 @@ static unsigned int dec_jas_im(DisasContext *dc)
2766 2769
2767 imm = ldl_code(dc->pc + 2); 2770 imm = ldl_code(dc->pc + 2);
2768 2771
2769 - DIS(fprintf (logfile, "jas 0x%x\n", imm)); 2772 + LOG_DIS("jas 0x%x\n", imm);
2770 cris_cc_mask(dc, 0); 2773 cris_cc_mask(dc, 0);
2771 /* Store the return address in Pd. */ 2774 /* Store the return address in Pd. */
2772 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); 2775 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
@@ -2782,7 +2785,7 @@ static unsigned int dec_jasc_im(DisasContext *dc) @@ -2782,7 +2785,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
2782 2785
2783 imm = ldl_code(dc->pc + 2); 2786 imm = ldl_code(dc->pc + 2);
2784 2787
2785 - DIS(fprintf (logfile, "jasc 0x%x\n", imm)); 2788 + LOG_DIS("jasc 0x%x\n", imm);
2786 cris_cc_mask(dc, 0); 2789 cris_cc_mask(dc, 0);
2787 /* Store the return address in Pd. */ 2790 /* Store the return address in Pd. */
2788 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4)); 2791 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
@@ -2794,7 +2797,7 @@ static unsigned int dec_jasc_im(DisasContext *dc) @@ -2794,7 +2797,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
2794 2797
2795 static unsigned int dec_jasc_r(DisasContext *dc) 2798 static unsigned int dec_jasc_r(DisasContext *dc)
2796 { 2799 {
2797 - DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2)); 2800 + LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2798 cris_cc_mask(dc, 0); 2801 cris_cc_mask(dc, 0);
2799 /* Store the return address in Pd. */ 2802 /* Store the return address in Pd. */
2800 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); 2803 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
@@ -2810,9 +2813,9 @@ static unsigned int dec_bcc_im(DisasContext *dc) @@ -2810,9 +2813,9 @@ static unsigned int dec_bcc_im(DisasContext *dc)
2810 2813
2811 offset = ldsw_code(dc->pc + 2); 2814 offset = ldsw_code(dc->pc + 2);
2812 2815
2813 - DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n", 2816 + LOG_DIS("b%s %d pc=%x dst=%x\n",
2814 cc_name(cond), offset, 2817 cc_name(cond), offset,
2815 - dc->pc, dc->pc + offset)); 2818 + dc->pc, dc->pc + offset);
2816 2819
2817 cris_cc_mask(dc, 0); 2820 cris_cc_mask(dc, 0);
2818 /* op2 holds the condition-code. */ 2821 /* op2 holds the condition-code. */
@@ -2827,7 +2830,7 @@ static unsigned int dec_bas_im(DisasContext *dc) @@ -2827,7 +2830,7 @@ static unsigned int dec_bas_im(DisasContext *dc)
2827 2830
2828 simm = ldl_code(dc->pc + 2); 2831 simm = ldl_code(dc->pc + 2);
2829 2832
2830 - DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2)); 2833 + LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2831 cris_cc_mask(dc, 0); 2834 cris_cc_mask(dc, 0);
2832 /* Store the return address in Pd. */ 2835 /* Store the return address in Pd. */
2833 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); 2836 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
@@ -2842,7 +2845,7 @@ static unsigned int dec_basc_im(DisasContext *dc) @@ -2842,7 +2845,7 @@ static unsigned int dec_basc_im(DisasContext *dc)
2842 int32_t simm; 2845 int32_t simm;
2843 simm = ldl_code(dc->pc + 2); 2846 simm = ldl_code(dc->pc + 2);
2844 2847
2845 - DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2)); 2848 + LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2846 cris_cc_mask(dc, 0); 2849 cris_cc_mask(dc, 0);
2847 /* Store the return address in Pd. */ 2850 /* Store the return address in Pd. */
2848 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12)); 2851 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
@@ -2866,20 +2869,20 @@ static unsigned int dec_rfe_etc(DisasContext *dc) @@ -2866,20 +2869,20 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
2866 switch (dc->op2 & 7) { 2869 switch (dc->op2 & 7) {
2867 case 2: 2870 case 2:
2868 /* rfe. */ 2871 /* rfe. */
2869 - DIS(fprintf(logfile, "rfe\n")); 2872 + LOG_DIS("rfe\n");
2870 cris_evaluate_flags(dc); 2873 cris_evaluate_flags(dc);
2871 gen_helper_rfe(); 2874 gen_helper_rfe();
2872 dc->is_jmp = DISAS_UPDATE; 2875 dc->is_jmp = DISAS_UPDATE;
2873 break; 2876 break;
2874 case 5: 2877 case 5:
2875 /* rfn. */ 2878 /* rfn. */
2876 - DIS(fprintf(logfile, "rfn\n")); 2879 + LOG_DIS("rfn\n");
2877 cris_evaluate_flags(dc); 2880 cris_evaluate_flags(dc);
2878 gen_helper_rfn(); 2881 gen_helper_rfn();
2879 dc->is_jmp = DISAS_UPDATE; 2882 dc->is_jmp = DISAS_UPDATE;
2880 break; 2883 break;
2881 case 6: 2884 case 6:
2882 - DIS(fprintf(logfile, "break %d\n", dc->op1)); 2885 + LOG_DIS("break %d\n", dc->op1);
2883 cris_evaluate_flags (dc); 2886 cris_evaluate_flags (dc);
2884 /* break. */ 2887 /* break. */
2885 tcg_gen_movi_tl(env_pc, dc->pc + 2); 2888 tcg_gen_movi_tl(env_pc, dc->pc + 2);
@@ -3231,7 +3234,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, @@ -3231,7 +3234,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3231 } 3234 }
3232 3235
3233 /* Pretty disas. */ 3236 /* Pretty disas. */
3234 - DIS(fprintf(logfile, "%8.8x:\t", dc->pc)); 3237 + LOG_DIS("%8.8x:\t", dc->pc);
3235 3238
3236 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) 3239 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3237 gen_io_start(); 3240 gen_io_start();
target-i386/op_helper.c
  View file @d12d51d
@@ -24,6 +24,22 @@ @@ -24,6 +24,22 @@
24 24
25 //#define DEBUG_PCALL 25 //#define DEBUG_PCALL
26 26
  27 +
  28 +#ifdef DEBUG_PCALL
  29 +# define LOG_PCALL(...) do { \
  30 + if (loglevel & CPU_LOG_PCALL) \
  31 + fprintf(logfile, ## __VA_ARGS__); \
  32 + } while (0)
  33 +# define LOG_PCALL_STATE(env) do { \
  34 + if (loglevel & CPU_LOG_PCALL) \
  35 + cpu_dump_state((env), logfile, fprintf, X86_DUMP_CCOP); \
  36 + } while (0)
  37 +#else
  38 +# define LOG_PCALL(...) do { } while (0)
  39 +# define LOG_PCALL_STATE(env) do { } while (0)
  40 +#endif
  41 +
  42 +
27 #if 0 43 #if 0
28 #define raise_exception_err(a, b)\ 44 #define raise_exception_err(a, b)\
29 do {\ 45 do {\
@@ -277,10 +293,7 @@ static void switch_tss(int tss_selector, @@ -277,10 +293,7 @@ static void switch_tss(int tss_selector,
277 target_ulong ptr; 293 target_ulong ptr;
278 294
279 type = (e2 >> DESC_TYPE_SHIFT) & 0xf; 295 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
280 -#ifdef DEBUG_PCALL  
281 - if (loglevel & CPU_LOG_PCALL)  
282 - fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);  
283 -#endif 296 + LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
284 297
285 /* if task gate, we read the TSS segment and we load it */ 298 /* if task gate, we read the TSS segment and we load it */
286 if (type == 5) { 299 if (type == 5) {
@@ -2276,23 +2289,14 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip, @@ -2276,23 +2289,14 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip,
2276 target_ulong ssp, old_ssp, next_eip; 2289 target_ulong ssp, old_ssp, next_eip;
2277 2290
2278 next_eip = env->eip + next_eip_addend; 2291 next_eip = env->eip + next_eip_addend;
2279 -#ifdef DEBUG_PCALL  
2280 - if (loglevel & CPU_LOG_PCALL) {  
2281 - fprintf(logfile, "lcall %04x:%08x s=%d\n",  
2282 - new_cs, (uint32_t)new_eip, shift);  
2283 - cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);  
2284 - }  
2285 -#endif 2292 + LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
  2293 + LOG_PCALL_STATE(env);
2286 if ((new_cs & 0xfffc) == 0) 2294 if ((new_cs & 0xfffc) == 0)
2287 raise_exception_err(EXCP0D_GPF, 0); 2295 raise_exception_err(EXCP0D_GPF, 0);
2288 if (load_segment(&e1, &e2, new_cs) != 0) 2296 if (load_segment(&e1, &e2, new_cs) != 0)
2289 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); 2297 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2290 cpl = env->hflags & HF_CPL_MASK; 2298 cpl = env->hflags & HF_CPL_MASK;
2291 -#ifdef DEBUG_PCALL  
2292 - if (loglevel & CPU_LOG_PCALL) {  
2293 - fprintf(logfile, "desc=%08x:%08x\n", e1, e2);  
2294 - }  
2295 -#endif 2299 + LOG_PCALL("desc=%08x:%08x\n", e1, e2);
2296 if (e2 & DESC_S_MASK) { 2300 if (e2 & DESC_S_MASK) {
2297 if (!(e2 & DESC_CS_MASK)) 2301 if (!(e2 & DESC_CS_MASK))
2298 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); 2302 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
@@ -2396,11 +2400,8 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip, @@ -2396,11 +2400,8 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip,
2396 if (!(e2 & DESC_C_MASK) && dpl < cpl) { 2400 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2397 /* to inner privilege */ 2401 /* to inner privilege */
2398 get_ss_esp_from_tss(&ss, &sp, dpl); 2402 get_ss_esp_from_tss(&ss, &sp, dpl);
2399 -#ifdef DEBUG_PCALL  
2400 - if (loglevel & CPU_LOG_PCALL)  
2401 - fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n", 2403 + LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2402 ss, sp, param_count, ESP); 2404 ss, sp, param_count, ESP);
2403 -#endif  
2404 if ((ss & 0xfffc) == 0) 2405 if ((ss & 0xfffc) == 0)
2405 raise_exception_err(EXCP0A_TSS, ss & 0xfffc); 2406 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2406 if ((ss & 3) != dpl) 2407 if ((ss & 3) != dpl)
@@ -2587,13 +2588,9 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend) @@ -2587,13 +2588,9 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
2587 if (is_iret) 2588 if (is_iret)
2588 POPW(ssp, sp, sp_mask, new_eflags); 2589 POPW(ssp, sp, sp_mask, new_eflags);
2589 } 2590 }
2590 -#ifdef DEBUG_PCALL  
2591 - if (loglevel & CPU_LOG_PCALL) {  
2592 - fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",  
2593 - new_cs, new_eip, shift, addend);  
2594 - cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);  
2595 - }  
2596 -#endif 2591 + LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
  2592 + new_cs, new_eip, shift, addend);
  2593 + LOG_PCALL_STATE(env);
2597 if ((new_cs & 0xfffc) == 0) 2594 if ((new_cs & 0xfffc) == 0)
2598 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); 2595 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2599 if (load_segment(&e1, &e2, new_cs) != 0) 2596 if (load_segment(&e1, &e2, new_cs) != 0)
@@ -2643,12 +2640,8 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend) @@ -2643,12 +2640,8 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
2643 POPW(ssp, sp, sp_mask, new_esp); 2640 POPW(ssp, sp, sp_mask, new_esp);
2644 POPW(ssp, sp, sp_mask, new_ss); 2641 POPW(ssp, sp, sp_mask, new_ss);
2645 } 2642 }
2646 -#ifdef DEBUG_PCALL  
2647 - if (loglevel & CPU_LOG_PCALL) {  
2648 - fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n", 2643 + LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
2649 new_ss, new_esp); 2644 new_ss, new_esp);
2650 - }  
2651 -#endif  
2652 if ((new_ss & 0xfffc) == 0) { 2645 if ((new_ss & 0xfffc) == 0) {
2653 #ifdef TARGET_X86_64 2646 #ifdef TARGET_X86_64
2654 /* NULL ss is allowed in long mode if cpl != 3*/ 2647 /* NULL ss is allowed in long mode if cpl != 3*/
target-mips/translate.c
  View file @d12d51d
@@ -521,8 +521,14 @@ do { \ @@ -521,8 +521,14 @@ do { \
521 ctx->pc, ctx->opcode , ##args); \ 521 ctx->pc, ctx->opcode , ##args); \
522 } \ 522 } \
523 } while (0) 523 } while (0)
  524 +#define LOG_DISAS(...) \
  525 + do { \
  526 + if (loglevel & CPU_LOG_TB_IN_ASM) \
  527 + fprintf(logfile, ## __VA_ARGS__); \
  528 + } while (0)
524 #else 529 #else
525 #define MIPS_DEBUG(fmt, args...) do { } while(0) 530 #define MIPS_DEBUG(fmt, args...) do { } while(0)
  531 +#define LOG_DISAS(...) do { } while (0)
526 #endif 532 #endif
527 533
528 #define MIPS_INVAL(op) \ 534 #define MIPS_INVAL(op) \
@@ -758,12 +764,7 @@ static inline void gen_save_pc(target_ulong pc) @@ -758,12 +764,7 @@ static inline void gen_save_pc(target_ulong pc)
758 764
759 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) 765 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
760 { 766 {
761 -#if defined MIPS_DEBUG_DISAS  
762 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
763 - fprintf(logfile, "hflags %08x saved %08x\n",  
764 - ctx->hflags, ctx->saved_hflags);  
765 - }  
766 -#endif 767 + LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
767 if (do_save_pc && ctx->pc != ctx->saved_pc) { 768 if (do_save_pc && ctx->pc != ctx->saved_pc) {
768 gen_save_pc(ctx->pc); 769 gen_save_pc(ctx->pc);
769 ctx->saved_pc = ctx->pc; 770 ctx->saved_pc = ctx->pc;
@@ -2314,11 +2315,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, @@ -2314,11 +2315,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2314 2315
2315 if (ctx->hflags & MIPS_HFLAG_BMASK) { 2316 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2316 #ifdef MIPS_DEBUG_DISAS 2317 #ifdef MIPS_DEBUG_DISAS
2317 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
2318 - fprintf(logfile,  
2319 - "Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",  
2320 - ctx->pc);  
2321 - } 2318 + LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
2322 #endif 2319 #endif
2323 generate_exception(ctx, EXCP_RI); 2320 generate_exception(ctx, EXCP_RI);
2324 goto out; 2321 goto out;
@@ -3295,21 +3292,11 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se @@ -3295,21 +3292,11 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3295 default: 3292 default:
3296 goto die; 3293 goto die;
3297 } 3294 }
3298 -#if defined MIPS_DEBUG_DISAS  
3299 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
3300 - fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",  
3301 - rn, reg, sel);  
3302 - }  
3303 -#endif 3295 + LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
3304 return; 3296 return;
3305 3297
3306 die: 3298 die:
3307 -#if defined MIPS_DEBUG_DISAS  
3308 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
3309 - fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",  
3310 - rn, reg, sel);  
3311 - }  
3312 -#endif 3299 + LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
3313 generate_exception(ctx, EXCP_RI); 3300 generate_exception(ctx, EXCP_RI);
3314 } 3301 }
3315 3302
@@ -3899,12 +3886,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se @@ -3899,12 +3886,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3899 default: 3886 default:
3900 goto die; 3887 goto die;
3901 } 3888 }
3902 -#if defined MIPS_DEBUG_DISAS  
3903 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
3904 - fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",  
3905 - rn, reg, sel);  
3906 - }  
3907 -#endif 3889 + LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
3908 /* For simplicity assume that all writes can cause interrupts. */ 3890 /* For simplicity assume that all writes can cause interrupts. */
3909 if (use_icount) { 3891 if (use_icount) {
3910 gen_io_end(); 3892 gen_io_end();
@@ -3913,12 +3895,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se @@ -3913,12 +3895,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3913 return; 3895 return;
3914 3896
3915 die: 3897 die:
3916 -#if defined MIPS_DEBUG_DISAS  
3917 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
3918 - fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",  
3919 - rn, reg, sel);  
3920 - }  
3921 -#endif 3898 + LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
3922 generate_exception(ctx, EXCP_RI); 3899 generate_exception(ctx, EXCP_RI);
3923 } 3900 }
3924 3901
@@ -4481,21 +4458,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s @@ -4481,21 +4458,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4481 default: 4458 default:
4482 goto die; 4459 goto die;
4483 } 4460 }
4484 -#if defined MIPS_DEBUG_DISAS  
4485 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
4486 - fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",  
4487 - rn, reg, sel);  
4488 - }  
4489 -#endif 4461 + LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
4490 return; 4462 return;
4491 4463
4492 die: 4464 die:
4493 -#if defined MIPS_DEBUG_DISAS  
4494 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
4495 - fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",  
4496 - rn, reg, sel);  
4497 - }  
4498 -#endif 4465 + LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
4499 generate_exception(ctx, EXCP_RI); 4466 generate_exception(ctx, EXCP_RI);
4500 } 4467 }
4501 4468
@@ -5072,12 +5039,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s @@ -5072,12 +5039,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5072 default: 5039 default:
5073 goto die; 5040 goto die;
5074 } 5041 }
5075 -#if defined MIPS_DEBUG_DISAS  
5076 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
5077 - fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",  
5078 - rn, reg, sel);  
5079 - }  
5080 -#endif 5042 + LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
5081 /* For simplicity assume that all writes can cause interrupts. */ 5043 /* For simplicity assume that all writes can cause interrupts. */
5082 if (use_icount) { 5044 if (use_icount) {
5083 gen_io_end(); 5045 gen_io_end();
@@ -5086,12 +5048,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s @@ -5086,12 +5048,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
5086 return; 5048 return;
5087 5049
5088 die: 5050 die:
5089 -#if defined MIPS_DEBUG_DISAS  
5090 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
5091 - fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",  
5092 - rn, reg, sel);  
5093 - }  
5094 -#endif 5051 + LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
5095 generate_exception(ctx, EXCP_RI); 5052 generate_exception(ctx, EXCP_RI);
5096 } 5053 }
5097 #endif /* TARGET_MIPS64 */ 5054 #endif /* TARGET_MIPS64 */
@@ -5249,24 +5206,14 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, @@ -5249,24 +5206,14 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5249 default: 5206 default:
5250 goto die; 5207 goto die;
5251 } 5208 }
5252 -#if defined MIPS_DEBUG_DISAS  
5253 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
5254 - fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",  
5255 - rt, u, sel, h);  
5256 - }  
5257 -#endif 5209 + LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
5258 gen_store_gpr(t0, rd); 5210 gen_store_gpr(t0, rd);
5259 tcg_temp_free(t0); 5211 tcg_temp_free(t0);
5260 return; 5212 return;
5261 5213
5262 die: 5214 die:
5263 tcg_temp_free(t0); 5215 tcg_temp_free(t0);
5264 -#if defined MIPS_DEBUG_DISAS  
5265 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
5266 - fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",  
5267 - rt, u, sel, h);  
5268 - }  
5269 -#endif 5216 + LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
5270 generate_exception(ctx, EXCP_RI); 5217 generate_exception(ctx, EXCP_RI);
5271 } 5218 }
5272 5219
@@ -5424,23 +5371,13 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, @@ -5424,23 +5371,13 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5424 default: 5371 default:
5425 goto die; 5372 goto die;
5426 } 5373 }
5427 -#if defined MIPS_DEBUG_DISAS  
5428 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
5429 - fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",  
5430 - rd, u, sel, h);  
5431 - }  
5432 -#endif 5374 + LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
5433 tcg_temp_free(t0); 5375 tcg_temp_free(t0);
5434 return; 5376 return;
5435 5377
5436 die: 5378 die:
5437 tcg_temp_free(t0); 5379 tcg_temp_free(t0);
5438 -#if defined MIPS_DEBUG_DISAS  
5439 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
5440 - fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",  
5441 - rd, u, sel, h);  
5442 - }  
5443 -#endif 5380 + LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
5444 generate_exception(ctx, EXCP_RI); 5381 generate_exception(ctx, EXCP_RI);
5445 } 5382 }
5446 5383
@@ -8272,11 +8209,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -8272,11 +8209,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
8272 cpu_dump_state(env, logfile, fprintf, 0); 8209 cpu_dump_state(env, logfile, fprintf, 0);
8273 } 8210 }
8274 #endif 8211 #endif
8275 -#ifdef MIPS_DEBUG_DISAS  
8276 - if (loglevel & CPU_LOG_TB_IN_ASM)  
8277 - fprintf(logfile, "\ntb %p idx %d hflags %04x\n",  
8278 - tb, ctx.mem_idx, ctx.hflags);  
8279 -#endif 8212 + LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
8280 gen_icount_start(); 8213 gen_icount_start();
8281 while (ctx.bstate == BS_NONE) { 8214 while (ctx.bstate == BS_NONE) {
8282 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { 8215 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
@@ -8364,10 +8297,7 @@ done_generating: @@ -8364,10 +8297,7 @@ done_generating:
8364 tb->icount = num_insns; 8297 tb->icount = num_insns;
8365 } 8298 }
8366 #ifdef DEBUG_DISAS 8299 #ifdef DEBUG_DISAS
8367 -#if defined MIPS_DEBUG_DISAS  
8368 - if (loglevel & CPU_LOG_TB_IN_ASM)  
8369 - fprintf(logfile, "\n");  
8370 -#endif 8300 + LOG_DISAS("\n");
8371 if (loglevel & CPU_LOG_TB_IN_ASM) { 8301 if (loglevel & CPU_LOG_TB_IN_ASM) {
8372 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); 8302 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
8373 target_disas(logfile, pc_start, ctx.pc - pc_start, 0); 8303 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
target-ppc/helper.c
  View file @d12d51d
@@ -39,6 +39,58 @@ @@ -39,6 +39,58 @@
39 //#define DEBUG_EXCEPTIONS 39 //#define DEBUG_EXCEPTIONS
40 //#define FLUSH_ALL_TLBS 40 //#define FLUSH_ALL_TLBS
41 41
  42 +#ifdef DEBUG_MMU
  43 +# define LOG_MMU(...) do { \
  44 + if (loglevel) \
  45 + fprintf(logfile, ## __VA_ARGS__); \
  46 + } while (0)
  47 +# define LOG_MMU_STATE(env) do { \
  48 + if (loglevel) \
  49 + cpu_dump_state(env, logfile, fprintf, 0); \
  50 + } while (0)
  51 +#else
  52 +# define LOG_MMU(...) do { } while (0)
  53 +# define LOG_MMU_STATE(...) do { } while (0)
  54 +#endif
  55 +
  56 +
  57 +#ifdef DEBUG_SOFTWARE_TLB
  58 +# define LOG_SWTLB(...) do { \
  59 + if (loglevel) \
  60 + fprintf(logfile, ## __VA_ARGS__); \
  61 + } while (0)
  62 +#else
  63 +# define LOG_SWTLB(...) do { } while (0)
  64 +#endif
  65 +
  66 +#ifdef DEBUG_BATS
  67 +# define LOG_BATS(...) do { \
  68 + if (loglevel) \
  69 + fprintf(logfile, ## __VA_ARGS__); \
  70 + } while (0)
  71 +#else
  72 +# define LOG_BATS(...) do { } while (0)
  73 +#endif
  74 +
  75 +#ifdef DEBUG_SLB
  76 +# define LOG_SLB(...) do { \
  77 + if (loglevel) \
  78 + fprintf(logfile, ## __VA_ARGS__); \
  79 + } while (0)
  80 +#else
  81 +# define LOG_SLB(...) do { } while (0)
  82 +#endif
  83 +
  84 +#ifdef DEBUG_EXCEPTIONS
  85 +# define LOG_EXCP(...) do { \
  86 + if (loglevel) \
  87 + fprintf(logfile, ## __VA_ARGS__); \
  88 + } while (0)
  89 +#else
  90 +# define LOG_EXCP(...) do { } while (0)
  91 +#endif
  92 +
  93 +
42 /*****************************************************************************/ 94 /*****************************************************************************/
43 /* PowerPC MMU emulation */ 95 /* PowerPC MMU emulation */
44 96
@@ -218,16 +270,10 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, @@ -218,16 +270,10 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
218 ret = check_prot(ctx->prot, rw, type); 270 ret = check_prot(ctx->prot, rw, type);
219 if (ret == 0) { 271 if (ret == 0) {
220 /* Access granted */ 272 /* Access granted */
221 -#if defined (DEBUG_MMU)  
222 - if (loglevel != 0)  
223 - fprintf(logfile, "PTE access granted !\n");  
224 -#endif 273 + LOG_MMU("PTE access granted !\n");
225 } else { 274 } else {
226 /* Access right violation */ 275 /* Access right violation */
227 -#if defined (DEBUG_MMU)  
228 - if (loglevel != 0)  
229 - fprintf(logfile, "PTE access rejected\n");  
230 -#endif 276 + LOG_MMU("PTE access rejected\n");
231 } 277 }
232 } 278 }
233 } 279 }
@@ -298,11 +344,7 @@ static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) @@ -298,11 +344,7 @@ static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
298 ppc6xx_tlb_t *tlb; 344 ppc6xx_tlb_t *tlb;
299 int nr, max; 345 int nr, max;
300 346
301 -#if defined (DEBUG_SOFTWARE_TLB) && 0  
302 - if (loglevel != 0) {  
303 - fprintf(logfile, "Invalidate all TLBs\n");  
304 - }  
305 -#endif 347 + //LOG_SWTLB("Invalidate all TLBs\n");
306 /* Invalidate all defined software TLB */ 348 /* Invalidate all defined software TLB */
307 max = env->nb_tlb; 349 max = env->nb_tlb;
308 if (env->id_tlbs == 1) 350 if (env->id_tlbs == 1)
@@ -328,12 +370,8 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, @@ -328,12 +370,8 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
328 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); 370 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
329 tlb = &env->tlb[nr].tlb6; 371 tlb = &env->tlb[nr].tlb6;
330 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { 372 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
331 -#if defined (DEBUG_SOFTWARE_TLB)  
332 - if (loglevel != 0) {  
333 - fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", 373 + LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n",
334 nr, env->nb_tlb, eaddr); 374 nr, env->nb_tlb, eaddr);
335 - }  
336 -#endif  
337 pte_invalidate(&tlb->pte0); 375 pte_invalidate(&tlb->pte0);
338 tlb_flush_page(env, tlb->EPN); 376 tlb_flush_page(env, tlb->EPN);
339 } 377 }
@@ -359,12 +397,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, @@ -359,12 +397,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
359 397
360 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); 398 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
361 tlb = &env->tlb[nr].tlb6; 399 tlb = &env->tlb[nr].tlb6;
362 -#if defined (DEBUG_SOFTWARE_TLB)  
363 - if (loglevel != 0) {  
364 - fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX 400 + LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
365 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); 401 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
366 - }  
367 -#endif  
368 /* Invalidate any pending reference in Qemu for this virtual address */ 402 /* Invalidate any pending reference in Qemu for this virtual address */
369 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1); 403 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
370 tlb->pte0 = pte0; 404 tlb->pte0 = pte0;
@@ -390,27 +424,19 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, @@ -390,27 +424,19 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
390 tlb = &env->tlb[nr].tlb6; 424 tlb = &env->tlb[nr].tlb6;
391 /* This test "emulates" the PTE index match for hardware TLBs */ 425 /* This test "emulates" the PTE index match for hardware TLBs */
392 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { 426 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
393 -#if defined (DEBUG_SOFTWARE_TLB)  
394 - if (loglevel != 0) {  
395 - fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX 427 + LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX
396 "] <> " ADDRX "\n", 428 "] <> " ADDRX "\n",
397 nr, env->nb_tlb, 429 nr, env->nb_tlb,
398 pte_is_valid(tlb->pte0) ? "valid" : "inval", 430 pte_is_valid(tlb->pte0) ? "valid" : "inval",
399 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); 431 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
400 - }  
401 -#endif  
402 continue; 432 continue;
403 } 433 }
404 -#if defined (DEBUG_SOFTWARE_TLB)  
405 - if (loglevel != 0) {  
406 - fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX 434 + LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
407 " %c %c\n", 435 " %c %c\n",
408 nr, env->nb_tlb, 436 nr, env->nb_tlb,
409 pte_is_valid(tlb->pte0) ? "valid" : "inval", 437 pte_is_valid(tlb->pte0) ? "valid" : "inval",
410 tlb->EPN, eaddr, tlb->pte1, 438 tlb->EPN, eaddr, tlb->pte1,
411 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); 439 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
412 - }  
413 -#endif  
414 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { 440 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
415 case -3: 441 case -3:
416 /* TLB inconsistency */ 442 /* TLB inconsistency */
@@ -437,12 +463,8 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, @@ -437,12 +463,8 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
437 } 463 }
438 if (best != -1) { 464 if (best != -1) {
439 done: 465 done:
440 -#if defined (DEBUG_SOFTWARE_TLB)  
441 - if (loglevel != 0) {  
442 - fprintf(logfile, "found TLB at addr " PADDRX " prot=%01x ret=%d\n", 466 + LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n",
443 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); 467 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
444 - }  
445 -#endif  
446 /* Update page flags */ 468 /* Update page flags */
447 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); 469 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
448 } 470 }
@@ -485,12 +507,8 @@ static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, @@ -485,12 +507,8 @@ static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
485 int key, pp, valid, prot; 507 int key, pp, valid, prot;
486 508
487 bl = (*BATl & 0x0000003F) << 17; 509 bl = (*BATl & 0x0000003F) << 17;
488 -#if defined (DEBUG_BATS)  
489 - if (loglevel != 0) {  
490 - fprintf(logfile, "b %02x ==> bl " ADDRX " msk " ADDRX "\n", 510 + LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n",
491 (uint8_t)(*BATl & 0x0000003F), bl, ~bl); 511 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
492 - }  
493 -#endif  
494 prot = 0; 512 prot = 0;
495 valid = (*BATl >> 6) & 1; 513 valid = (*BATl >> 6) & 1;
496 if (valid) { 514 if (valid) {
@@ -514,12 +532,8 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, @@ -514,12 +532,8 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
514 int i, valid, prot; 532 int i, valid, prot;
515 int ret = -1; 533 int ret = -1;
516 534
517 -#if defined (DEBUG_BATS)  
518 - if (loglevel != 0) {  
519 - fprintf(logfile, "%s: %cBAT v " ADDRX "\n", __func__, 535 + LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__,
520 type == ACCESS_CODE ? 'I' : 'D', virtual); 536 type == ACCESS_CODE ? 'I' : 'D', virtual);
521 - }  
522 -#endif  
523 switch (type) { 537 switch (type) {
524 case ACCESS_CODE: 538 case ACCESS_CODE:
525 BATlt = env->IBAT[1]; 539 BATlt = env->IBAT[1];
@@ -541,13 +555,9 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, @@ -541,13 +555,9 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
541 } else { 555 } else {
542 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); 556 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
543 } 557 }
544 -#if defined (DEBUG_BATS)  
545 - if (loglevel != 0) {  
546 - fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX 558 + LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
547 " BATl " ADDRX "\n", __func__, 559 " BATl " ADDRX "\n", __func__,
548 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); 560 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
549 - }  
550 -#endif  
551 if ((virtual & 0xF0000000) == BEPIu && 561 if ((virtual & 0xF0000000) == BEPIu &&
552 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) { 562 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
553 /* BAT matches */ 563 /* BAT matches */
@@ -559,28 +569,25 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, @@ -559,28 +569,25 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
559 /* Compute access rights */ 569 /* Compute access rights */
560 ctx->prot = prot; 570 ctx->prot = prot;
561 ret = check_prot(ctx->prot, rw, type); 571 ret = check_prot(ctx->prot, rw, type);
562 -#if defined (DEBUG_BATS)  
563 - if (ret == 0 && loglevel != 0) {  
564 - fprintf(logfile, "BAT %d match: r " PADDRX " prot=%c%c\n",  
565 - i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',  
566 - ctx->prot & PAGE_WRITE ? 'W' : '-');  
567 - }  
568 -#endif 572 + if (ret == 0)
  573 + LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n",
  574 + i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
  575 + ctx->prot & PAGE_WRITE ? 'W' : '-');
569 break; 576 break;
570 } 577 }
571 } 578 }
572 } 579 }
573 if (ret < 0) { 580 if (ret < 0) {
574 -#if defined (DEBUG_BATS)  
575 - if (loglevel != 0) {  
576 - fprintf(logfile, "no BAT match for " ADDRX ":\n", virtual); 581 +#if defined(DEBUG_BATS)
  582 + if (IS_LOGGING) {
  583 + QEMU_LOG0("no BAT match for " ADDRX ":\n", virtual);
577 for (i = 0; i < 4; i++) { 584 for (i = 0; i < 4; i++) {
578 BATu = &BATut[i]; 585 BATu = &BATut[i];
579 BATl = &BATlt[i]; 586 BATl = &BATlt[i];
580 BEPIu = *BATu & 0xF0000000; 587 BEPIu = *BATu & 0xF0000000;
581 BEPIl = *BATu & 0x0FFE0000; 588 BEPIl = *BATu & 0x0FFE0000;
582 bl = (*BATu & 0x00001FFC) << 15; 589 bl = (*BATu & 0x00001FFC) << 15;
583 - fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX 590 + QEMU_LOG0("%s: %cBAT%d v " ADDRX " BATu " ADDRX
584 " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n", 591 " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
585 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, 592 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
586 *BATu, *BATl, BEPIu, BEPIl, bl); 593 *BATu, *BATl, BEPIu, BEPIl, bl);
@@ -588,7 +595,6 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, @@ -588,7 +595,6 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
588 } 595 }
589 #endif 596 #endif
590 } 597 }
591 -  
592 /* No hit */ 598 /* No hit */
593 return ret; 599 return ret;
594 } 600 }
@@ -609,30 +615,22 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, @@ -609,30 +615,22 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
609 pte0 = ldq_phys(base + (i * 16)); 615 pte0 = ldq_phys(base + (i * 16));
610 pte1 = ldq_phys(base + (i * 16) + 8); 616 pte1 = ldq_phys(base + (i * 16) + 8);
611 r = pte64_check(ctx, pte0, pte1, h, rw, type); 617 r = pte64_check(ctx, pte0, pte1, h, rw, type);
612 -#if defined (DEBUG_MMU)  
613 - if (loglevel != 0) {  
614 - fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX 618 + LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
615 " %d %d %d " ADDRX "\n", 619 " %d %d %d " ADDRX "\n",
616 base + (i * 16), pte0, pte1, 620 base + (i * 16), pte0, pte1,
617 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), 621 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
618 ctx->ptem); 622 ctx->ptem);
619 - }  
620 -#endif  
621 } else 623 } else
622 #endif 624 #endif
623 { 625 {
624 pte0 = ldl_phys(base + (i * 8)); 626 pte0 = ldl_phys(base + (i * 8));
625 pte1 = ldl_phys(base + (i * 8) + 4); 627 pte1 = ldl_phys(base + (i * 8) + 4);
626 r = pte32_check(ctx, pte0, pte1, h, rw, type); 628 r = pte32_check(ctx, pte0, pte1, h, rw, type);
627 -#if defined (DEBUG_MMU)  
628 - if (loglevel != 0) {  
629 - fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX 629 + LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
630 " %d %d %d " ADDRX "\n", 630 " %d %d %d " ADDRX "\n",
631 base + (i * 8), pte0, pte1, 631 base + (i * 8), pte0, pte1,
632 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), 632 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
633 ctx->ptem); 633 ctx->ptem);
634 - }  
635 -#endif  
636 } 634 }
637 switch (r) { 635 switch (r) {
638 case -3: 636 case -3:
@@ -660,12 +658,8 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, @@ -660,12 +658,8 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
660 } 658 }
661 if (good != -1) { 659 if (good != -1) {
662 done: 660 done:
663 -#if defined (DEBUG_MMU)  
664 - if (loglevel != 0) {  
665 - fprintf(logfile, "found PTE at addr " PADDRX " prot=%01x ret=%d\n", 661 + LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n",
666 ctx->raddr, ctx->prot, ret); 662 ctx->raddr, ctx->prot, ret);
667 - }  
668 -#endif  
669 /* Update page flags */ 663 /* Update page flags */
670 pte1 = ctx->raddr; 664 pte1 = ctx->raddr;
671 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { 665 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
@@ -729,22 +723,14 @@ static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, @@ -729,22 +723,14 @@ static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
729 723
730 ret = -5; 724 ret = -5;
731 sr_base = env->spr[SPR_ASR]; 725 sr_base = env->spr[SPR_ASR];
732 -#if defined(DEBUG_SLB)  
733 - if (loglevel != 0) {  
734 - fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n", 726 + LOG_SLB("%s: eaddr " ADDRX " base " PADDRX "\n",
735 __func__, eaddr, sr_base); 727 __func__, eaddr, sr_base);
736 - }  
737 -#endif  
738 mask = 0x0000000000000000ULL; /* Avoid gcc warning */ 728 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
739 for (n = 0; n < env->slb_nr; n++) { 729 for (n = 0; n < env->slb_nr; n++) {
740 tmp64 = ldq_phys(sr_base); 730 tmp64 = ldq_phys(sr_base);
741 tmp = ldl_phys(sr_base + 8); 731 tmp = ldl_phys(sr_base + 8);
742 -#if defined(DEBUG_SLB)  
743 - if (loglevel != 0) {  
744 - fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08" 732 + LOG_SLB("%s: seg %d " PADDRX " %016" PRIx64 " %08"
745 PRIx32 "\n", __func__, n, sr_base, tmp64, tmp); 733 PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
746 - }  
747 -#endif  
748 if (slb_is_valid(tmp64)) { 734 if (slb_is_valid(tmp64)) {
749 /* SLB entry is valid */ 735 /* SLB entry is valid */
750 switch (tmp64 & 0x0000000006000000ULL) { 736 switch (tmp64 & 0x0000000006000000ULL) {
@@ -848,12 +834,8 @@ target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr) @@ -848,12 +834,8 @@ target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
848 } else { 834 } else {
849 rt = 0; 835 rt = 0;
850 } 836 }
851 -#if defined(DEBUG_SLB)  
852 - if (loglevel != 0) {  
853 - fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d " 837 + LOG_SLB("%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
854 ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt); 838 ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
855 - }  
856 -#endif  
857 839
858 return rt; 840 return rt;
859 } 841 }
@@ -875,13 +857,9 @@ void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs) @@ -875,13 +857,9 @@ void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
875 tmp64 |= 1 << 27; 857 tmp64 |= 1 << 27;
876 /* Set ESID */ 858 /* Set ESID */
877 tmp64 |= (uint32_t)slb_nr << 28; 859 tmp64 |= (uint32_t)slb_nr << 28;
878 -#if defined(DEBUG_SLB)  
879 - if (loglevel != 0) {  
880 - fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 860 + LOG_SLB("%s: %d " ADDRX " => " PADDRX " %016" PRIx64
881 " %08" PRIx32 "\n", __func__, 861 " %08" PRIx32 "\n", __func__,
882 slb_nr, rs, sr_base, tmp64, tmp); 862 slb_nr, rs, sr_base, tmp64, tmp);
883 - }  
884 -#endif  
885 /* Write SLB entry to memory */ 863 /* Write SLB entry to memory */
886 stq_phys(sr_base, tmp64); 864 stq_phys(sr_base, tmp64);
887 stl_phys(sr_base + 8, tmp); 865 stl_phys(sr_base + 8, tmp);
@@ -911,11 +889,7 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, @@ -911,11 +889,7 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
911 pr = msr_pr; 889 pr = msr_pr;
912 #if defined(TARGET_PPC64) 890 #if defined(TARGET_PPC64)
913 if (env->mmu_model & POWERPC_MMU_64) { 891 if (env->mmu_model & POWERPC_MMU_64) {
914 -#if defined (DEBUG_MMU)  
915 - if (loglevel != 0) {  
916 - fprintf(logfile, "Check SLBs\n");  
917 - }  
918 -#endif 892 + LOG_MMU("Check SLBs\n");
919 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); 893 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
920 if (ret < 0) 894 if (ret < 0)
921 return ret; 895 return ret;
@@ -941,22 +915,14 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, @@ -941,22 +915,14 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
941 vsid_sh = 6; 915 vsid_sh = 6;
942 sdr_sh = 16; 916 sdr_sh = 16;
943 sdr_mask = 0xFFC0; 917 sdr_mask = 0xFFC0;
944 -#if defined (DEBUG_MMU)  
945 - if (loglevel != 0) {  
946 - fprintf(logfile, "Check segment v=" ADDRX " %d " ADDRX 918 + LOG_MMU("Check segment v=" ADDRX " %d " ADDRX
947 " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n", 919 " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
948 eaddr, (int)(eaddr >> 28), sr, env->nip, 920 eaddr, (int)(eaddr >> 28), sr, env->nip,
949 env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, 921 env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
950 rw, type); 922 rw, type);
951 - }  
952 -#endif  
953 } 923 }
954 -#if defined (DEBUG_MMU)  
955 - if (loglevel != 0) {  
956 - fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", 924 + LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
957 ctx->key, ds, ctx->nx, vsid); 925 ctx->key, ds, ctx->nx, vsid);
958 - }  
959 -#endif  
960 ret = -1; 926 ret = -1;
961 if (!ds) { 927 if (!ds) {
962 /* Check if instruction fetch is allowed, if needed */ 928 /* Check if instruction fetch is allowed, if needed */
@@ -977,23 +943,15 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, @@ -977,23 +943,15 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
977 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; 943 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
978 } 944 }
979 mask = (htab_mask << sdr_sh) | sdr_mask; 945 mask = (htab_mask << sdr_sh) | sdr_mask;
980 -#if defined (DEBUG_MMU)  
981 - if (loglevel != 0) {  
982 - fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX 946 + LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
983 " mask " PADDRX " " ADDRX "\n", 947 " mask " PADDRX " " ADDRX "\n",
984 sdr, sdr_sh, hash, mask, page_mask); 948 sdr, sdr_sh, hash, mask, page_mask);
985 - }  
986 -#endif  
987 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask); 949 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
988 /* Secondary table address */ 950 /* Secondary table address */
989 hash = (~hash) & vsid_mask; 951 hash = (~hash) & vsid_mask;
990 -#if defined (DEBUG_MMU)  
991 - if (loglevel != 0) {  
992 - fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX 952 + LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
993 " mask " PADDRX "\n", 953 " mask " PADDRX "\n",
994 sdr, sdr_sh, hash, mask); 954 sdr, sdr_sh, hash, mask);
995 - }  
996 -#endif  
997 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask); 955 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
998 #if defined(TARGET_PPC64) 956 #if defined(TARGET_PPC64)
999 if (env->mmu_model & POWERPC_MMU_64) { 957 if (env->mmu_model & POWERPC_MMU_64) {
@@ -1011,26 +969,19 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, @@ -1011,26 +969,19 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
1011 /* Software TLB search */ 969 /* Software TLB search */
1012 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); 970 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
1013 } else { 971 } else {
1014 -#if defined (DEBUG_MMU)  
1015 - if (loglevel != 0) {  
1016 - fprintf(logfile, "0 sdr1=" PADDRX " vsid=" ADDRX " " 972 + LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " "
1017 "api=" ADDRX " hash=" PADDRX 973 "api=" ADDRX " hash=" PADDRX
1018 " pg_addr=" PADDRX "\n", 974 " pg_addr=" PADDRX "\n",
1019 sdr, vsid, pgidx, hash, ctx->pg_addr[0]); 975 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
1020 - }  
1021 -#endif  
1022 /* Primary table lookup */ 976 /* Primary table lookup */
1023 ret = find_pte(env, ctx, 0, rw, type); 977 ret = find_pte(env, ctx, 0, rw, type);
1024 if (ret < 0) { 978 if (ret < 0) {
1025 /* Secondary table lookup */ 979 /* Secondary table lookup */
1026 -#if defined (DEBUG_MMU)  
1027 - if (eaddr != 0xEFFFFFFF && loglevel != 0) {  
1028 - fprintf(logfile, "1 sdr1=" PADDRX " vsid=" ADDRX " " 980 + if (eaddr != 0xEFFFFFFF)
  981 + LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " "
1029 "api=" ADDRX " hash=" PADDRX 982 "api=" ADDRX " hash=" PADDRX
1030 " pg_addr=" PADDRX "\n", 983 " pg_addr=" PADDRX "\n",
1031 sdr, vsid, pgidx, hash, ctx->pg_addr[1]); 984 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
1032 - }  
1033 -#endif  
1034 ret2 = find_pte(env, ctx, 1, rw, type); 985 ret2 = find_pte(env, ctx, 1, rw, type);
1035 if (ret2 != -1) 986 if (ret2 != -1)
1036 ret = ret2; 987 ret = ret2;
@@ -1056,17 +1007,11 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, @@ -1056,17 +1007,11 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
1056 } 1007 }
1057 #endif 1008 #endif
1058 } else { 1009 } else {
1059 -#if defined (DEBUG_MMU)  
1060 - if (loglevel != 0)  
1061 - fprintf(logfile, "No access allowed\n");  
1062 -#endif 1010 + LOG_MMU("No access allowed\n");
1063 ret = -3; 1011 ret = -3;
1064 } 1012 }
1065 } else { 1013 } else {
1066 -#if defined (DEBUG_MMU)  
1067 - if (loglevel != 0)  
1068 - fprintf(logfile, "direct store...\n");  
1069 -#endif 1014 + LOG_MMU("direct store...\n");
1070 /* Direct-store segment : absolutely *BUGGY* for now */ 1015 /* Direct-store segment : absolutely *BUGGY* for now */
1071 switch (type) { 1016 switch (type) {
1072 case ACCESS_INT: 1017 case ACCESS_INT:
@@ -1124,13 +1069,9 @@ static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, @@ -1124,13 +1069,9 @@ static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
1124 return -1; 1069 return -1;
1125 } 1070 }
1126 mask = ~(tlb->size - 1); 1071 mask = ~(tlb->size - 1);
1127 -#if defined (DEBUG_SOFTWARE_TLB)  
1128 - if (loglevel != 0) {  
1129 - fprintf(logfile, "%s: TLB %d address " ADDRX " PID %u <=> " ADDRX 1072 + LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
1130 " " ADDRX " %u\n", 1073 " " ADDRX " %u\n",
1131 __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID); 1074 __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
1132 - }  
1133 -#endif  
1134 /* Check PID */ 1075 /* Check PID */
1135 if (tlb->PID != 0 && tlb->PID != pid) 1076 if (tlb->PID != 0 && tlb->PID != pid)
1136 return -1; 1077 return -1;
@@ -1223,12 +1164,8 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, @@ -1223,12 +1164,8 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1223 continue; 1164 continue;
1224 zsel = (tlb->attr >> 4) & 0xF; 1165 zsel = (tlb->attr >> 4) & 0xF;
1225 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; 1166 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
1226 -#if defined (DEBUG_SOFTWARE_TLB)  
1227 - if (loglevel != 0) {  
1228 - fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n", 1167 + LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1229 __func__, i, zsel, zpr, rw, tlb->attr); 1168 __func__, i, zsel, zpr, rw, tlb->attr);
1230 - }  
1231 -#endif  
1232 /* Check execute enable bit */ 1169 /* Check execute enable bit */
1233 switch (zpr) { 1170 switch (zpr) {
1234 case 0x2: 1171 case 0x2:
@@ -1258,23 +1195,15 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, @@ -1258,23 +1195,15 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1258 } 1195 }
1259 if (ret >= 0) { 1196 if (ret >= 0) {
1260 ctx->raddr = raddr; 1197 ctx->raddr = raddr;
1261 -#if defined (DEBUG_SOFTWARE_TLB)  
1262 - if (loglevel != 0) {  
1263 - fprintf(logfile, "%s: access granted " ADDRX " => " PADDRX 1198 + LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX
1264 " %d %d\n", __func__, address, ctx->raddr, ctx->prot, 1199 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1265 ret); 1200 ret);
1266 - }  
1267 -#endif  
1268 return 0; 1201 return 0;
1269 } 1202 }
1270 } 1203 }
1271 -#if defined (DEBUG_SOFTWARE_TLB)  
1272 - if (loglevel != 0) {  
1273 - fprintf(logfile, "%s: access refused " ADDRX " => " PADDRX 1204 + LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX
1274 " %d %d\n", __func__, address, raddr, ctx->prot, 1205 " %d %d\n", __func__, address, raddr, ctx->prot,
1275 ret); 1206 ret);
1276 - }  
1277 -#endif  
1278 1207
1279 return ret; 1208 return ret;
1280 } 1209 }
@@ -1500,10 +1429,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, @@ -1500,10 +1429,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1500 ctx.raddr & TARGET_PAGE_MASK, ctx.prot, 1429 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1501 mmu_idx, is_softmmu); 1430 mmu_idx, is_softmmu);
1502 } else if (ret < 0) { 1431 } else if (ret < 0) {
1503 -#if defined (DEBUG_MMU)  
1504 - if (loglevel != 0)  
1505 - cpu_dump_state(env, logfile, fprintf, 0);  
1506 -#endif 1432 + LOG_MMU_STATE(env);
1507 if (access_type == ACCESS_CODE) { 1433 if (access_type == ACCESS_CODE) {
1508 switch (ret) { 1434 switch (ret) {
1509 case -1: 1435 case -1:
@@ -1753,30 +1679,19 @@ static always_inline void do_invalidate_BAT (CPUPPCState *env, @@ -1753,30 +1679,19 @@ static always_inline void do_invalidate_BAT (CPUPPCState *env,
1753 1679
1754 base = BATu & ~0x0001FFFF; 1680 base = BATu & ~0x0001FFFF;
1755 end = base + mask + 0x00020000; 1681 end = base + mask + 0x00020000;
1756 -#if defined (DEBUG_BATS)  
1757 - if (loglevel != 0) {  
1758 - fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", 1682 + LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1759 base, end, mask); 1683 base, end, mask);
1760 - }  
1761 -#endif  
1762 for (page = base; page != end; page += TARGET_PAGE_SIZE) 1684 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1763 tlb_flush_page(env, page); 1685 tlb_flush_page(env, page);
1764 -#if defined (DEBUG_BATS)  
1765 - if (loglevel != 0)  
1766 - fprintf(logfile, "Flush done\n");  
1767 -#endif 1686 + LOG_BATS("Flush done\n");
1768 } 1687 }
1769 #endif 1688 #endif
1770 1689
1771 static always_inline void dump_store_bat (CPUPPCState *env, char ID, 1690 static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1772 int ul, int nr, target_ulong value) 1691 int ul, int nr, target_ulong value)
1773 { 1692 {
1774 -#if defined (DEBUG_BATS)  
1775 - if (loglevel != 0) {  
1776 - fprintf(logfile, "Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n", 1693 + LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
1777 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); 1694 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1778 - }  
1779 -#endif  
1780 } 1695 }
1781 1696
1782 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) 1697 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
@@ -2046,11 +1961,7 @@ void ppc_store_asr (CPUPPCState *env, target_ulong value) @@ -2046,11 +1961,7 @@ void ppc_store_asr (CPUPPCState *env, target_ulong value)
2046 1961
2047 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value) 1962 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
2048 { 1963 {
2049 -#if defined (DEBUG_MMU)  
2050 - if (loglevel != 0) {  
2051 - fprintf(logfile, "%s: " ADDRX "\n", __func__, value);  
2052 - }  
2053 -#endif 1964 + LOG_MMU("%s: " ADDRX "\n", __func__, value);
2054 if (env->sdr1 != value) { 1965 if (env->sdr1 != value) {
2055 /* XXX: for PowerPC 64, should check that the HTABSIZE value 1966 /* XXX: for PowerPC 64, should check that the HTABSIZE value
2056 * is <= 28 1967 * is <= 28
@@ -2062,12 +1973,8 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value) @@ -2062,12 +1973,8 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
2062 1973
2063 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) 1974 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
2064 { 1975 {
2065 -#if defined (DEBUG_MMU)  
2066 - if (loglevel != 0) {  
2067 - fprintf(logfile, "%s: reg=%d " ADDRX " " ADDRX "\n", 1976 + LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n",
2068 __func__, srnum, value, env->sr[srnum]); 1977 __func__, srnum, value, env->sr[srnum]);
2069 - }  
2070 -#endif  
2071 if (env->sr[srnum] != value) { 1978 if (env->sr[srnum] != value) {
2072 env->sr[srnum] = value; 1979 env->sr[srnum] = value;
2073 #if !defined(FLUSH_ALL_TLBS) && 0 1980 #if !defined(FLUSH_ALL_TLBS) && 0
@@ -2205,23 +2112,15 @@ static always_inline void powerpc_excp (CPUState *env, @@ -2205,23 +2112,15 @@ static always_inline void powerpc_excp (CPUState *env,
2205 } 2112 }
2206 goto store_next; 2113 goto store_next;
2207 case POWERPC_EXCP_DSI: /* Data storage exception */ 2114 case POWERPC_EXCP_DSI: /* Data storage exception */
2208 -#if defined (DEBUG_EXCEPTIONS)  
2209 - if (loglevel != 0) {  
2210 - fprintf(logfile, "DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n", 2115 + LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
2211 env->spr[SPR_DSISR], env->spr[SPR_DAR]); 2116 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2212 - }  
2213 -#endif  
2214 new_msr &= ~((target_ulong)1 << MSR_RI); 2117 new_msr &= ~((target_ulong)1 << MSR_RI);
2215 if (lpes1 == 0) 2118 if (lpes1 == 0)
2216 new_msr |= (target_ulong)MSR_HVB; 2119 new_msr |= (target_ulong)MSR_HVB;
2217 goto store_next; 2120 goto store_next;
2218 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 2121 case POWERPC_EXCP_ISI: /* Instruction storage exception */
2219 -#if defined (DEBUG_EXCEPTIONS)  
2220 - if (loglevel != 0) {  
2221 - fprintf(logfile, "ISI exception: msr=" ADDRX ", nip=" ADDRX "\n", 2122 + LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
2222 msr, env->nip); 2123 msr, env->nip);
2223 - }  
2224 -#endif  
2225 new_msr &= ~((target_ulong)1 << MSR_RI); 2124 new_msr &= ~((target_ulong)1 << MSR_RI);
2226 if (lpes1 == 0) 2125 if (lpes1 == 0)
2227 new_msr |= (target_ulong)MSR_HVB; 2126 new_msr |= (target_ulong)MSR_HVB;
@@ -2244,11 +2143,7 @@ static always_inline void powerpc_excp (CPUState *env, @@ -2244,11 +2143,7 @@ static always_inline void powerpc_excp (CPUState *env,
2244 switch (env->error_code & ~0xF) { 2143 switch (env->error_code & ~0xF) {
2245 case POWERPC_EXCP_FP: 2144 case POWERPC_EXCP_FP:
2246 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { 2145 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2247 -#if defined (DEBUG_EXCEPTIONS)  
2248 - if (loglevel != 0) {  
2249 - fprintf(logfile, "Ignore floating point exception\n");  
2250 - }  
2251 -#endif 2146 + LOG_EXCP("Ignore floating point exception\n");
2252 env->exception_index = POWERPC_EXCP_NONE; 2147 env->exception_index = POWERPC_EXCP_NONE;
2253 env->error_code = 0; 2148 env->error_code = 0;
2254 return; 2149 return;
@@ -2262,12 +2157,8 @@ static always_inline void powerpc_excp (CPUState *env, @@ -2262,12 +2157,8 @@ static always_inline void powerpc_excp (CPUState *env,
2262 msr |= 0x00010000; 2157 msr |= 0x00010000;
2263 break; 2158 break;
2264 case POWERPC_EXCP_INVAL: 2159 case POWERPC_EXCP_INVAL:
2265 -#if defined (DEBUG_EXCEPTIONS)  
2266 - if (loglevel != 0) {  
2267 - fprintf(logfile, "Invalid instruction at " ADDRX "\n", 2160 + LOG_EXCP("Invalid instruction at " ADDRX "\n",
2268 env->nip); 2161 env->nip);
2269 - }  
2270 -#endif  
2271 new_msr &= ~((target_ulong)1 << MSR_RI); 2162 new_msr &= ~((target_ulong)1 << MSR_RI);
2272 if (lpes1 == 0) 2163 if (lpes1 == 0)
2273 new_msr |= (target_ulong)MSR_HVB; 2164 new_msr |= (target_ulong)MSR_HVB;
@@ -2327,17 +2218,11 @@ static always_inline void powerpc_excp (CPUState *env, @@ -2327,17 +2218,11 @@ static always_inline void powerpc_excp (CPUState *env,
2327 goto store_next; 2218 goto store_next;
2328 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 2219 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2329 /* FIT on 4xx */ 2220 /* FIT on 4xx */
2330 -#if defined (DEBUG_EXCEPTIONS)  
2331 - if (loglevel != 0)  
2332 - fprintf(logfile, "FIT exception\n");  
2333 -#endif 2221 + LOG_EXCP("FIT exception\n");
2334 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ 2222 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2335 goto store_next; 2223 goto store_next;
2336 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 2224 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2337 -#if defined (DEBUG_EXCEPTIONS)  
2338 - if (loglevel != 0)  
2339 - fprintf(logfile, "WDT exception\n");  
2340 -#endif 2225 + LOG_EXCP("WDT exception\n");
2341 switch (excp_model) { 2226 switch (excp_model) {
2342 case POWERPC_EXCP_BOOKE: 2227 case POWERPC_EXCP_BOOKE:
2343 srr0 = SPR_BOOKE_CSRR0; 2228 srr0 = SPR_BOOKE_CSRR0;
@@ -2458,10 +2343,7 @@ static always_inline void powerpc_excp (CPUState *env, @@ -2458,10 +2343,7 @@ static always_inline void powerpc_excp (CPUState *env,
2458 new_msr |= (target_ulong)MSR_HVB; 2343 new_msr |= (target_ulong)MSR_HVB;
2459 goto store_current; 2344 goto store_current;
2460 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ 2345 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2461 -#if defined (DEBUG_EXCEPTIONS)  
2462 - if (loglevel != 0)  
2463 - fprintf(logfile, "PIT exception\n");  
2464 -#endif 2346 + LOG_EXCP("PIT exception\n");
2465 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ 2347 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2466 goto store_next; 2348 goto store_next;
2467 case POWERPC_EXCP_IO: /* IO error exception */ 2349 case POWERPC_EXCP_IO: /* IO error exception */
target-ppc/op_helper.c
  View file @d12d51d
@@ -28,6 +28,16 @@ @@ -28,6 +28,16 @@
28 //#define DEBUG_EXCEPTIONS 28 //#define DEBUG_EXCEPTIONS
29 //#define DEBUG_SOFTWARE_TLB 29 //#define DEBUG_SOFTWARE_TLB
30 30
  31 +#ifdef DEBUG_SOFTWARE_TLB
  32 +# define LOG_SWTLB(...) do { \
  33 + if (loglevel) \
  34 + fprintf(logfile, ## __VA_ARGS__); \
  35 + } while (0)
  36 +#else
  37 +# define LOG_SWTLB(...) do { } while (0)
  38 +#endif
  39 +
  40 +
31 /*****************************************************************************/ 41 /*****************************************************************************/
32 /* Exceptions processing helpers */ 42 /* Exceptions processing helpers */
33 43
@@ -3564,13 +3574,9 @@ static void do_6xx_tlb (target_ulong new_EPN, int is_code) @@ -3564,13 +3574,9 @@ static void do_6xx_tlb (target_ulong new_EPN, int is_code)
3564 EPN = env->spr[SPR_DMISS]; 3574 EPN = env->spr[SPR_DMISS];
3565 } 3575 }
3566 way = (env->spr[SPR_SRR1] >> 17) & 1; 3576 way = (env->spr[SPR_SRR1] >> 17) & 1;
3567 -#if defined (DEBUG_SOFTWARE_TLB)  
3568 - if (loglevel != 0) {  
3569 - fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX 3577 + LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
3570 " PTE1 " ADDRX " way %d\n", 3578 " PTE1 " ADDRX " way %d\n",
3571 __func__, new_EPN, EPN, CMP, RPN, way); 3579 __func__, new_EPN, EPN, CMP, RPN, way);
3572 - }  
3573 -#endif  
3574 /* Store this TLB */ 3580 /* Store this TLB */
3575 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK), 3581 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
3576 way, is_code, CMP, RPN); 3582 way, is_code, CMP, RPN);
@@ -3596,13 +3602,9 @@ static void do_74xx_tlb (target_ulong new_EPN, int is_code) @@ -3596,13 +3602,9 @@ static void do_74xx_tlb (target_ulong new_EPN, int is_code)
3596 CMP = env->spr[SPR_PTEHI]; 3602 CMP = env->spr[SPR_PTEHI];
3597 EPN = env->spr[SPR_TLBMISS] & ~0x3; 3603 EPN = env->spr[SPR_TLBMISS] & ~0x3;
3598 way = env->spr[SPR_TLBMISS] & 0x3; 3604 way = env->spr[SPR_TLBMISS] & 0x3;
3599 -#if defined (DEBUG_SOFTWARE_TLB)  
3600 - if (loglevel != 0) {  
3601 - fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX 3605 + LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
3602 " PTE1 " ADDRX " way %d\n", 3606 " PTE1 " ADDRX " way %d\n",
3603 __func__, new_EPN, EPN, CMP, RPN, way); 3607 __func__, new_EPN, EPN, CMP, RPN, way);
3604 - }  
3605 -#endif  
3606 /* Store this TLB */ 3608 /* Store this TLB */
3607 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK), 3609 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
3608 way, is_code, CMP, RPN); 3610 way, is_code, CMP, RPN);
@@ -3726,22 +3728,14 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val) @@ -3726,22 +3728,14 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
3726 ppcemb_tlb_t *tlb; 3728 ppcemb_tlb_t *tlb;
3727 target_ulong page, end; 3729 target_ulong page, end;
3728 3730
3729 -#if defined (DEBUG_SOFTWARE_TLB)  
3730 - if (loglevel != 0) {  
3731 - fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);  
3732 - }  
3733 -#endif 3731 + LOG_SWTLB("%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
3734 entry &= 0x3F; 3732 entry &= 0x3F;
3735 tlb = &env->tlb[entry].tlbe; 3733 tlb = &env->tlb[entry].tlbe;
3736 /* Invalidate previous TLB (if it's valid) */ 3734 /* Invalidate previous TLB (if it's valid) */
3737 if (tlb->prot & PAGE_VALID) { 3735 if (tlb->prot & PAGE_VALID) {
3738 end = tlb->EPN + tlb->size; 3736 end = tlb->EPN + tlb->size;
3739 -#if defined (DEBUG_SOFTWARE_TLB)  
3740 - if (loglevel != 0) {  
3741 - fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX 3737 + LOG_SWTLB("%s: invalidate old TLB %d start " ADDRX
3742 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end); 3738 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
3743 - }  
3744 -#endif  
3745 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) 3739 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3746 tlb_flush_page(env, page); 3740 tlb_flush_page(env, page);
3747 } 3741 }
@@ -3766,26 +3760,18 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val) @@ -3766,26 +3760,18 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
3766 } 3760 }
3767 tlb->PID = env->spr[SPR_40x_PID]; /* PID */ 3761 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
3768 tlb->attr = val & 0xFF; 3762 tlb->attr = val & 0xFF;
3769 -#if defined (DEBUG_SOFTWARE_TLB)  
3770 - if (loglevel != 0) {  
3771 - fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX 3763 + LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3772 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, 3764 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3773 (int)entry, tlb->RPN, tlb->EPN, tlb->size, 3765 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3774 tlb->prot & PAGE_READ ? 'r' : '-', 3766 tlb->prot & PAGE_READ ? 'r' : '-',
3775 tlb->prot & PAGE_WRITE ? 'w' : '-', 3767 tlb->prot & PAGE_WRITE ? 'w' : '-',
3776 tlb->prot & PAGE_EXEC ? 'x' : '-', 3768 tlb->prot & PAGE_EXEC ? 'x' : '-',
3777 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); 3769 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3778 - }  
3779 -#endif  
3780 /* Invalidate new TLB (if valid) */ 3770 /* Invalidate new TLB (if valid) */
3781 if (tlb->prot & PAGE_VALID) { 3771 if (tlb->prot & PAGE_VALID) {
3782 end = tlb->EPN + tlb->size; 3772 end = tlb->EPN + tlb->size;
3783 -#if defined (DEBUG_SOFTWARE_TLB)  
3784 - if (loglevel != 0) {  
3785 - fprintf(logfile, "%s: invalidate TLB %d start " ADDRX 3773 + LOG_SWTLB("%s: invalidate TLB %d start " ADDRX
3786 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end); 3774 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
3787 - }  
3788 -#endif  
3789 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) 3775 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3790 tlb_flush_page(env, page); 3776 tlb_flush_page(env, page);
3791 } 3777 }
@@ -3795,11 +3781,7 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val) @@ -3795,11 +3781,7 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
3795 { 3781 {
3796 ppcemb_tlb_t *tlb; 3782 ppcemb_tlb_t *tlb;
3797 3783
3798 -#if defined (DEBUG_SOFTWARE_TLB)  
3799 - if (loglevel != 0) {  
3800 - fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);  
3801 - }  
3802 -#endif 3784 + LOG_SWTLB("%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
3803 entry &= 0x3F; 3785 entry &= 0x3F;
3804 tlb = &env->tlb[entry].tlbe; 3786 tlb = &env->tlb[entry].tlbe;
3805 tlb->RPN = val & 0xFFFFFC00; 3787 tlb->RPN = val & 0xFFFFFC00;
@@ -3808,17 +3790,13 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val) @@ -3808,17 +3790,13 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
3808 tlb->prot |= PAGE_EXEC; 3790 tlb->prot |= PAGE_EXEC;
3809 if (val & 0x100) 3791 if (val & 0x100)
3810 tlb->prot |= PAGE_WRITE; 3792 tlb->prot |= PAGE_WRITE;
3811 -#if defined (DEBUG_SOFTWARE_TLB)  
3812 - if (loglevel != 0) {  
3813 - fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX 3793 + LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3814 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, 3794 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3815 (int)entry, tlb->RPN, tlb->EPN, tlb->size, 3795 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3816 tlb->prot & PAGE_READ ? 'r' : '-', 3796 tlb->prot & PAGE_READ ? 'r' : '-',
3817 tlb->prot & PAGE_WRITE ? 'w' : '-', 3797 tlb->prot & PAGE_WRITE ? 'w' : '-',
3818 tlb->prot & PAGE_EXEC ? 'x' : '-', 3798 tlb->prot & PAGE_EXEC ? 'x' : '-',
3819 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); 3799 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3820 - }  
3821 -#endif  
3822 } 3800 }
3823 3801
3824 target_ulong helper_4xx_tlbsx (target_ulong address) 3802 target_ulong helper_4xx_tlbsx (target_ulong address)
@@ -3833,12 +3811,8 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value) @@ -3833,12 +3811,8 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3833 target_ulong EPN, RPN, size; 3811 target_ulong EPN, RPN, size;
3834 int do_flush_tlbs; 3812 int do_flush_tlbs;
3835 3813
3836 -#if defined (DEBUG_SOFTWARE_TLB)  
3837 - if (loglevel != 0) {  
3838 - fprintf(logfile, "%s word %d entry %d value " ADDRX "\n", 3814 + LOG_SWTLB("%s word %d entry %d value " ADDRX "\n",
3839 __func__, word, (int)entry, value); 3815 __func__, word, (int)entry, value);
3840 - }  
3841 -#endif  
3842 do_flush_tlbs = 0; 3816 do_flush_tlbs = 0;
3843 entry &= 0x3F; 3817 entry &= 0x3F;
3844 tlb = &env->tlb[entry].tlbe; 3818 tlb = &env->tlb[entry].tlbe;
target-ppc/translate.c
  View file @d12d51d
@@ -42,6 +42,14 @@ @@ -42,6 +42,14 @@
42 //#define PPC_DEBUG_DISAS 42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS 43 //#define DO_PPC_STATISTICS
44 44
  45 +#ifdef PPC_DEBUG_DISAS
  46 +# define LOG_DISAS(...) do { \
  47 + if (loglevel & CPU_LOG_TB_IN_ASM) \
  48 + fprintf(logfile, ## __VA_ARGS__); \
  49 + } while (0)
  50 +#else
  51 +# define LOG_DISAS(...) do { } while (0)
  52 +#endif
45 /*****************************************************************************/ 53 /*****************************************************************************/
46 /* Code translation helpers */ 54 /* Code translation helpers */
47 55
@@ -8232,13 +8240,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -8232,13 +8240,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
8232 gen_opc_icount[lj] = num_insns; 8240 gen_opc_icount[lj] = num_insns;
8233 } 8241 }
8234 } 8242 }
8235 -#if defined PPC_DEBUG_DISAS  
8236 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
8237 - fprintf(logfile, "----------------\n");  
8238 - fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",  
8239 - ctx.nip, ctx.mem_idx, (int)msr_ir);  
8240 - }  
8241 -#endif 8243 + LOG_DISAS("----------------\n");
  8244 + LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
  8245 + ctx.nip, ctx.mem_idx, (int)msr_ir);
8242 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) 8246 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8243 gen_io_start(); 8247 gen_io_start();
8244 if (unlikely(ctx.le_mode)) { 8248 if (unlikely(ctx.le_mode)) {
@@ -8246,13 +8250,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -8246,13 +8250,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
8246 } else { 8250 } else {
8247 ctx.opcode = ldl_code(ctx.nip); 8251 ctx.opcode = ldl_code(ctx.nip);
8248 } 8252 }
8249 -#if defined PPC_DEBUG_DISAS  
8250 - if (loglevel & CPU_LOG_TB_IN_ASM) {  
8251 - fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n", 8253 + LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8252 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), 8254 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8253 opc3(ctx.opcode), little_endian ? "little" : "big"); 8255 opc3(ctx.opcode), little_endian ? "little" : "big");
8254 - }  
8255 -#endif  
8256 ctx.nip += 4; 8256 ctx.nip += 4;
8257 table = env->opcodes; 8257 table = env->opcodes;
8258 num_insns++; 8258 num_insns++;
@@ -154,6 +154,16 @@ @@ -154,6 +154,16 @@
154 //#define DEBUG_NET 154 //#define DEBUG_NET
155 //#define DEBUG_SLIRP 155 //#define DEBUG_SLIRP
156 156
  157 +
  158 +#ifdef DEBUG_IOPORT
  159 +# define LOG_IOPORT(...) do { \
  160 + if (loglevel & CPU_LOG_IOPORT) \
  161 + fprintf(logfile, ## __VA_ARGS__); \
  162 + } while (0)
  163 +#else
  164 +# define LOG_IOPORT(...) do { } while (0)
  165 +#endif
  166 +
157 #ifdef TARGET_PPC 167 #ifdef TARGET_PPC
158 #define DEFAULT_RAM_SIZE 144 168 #define DEFAULT_RAM_SIZE 144
159 #else 169 #else
@@ -409,10 +419,7 @@ void isa_unassign_ioport(int start, int length) @@ -409,10 +419,7 @@ void isa_unassign_ioport(int start, int length)
409 419
410 void cpu_outb(CPUState *env, int addr, int val) 420 void cpu_outb(CPUState *env, int addr, int val)
411 { 421 {
412 -#ifdef DEBUG_IOPORT  
413 - if (loglevel & CPU_LOG_IOPORT)  
414 - fprintf(logfile, "outb: %04x %02x\n", addr, val);  
415 -#endif 422 + LOG_IOPORT("outb: %04x %02x\n", addr, val);
416 ioport_write(0, addr, val); 423 ioport_write(0, addr, val);
417 #ifdef USE_KQEMU 424 #ifdef USE_KQEMU
418 if (env) 425 if (env)
@@ -422,10 +429,7 @@ void cpu_outb(CPUState *env, int addr, int val) @@ -422,10 +429,7 @@ void cpu_outb(CPUState *env, int addr, int val)
422 429
423 void cpu_outw(CPUState *env, int addr, int val) 430 void cpu_outw(CPUState *env, int addr, int val)
424 { 431 {
425 -#ifdef DEBUG_IOPORT  
426 - if (loglevel & CPU_LOG_IOPORT)  
427 - fprintf(logfile, "outw: %04x %04x\n", addr, val);  
428 -#endif 432 + LOG_IOPORT("outw: %04x %04x\n", addr, val);
429 ioport_write(1, addr, val); 433 ioport_write(1, addr, val);
430 #ifdef USE_KQEMU 434 #ifdef USE_KQEMU
431 if (env) 435 if (env)
@@ -435,10 +439,7 @@ void cpu_outw(CPUState *env, int addr, int val) @@ -435,10 +439,7 @@ void cpu_outw(CPUState *env, int addr, int val)
435 439
436 void cpu_outl(CPUState *env, int addr, int val) 440 void cpu_outl(CPUState *env, int addr, int val)
437 { 441 {
438 -#ifdef DEBUG_IOPORT  
439 - if (loglevel & CPU_LOG_IOPORT)  
440 - fprintf(logfile, "outl: %04x %08x\n", addr, val);  
441 -#endif 442 + LOG_IOPORT("outl: %04x %08x\n", addr, val);
442 ioport_write(2, addr, val); 443 ioport_write(2, addr, val);
443 #ifdef USE_KQEMU 444 #ifdef USE_KQEMU
444 if (env) 445 if (env)
@@ -450,10 +451,7 @@ int cpu_inb(CPUState *env, int addr) @@ -450,10 +451,7 @@ int cpu_inb(CPUState *env, int addr)
450 { 451 {
451 int val; 452 int val;
452 val = ioport_read(0, addr); 453 val = ioport_read(0, addr);
453 -#ifdef DEBUG_IOPORT  
454 - if (loglevel & CPU_LOG_IOPORT)  
455 - fprintf(logfile, "inb : %04x %02x\n", addr, val);  
456 -#endif 454 + LOG_IOPORT("inb : %04x %02x\n", addr, val);
457 #ifdef USE_KQEMU 455 #ifdef USE_KQEMU
458 if (env) 456 if (env)
459 env->last_io_time = cpu_get_time_fast(); 457 env->last_io_time = cpu_get_time_fast();
@@ -465,10 +463,7 @@ int cpu_inw(CPUState *env, int addr) @@ -465,10 +463,7 @@ int cpu_inw(CPUState *env, int addr)
465 { 463 {
466 int val; 464 int val;
467 val = ioport_read(1, addr); 465 val = ioport_read(1, addr);
468 -#ifdef DEBUG_IOPORT  
469 - if (loglevel & CPU_LOG_IOPORT)  
470 - fprintf(logfile, "inw : %04x %04x\n", addr, val);  
471 -#endif 466 + LOG_IOPORT("inw : %04x %04x\n", addr, val);
472 #ifdef USE_KQEMU 467 #ifdef USE_KQEMU
473 if (env) 468 if (env)
474 env->last_io_time = cpu_get_time_fast(); 469 env->last_io_time = cpu_get_time_fast();
@@ -480,10 +475,7 @@ int cpu_inl(CPUState *env, int addr) @@ -480,10 +475,7 @@ int cpu_inl(CPUState *env, int addr)
480 { 475 {
481 int val; 476 int val;
482 val = ioport_read(2, addr); 477 val = ioport_read(2, addr);
483 -#ifdef DEBUG_IOPORT  
484 - if (loglevel & CPU_LOG_IOPORT)  
485 - fprintf(logfile, "inl : %04x %08x\n", addr, val);  
486 -#endif 478 + LOG_IOPORT("inl : %04x %08x\n", addr, val);
487 #ifdef USE_KQEMU 479 #ifdef USE_KQEMU
488 if (env) 480 if (env)
489 env->last_io_time = cpu_get_time_fast(); 481 env->last_io_time = cpu_get_time_fast();